Abstract: An electronic device and associated methods are disclosed. In one example, the electronic device includes one or more ribbon bond connections along with one or more wire bond connections. In one example, ribbon bond connections are shown, and are coupled to ground, and configured to provide a shielding effect to wire bond connections.

Abstract: A microelectronic component and a method of forming same. The microelectronic component includes: a first substrate having first through vias therein, the first substrate including silicon or glass; a first layer on a front surface of the first substrate and including one or more first dies coupled to the first through vias; a second substrate on a front surface of first layer and having second through vias therein and including silicon or glass; a second layer on a front surface of the second substrate, the first layer between the first substrate and the second substrate, the second layer including one or more second dies coupled to the second through vias; and electrically conductive structures on a back surface of the first substrate coupled to the first through vias.

Abstract: Embodiments of the invention include device packages and methods of forming such packages. In an embodiment, the method of forming a device package may comprise forming a reinforcement layer over a substrate. One or more openings may be formed through the reinforcement layer. In an embodiment, a device die may be placed into one of the openings. The device die may be bonded to the substrate by reflowing one or more solder bumps positioned between the device die and the substrate. Embodiments of the invention may include a molded reinforcement layer. Alternative embodiments include a reinforcement layer that is adhered to the surface of the substrate with an adhesive layer.

Abstract: Disclosed herein are microelectronic structures including bridges, as well as related assemblies and methods. In some embodiments, a microelectronic structure may include a substrate and a bridge.

Abstract: Multi-die composite packages including directly bonded IC die and at least one electro-thermo-mechanical die (ETMD). An ETMD is distinguished from an active IC die as an ETMD is a passive die lacking any semiconductor devices, such as transistors. In exemplary embodiments, an ETMD includes a substrate, which may be a crystalline semiconductor material, for example, and one or more through substrate vias (TSVs) passing through a thickness of the substrate. The TSVs may enable a ETMD to electrically interconnect an (active) IC die of a composite package to another IC die of the package or to a package host.

Abstract: A packaged device comprises first die stack and a third die. The first die stack includes a first die comprising first conductive contacts each at a first side of the first die, and a second die comprising second conductive contacts each at a second side of the second die. First solder bonds which each extend to a respective one of the first conductive contacts. The third die comprises third conductive contacts each at a third side of the third die. The third die is coupled to the first die stack via second solder bonds which each extend to a respective one of the second conductive contacts, and to a respective one of the third conductive contacts. Each die of the first die stack is coupled to each of a respective one or more other dies of the first die stack via respective hybrid bonds.

Abstract: Embodiments disclosed herein include semiconductor devices. In an embodiment, a die comprises a substrate, where the substrate comprises a semiconductor material. In an embodiment a fiducial is on the substrate. In an embodiment, the fiducial is a cantilever beam that extends out past an edge of the substrate.

Abstract: An integrated circuit (IC) package comprises a first IC die comprising a first hardware interface at a first side of the first die, and one or more first conductive contacts at the first side. A second IC die coupled to the first die comprises a second hardware interface at a second side of the second die. Second conductive contacts of the first hardware interface are each in direct contact with a respective one of third conductive contacts of the second hardware interface. A third hardware interface comprises: one or more interconnect structures, each coupled to a respective one of the one or more first conductive contacts and each comprising a fourth conductive contact, and fifth conductive contacts at a third side of the second die, wherein the one or more interconnect structures are each to electrically couple the third hardware interface to the first die.

Abstract: Embodiments disclosed herein include semiconductor devices. In one embodiment, a die comprises a substrate, where the substrate comprises a semiconductor material. In an embodiment, a backend layer is over the substrate, where the backend layer comprises conductive routing. In an embodiment, the die further comprises a protrusion extending out from an edge of the substrate and the backend layer. In an embodiment, a fiducial is on a surface of the protrusion.

Abstract: Embodiments disclosed herein include die modules and methods of making die modules. In an embodiment, a die module comprises a first die with a set of first pads with surfaces that are substantially coplanar with a surface of a first dielectric layer. In an embodiment, the die module further comprises a second die with a set of second pads with surfaces that are substantially coplanar with a surface of a second dielectric layer. In an embodiment the first pads are bonded to the second pads and the first dielectric layer is bonded to the second dielectric layer.

Abstract: Embodiments herein relate to systems, apparatuses, or processes for attaching dummy dies to a wafer that includes a plurality of active dies, where the dummy dies are placed along or in dicing streets where the wafer is to be cut during singulation. In embodiments, the dummy dies may be attached to the wafer using a die attach film, or may be attached using hybrid bonding. Other embodiments may be described and/or claimed.

Abstract: Integrated circuit assemblies can be fabricated on a wafer scale, wherein a base template, having a plurality of openings, may cover a base substrate, such as a die wafer, wherein the base substrate has a plurality of first integrated circuit devices formed therein and wherein at least one second integrated circuit device is electrically attached to a corresponding first integrated circuit device through a respective opening in the base template. Thus, when the base substrate and base template are singulated into individual integrated circuit assemblies, the individual integrated circuit assemblies will each have a first integrated circuit that is edge aligned to a singulated portion of the base template. The singulated portion of the base template can provide an improved thermal path, mechanical strength, and/or electrical paths for the individual integrated circuit assemblies.

Abstract: Techniques and mechanisms for a reconstituted circuit device to be formed using a flow of material, by capillary action, in a region between a first die and a second die. In an embodiment, a rigid mass extends around, and between, the first die and the second die. The rigid mass comprises a first body of a first material, and a second body of second material, wherein the bodies each extend across the region to respective sidewall structures of the first and second dies. In the region, a portion of the first body forms a surface structure which adjoins the second body. A concave or convex shape of the surface structure is an artefact of a meniscus formed by the first material during a liquid state thereof. In another embodiment, the reconstituted circuit device further comprises an interconnect which adjoins, and extends through, the rigid mass.

Abstract: Integrated circuit assemblies can be fabricated on a wafer scale, wherein a base template, having a plurality of openings, may cover a base substrate, such as a die wafer, wherein the base substrate has a plurality of first integrated circuit devices formed therein and wherein at least one second integrated circuit device is electrically attached to a corresponding first integrated circuit device through a respective opening in the base template. Thus, when the base substrate and base template are singulated into individual integrated circuit assemblies, the individual integrated circuit assemblies will each have a first integrated circuit that is edge aligned to a singulated portion of the base template. The singulated portion of the base template can provide an improved thermal path, mechanical strength, and/or electrical paths for the individual integrated circuit assemblies.

Abstract: Stacked die assemblies having a moisture sealant layer according to embodiments are described herein. A microelectronic package structure having a first die with a second and an adjacent third die on the first die. Each of the second and third die comprise hybrid bonding interfaces with the first die. A first layer is on a region of the first die adjacent sidewalls of the second and the third dies, and adjacent an edge portion of the first die. The first layer comprises a diffusion barrier material A second layer is over the first layer, the second layer, wherein a top surface of the second layer is substantially coplanar with the top surfaces of the second and third dies. The first layer provides a hermetic moisture sealant layer for stacked die package structures.

Abstract: An electronic assembly that includes a substrate having an upper surface and a bridge that includes an upper surface. The bridge is within a cavity in the upper surface of the substrate. A first electronic component is attached to the upper surface of the bridge and the upper surface of the substrate and a second electronic component is attached to the upper surface of the bridge and the upper surface of the substrate, wherein the bridge electrically connects the first electronic component to the second electronic component.

Abstract: Microelectronic assemblies including photonic integrated circuits (PICs), related devices and methods, are disclosed herein. For example, in some embodiments, a photonic assembly may include a PIC in a first layer including an insulating material, wherein the PIC has an active surface and an opposing backside, and wherein the PIC is embedded in the insulating material with the active surface facing up; a conductive pillar in the first layer; an integrated circuit (IC) in a second layer, wherein the second layer is on the first layer and the second layer includes the insulating material, wherein the IC is embedded in the insulating material in the second layer, and wherein the IC is electrically coupled to the active surface of the PIC and the conductive pillar; and an optical component optically coupled to the active surface of the PIC and extending through the insulating material in the second layer.

Abstract: Microelectronic assemblies including photonic integrated circuits (PICs), related devices and methods, are disclosed herein. For example, in some embodiments, a photonic assembly may include a PIC in a first layer including an insulating material, wherein the PIC has an active side and an opposing backside, and wherein the PIC is embedded in the insulating material with the active side facing up; an optical component optically coupled to the active surface of the PIC and extending at least partially through the first layer; and an integrated circuit (IC) in a second layer, wherein the second layer is on the first layer, wherein the second layer includes the insulating material, wherein the IC is embedded in the insulating material in the second layer, and wherein the IC is electrically coupled to the active side of the PIC.

Abstract: Microelectronic assemblies including photonic integrated circuits (PICs), related devices and methods, are disclosed herein. For example, in some embodiments, a photonic assembly may include a PIC in a first layer including an insulating material, wherein the PIC is embedded in the insulating material with an active surface facing up; a conductive pillar in the first layer; an integrated circuit (IC) in a second layer on the first layer, wherein the second layer includes the insulating material and the IC is embedded in the insulating material, and wherein the IC is electrically coupled to the active surface of the PIC and the conductive pillar; an optical component optically coupled to the active surface of the PIC; and a hollow channel surrounding the optical component, the hollow channel extending from the active surface of the PIC through the insulating material in the second layer.

Abstract: Microelectronic assemblies including photonic integrated circuits (PICs), related devices and methods, are disclosed herein. For example, in some embodiments, a photonic assembly may include a PIC in a first layer having a first surface and an opposing second surface, wherein the first layer includes an insulating material, wherein the PIC has an active side, an opposing backside, and a lateral side substantially perpendicular to the active side and backside, and wherein the PIC is embedded in the insulating material with the active side facing up; an integrated circuit (IC) in a second layer at the second surface of the first layer, wherein the IC is electrically coupled to the active side of the PIC; and an optical component, having a reflector, optically coupled to the lateral side of the PIC and extending at least partially through the insulating material in the first layer along the lateral side of the PIC.