Patents by Inventor Noboru Matsuda

Noboru Matsuda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20160026932
    Abstract: A computer-implemented method includes, in one aspect, obtaining data specifying one or more expressions for a problem to be solved and an action that changes a state of the problem when applied to the one or more expressions, identifying one or more features of the one or more expressions, identifying a precondition for applying the action that changes the state of the problem, identifying a sequence of operator functions, and generating a production rule based on the identified one or more features, the identified precondition, and the identified operator function.
    Type: Application
    Filed: July 24, 2015
    Publication date: January 28, 2016
    Inventors: Nan Li, William R. Cohen, Kenneth R. Koedinger, Noboru Matsuda
  • Patent number: 9214130
    Abstract: A display device of at least one embodiment of the present invention is a display device of an active matrix type, and includes a display driver supplied with image data included in serial data by serial transmission. The serial data is provided with a first flag for specifying a polarity of voltage of a common electrode. The display driver extracts the first flag from the serial data in accordance with a timing of a serial clock, and performs display in accordance with the image data, while generating the voltage of the common electrode which voltage has the polarity specified by the first flag extracted. This realizes a display device capable of generating a timing signal for AC common voltage, while having a small circuit.
    Type: Grant
    Filed: January 19, 2009
    Date of Patent: December 15, 2015
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Noboru Matsuda, Takahiro Yamaguchi, Isao Takahashi
  • Patent number: 8692758
    Abstract: A display device of an embodiment of the present invention is a display device of an active matrix type, and includes a display driver supplied with image data included in serial data by serial transmission. The serial data has a first flag for specifying a polarity of voltage of a common electrode added thereto. The display driver generates, in accordance with a timing of a serial clock, a timing signal for a horizontal period for a data signal line driver, and a timing signal for a gate signal line driver. This realizes a display device capable of easily generating, within a driver IC, a timing signal for writing the image data in pixels.
    Type: Grant
    Filed: January 29, 2009
    Date of Patent: April 8, 2014
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Noboru Matsuda, Isao Takahashi, Takahiro Yamaguchi
  • Patent number: 8426068
    Abstract: A metal foil for secondary battery generating less cutting chips at the time of forming an opening and allowed to have a higher aperture ratio without reducing strength and a secondary battery in which short circuit caused by generation of electrode debris can be suppressed are provided. A metal foil 1 for secondary battery is provided with a metal thin plate 2, plural first convex portions 3A formed on a first principal surface 2a of the thin plate 2 by plastic forming and plural second convex portions 3B formed on a second principal surface 2b opposite to the first principal surface 2a by the plastic forming, wherein the convex portions 3A and 3B each have an opening 31 of which aperture plane 31a is orthogonal or substantially orthogonal to the principal surfaces 2a and the 2b.
    Type: Grant
    Filed: September 13, 2010
    Date of Patent: April 23, 2013
    Assignee: Finecs Co., Ltd.
    Inventors: Noboru Matsuda, Hiroshi Furuki, Hideya Matsunaga
  • Patent number: 8421726
    Abstract: A liquid crystal display device of the present invention includes: an active matrix substrate; a counter substrate; and a liquid crystal layer (512) including light-diffusing liquid crystal that has (i) when no voltage is being applied thereto, a first display state in which the liquid crystal molecules are aligned irregularly, and (ii) when a voltage is being applied, a second display state in which the liquid crystal molecules are aligned regularly, the active matrix substrate having a first surface which is below a surface on which pixel electrodes (504) are provided, the first surface having a first region on which a gap between adjacent pixel electrodes (504) is projected, the first region having partial regions which orthogonally cross gate bus lines GL (501), source bus lines SL (502) being each provided in a second region at a location shifted from a corresponding one of the partial regions so that the source bus line SL (502) is covered by the adjacent pixel electrodes (504).
    Type: Grant
    Filed: May 28, 2009
    Date of Patent: April 16, 2013
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Yoshimizu Moriya, Hiroshi Yoshida, Noboru Matsuda
  • Publication number: 20120287110
    Abstract: In a liquid crystal display device, an in-phase signal or a reversed phase signal of a signal supplied to a counter electrode is supplied to a source bus line during a video signal unwritten period, where (i) a video signal written period represents a period during which a voltage is applied to a pixel electrode in accordance with a video signal to be supplied to the source bus line and (ii) the video signal unwritten period represents a period between end of the data written period and start of a next data written period. This allows an electronic potential difference between the source bus line and the counter electrode to be kept constant. It is therefore possible to attain a liquid crystal display device excellent in its display quality by preventing flickers from being generated between a source bus line and a counter electrode.
    Type: Application
    Filed: October 22, 2010
    Publication date: November 15, 2012
    Applicant: SHARP KABUSHIKI KAISHA
    Inventors: Takahiro Yamaguchi, Isao Takahashi, Seijirou Gyouten, Noboru Matsuda
  • Patent number: 8299523
    Abstract: In general, according to one embodiment, a semiconductor device includes a first electrode, a first and a second semiconductor layer of a first conductivity type, a third semiconductor layer of a second conductivity type, a fourth semiconductor layer of the first conductivity type in this order. A device region includes a gate electrode inside a first trench. A second trench having a ring-shaped structure forms a first region penetrating through the fourth and third semiconductor layers to the second semiconductor layer and including the device region inside and a second region surrounding the first region outside. A first opening is provided between adjacent ones of the first trenches. A second opening having a wider width than the first opening is provided in the first region outside the device region. A second electrode is electrically connected to the third and fourth semiconductor layers through the first and second openings.
    Type: Grant
    Filed: August 1, 2011
    Date of Patent: October 30, 2012
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kouta Tomita, Noboru Matsuda, Hideyuki Ura
  • Patent number: 8269272
    Abstract: According to one embodiment, a semiconductor device includes a first semiconductor layer of a first conductivity type, a second semiconductor layer, a third semiconductor layer, a fourth semiconductor layer, first trenches, a second trench, an insulating film, a gate electrode, a first main electrode, a second main electrode, a channel stopper layer and a channel stopper electrode. The second semiconductor layer of the first conductivity type is provided on the first semiconductor layer. The third semiconductor layer of a second conductivity type is provided on the second semiconductor layer. The fourth semiconductor layer of the first conductivity type is provided on the third semiconductor layer. The gate electrode is provided in the first trenches via the insulating film. The first main electrode is provided on the first semiconductor layer. The second main electrode is provided to contact the element part. The channel stopper electrode is provided on the termination part.
    Type: Grant
    Filed: September 20, 2010
    Date of Patent: September 18, 2012
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kouta Tomita, Noboru Matsuda, Hideyuki Ura
  • Patent number: 8174479
    Abstract: In one embodiment of the present invention, the present shift register is a shift register provided in a display device by which a partial-screen display is available. The shift register includes a shift stopping circuit that is provided in an in-between stage, and stops operation of the shift register between a first stage and a last stage of the shift register in partial-screen display. The shift register also includes a circuit that is provided in a stage other than the in-between stage in such a manner that the circuit does not perform signal processing but serves as a signal path. The circuit is same as the shift stopping circuit in configuration. The foregoing allows improvement in display quality of the display device employing the present shift register.
    Type: Grant
    Filed: June 12, 2006
    Date of Patent: May 8, 2012
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Yuhichiroh Murakami, Seijirou Gyouten, Noboru Matsuda, Hajime Washio
  • Patent number: 8144103
    Abstract: A driving circuit of a display device is disclosed in accordance with an embodiment of the present invention creates a non-display area on a display section of the display device so that a partial-screen display becomes available. The driving circuit includes a shift register and a signal processing circuit that processes a signal tapped off from the shift register. In partial-screen display, the signal processing circuit interrupts a signal tapped off from a predetermined stage of the shift register. This makes it possible to realize a driving circuit of a display device by which a high-quality display is possible with a small circuit area.
    Type: Grant
    Filed: June 12, 2006
    Date of Patent: March 27, 2012
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Yuhichiroh Murakami, Seijirou Gyouten, Noboru Matsuda, Hajime Washio
  • Publication number: 20120025306
    Abstract: In general, according to one embodiment, a semiconductor device includes a first electrode, a first and a second semiconductor layer of a first conductivity type, a third semiconductor layer of a second conductivity type, a fourth semiconductor layer of the first conductivity type in this order. A device region includes a gate electrode inside a first trench. A second trench having a ring-shaped structure forms a first region penetrating through the fourth and third semiconductor layers to the second semiconductor layer and including the device region inside and a second region surrounding the first region outside. A first opening is provided between adjacent ones of the first trenches. A second opening having a wider width than the first opening is provided in the first region outside the device region. A second electrode is electrically connected to the third and fourth semiconductor layers through the first and second openings.
    Type: Application
    Filed: August 1, 2011
    Publication date: February 2, 2012
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Kouta TOMITA, Noboru MATSUDA, Hideyuki URA
  • Publication number: 20110311877
    Abstract: A metal foil for secondary battery generating less cutting chips at the time of forming an opening and allowed to have a higher aperture ratio without reducing strength and a secondary battery in which short circuit caused by generation of electrode debris can be suppressed are provided. A metal foil 1 for secondary battery is provided with a metal thin plate 2, plural first convex portions 3A formed on a first principal surface 2a of the thin plate 2 by plastic forming and plural second convex portions 3B formed on a second principal surface 2b opposite to the first principal surface 2a by the plastic forming, wherein the convex portions 3A and 3B each have an opening 31 of which aperture plane 31a is orthogonal or substantially orthogonal to the principal surfaces 2a and the 2b.
    Type: Application
    Filed: September 13, 2010
    Publication date: December 22, 2011
    Applicant: Finecs Co., Ltd.
    Inventors: Noboru Matsuda, Hiroshi Furuki, Hideya Matsunaga
  • Publication number: 20110242078
    Abstract: In a display panel having no black matrix in a picture-frame region, occurrence of flicker in the picture-frame region is suppressed. On a substrate constituting a liquid crystal panel, a peripheral electrode is formed in such a way as to cover at least a part of an electrical wiring line arranged in a picture-frame region facing a counter electrode with a liquid crystal layer therebetween. Also, a voltage generating circuit for providing a predetermined potential to the peripheral electrode is provided in the liquid crystal panel. A control signal, which is a binary signal, is provided to the voltage generating circuit from an external source. The voltage generating circuit provides a potential having a predetermined potential difference from a potential provided to the counter electrode, or a potential equal to the potential provided to the counter electrode, to the peripheral electrode according to a value of the control signal.
    Type: Application
    Filed: February 12, 2010
    Publication date: October 6, 2011
    Applicant: Sharp Kabushiki Kaisha
    Inventors: Isao Takahashi, Takahiro Yamaguchi, Shinya Takahashi, Noboru Matsuda
  • Publication number: 20110140197
    Abstract: According to one embodiment, a semiconductor device includes a first semiconductor layer of a first conductivity type, a second semiconductor layer, a third semiconductor layer, a fourth semiconductor layer, first trenches, a second trench, an insulating film, a gate electrode, a first main electrode, a second main electrode, a channel stopper layer and a channel stopper electrode. The second semiconductor layer of the first conductivity type is provided on the first semiconductor layer. The third semiconductor layer of a second conductivity type is provided on the second semiconductor layer. The fourth semiconductor layer of the first conductivity type is provided on the third semiconductor layer. The gate electrode is provided in the first trenches via the insulating film. The first main electrode is provided on the first semiconductor layer. The second main electrode is provided to contact the element part. The channel stopper electrode is provided on the termination part.
    Type: Application
    Filed: September 20, 2010
    Publication date: June 16, 2011
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Kouta Tomita, Noboru Matsuda, Hideyuki Ura
  • Publication number: 20110141096
    Abstract: A liquid crystal display device of the present invention includes: an active matrix substrate; a counter substrate; and a liquid crystal layer (512) including light-diffusing liquid crystal that has (i) when no voltage is being applied thereto, a first display state in which the liquid crystal molecules are aligned irregularly, and (ii) when a voltage is being applied, a second display state in which the liquid crystal molecules are aligned regularly, the active matrix substrate having a first surface which is below a surface on which pixel electrodes (504) are provided, the first surface having a first region on which a gap between adjacent pixel electrodes (504) is projected, the first region having partial regions which orthogonally cross gate bus lines GL (501), source bus lines SL (502) being each provided in a second region at a location shifted from a corresponding one of the partial regions so that the source bus line SL (502) is covered by the adjacent pixel electrodes (504).
    Type: Application
    Filed: May 28, 2009
    Publication date: June 16, 2011
    Inventors: Yoshimizu Moriya, Hiroshi Yoshida, Noboru Matsuda
  • Publication number: 20100309173
    Abstract: A display device of at least one embodiment of the present invention is a display device of an active matrix type, and includes a display driver supplied with image data included in serial data by serial transmission. The serial data is provided with a first flag for specifying a polarity of voltage of a common electrode. The display driver extracts the first flag from the serial data in accordance with a timing of a serial clock, and performs display in accordance with the image data, while generating the voltage of the common electrode which voltage has the polarity specified by the first flag extracted. This realizes a display device capable of generating a timing signal for AC common voltage, while having a small circuit.
    Type: Application
    Filed: January 19, 2009
    Publication date: December 9, 2010
    Inventors: Noboru Matsuda, Takahiro Yamaguchi, Isao Takahashi
  • Publication number: 20100295841
    Abstract: A display device of an embodiment of the present invention is a display device of an active matrix type, and includes a display driver supplied with image data included in serial data by serial transmission. The serial data has a first flag for specifying a polarity of voltage of a common electrode added thereto. The display driver generates, in accordance with a timing of a serial clock, a timing signal for a horizontal period for a data signal line driver, and a timing signal for a gate signal line driver. This realizes a display device capable of easily generating, within a driver IC, a timing signal for writing the image data in pixels.
    Type: Application
    Filed: January 29, 2009
    Publication date: November 25, 2010
    Inventors: Noboru Matsuda, Isao Takahashi, Takahiro Yamaguchi
  • Publication number: 20090115716
    Abstract: In one embodiment of the present invention, the present shift register is a shift register provided in a display device by which a partial-screen display is available. The shift register includes a shift stopping circuit that is provided in an in-between stage, and stops operation of the shift register between a first stage and a last stage of the shift register in partial-screen display. The shift register also includes a circuit that is provided in a stage other than the in-between stage in such a manner that the circuit does not perform signal processing but serves as a signal path. The circuit is same as the shift stopping circuit in configuration. The foregoing allows improvement in display quality of the display device employing the present shift register.
    Type: Application
    Filed: June 12, 2006
    Publication date: May 7, 2009
    Inventors: Yuhichiroh Murakami, Seijirou Gyouten, Noboru Matsuda, Hajime Washio
  • Publication number: 20090027318
    Abstract: A driving circuit of a display device is disclosed in accordance with an embodiment of the present invention creates a non-display area on a display section of the display device so that a partial-screen display becomes available. The driving circuit includes a shift register and a signal processing circuit that processes a signal tapped off from the shift register. In partial-screen display, the signal processing circuit interrupts a signal tapped off from a predetermined stage of the shift register. This makes it possible to realize a driving circuit of a display device by which a high-quality display is possible with a small circuit area.
    Type: Application
    Filed: June 12, 2006
    Publication date: January 29, 2009
    Inventors: Yuhichiroh Murakami, Seijirou Gyouten, Noboru Matsuda
  • Patent number: RE48259
    Abstract: In general, according to one embodiment, a semiconductor device includes a first electrode, a first and a second semiconductor layer of a first conductivity type, a third semiconductor layer of a second conductivity type, a fourth semiconductor layer of the first conductivity type in this order. A device region includes a gate electrode inside a first trench. A second trench having a ring-shaped structure forms a first region penetrating through the fourth and third semiconductor layers to the second semiconductor layer and including the device region inside and a second region surrounding the first region outside. A first opening is provided between adjacent ones of the first trenches. A second opening having a wider width than the first opening is provided in the first region outside the device region. A second electrode is electrically connected to the third and fourth semiconductor layers through the first and second openings.
    Type: Grant
    Filed: October 29, 2014
    Date of Patent: October 13, 2020
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Kouta Tomita, Noboru Matsuda, Hideyuki Ura