Abstract: A driving circuit of a display device is disclosed in accordance with an embodiment of the present invention creates a non-display area on a display section of the display device so that a partial-screen display becomes available. The driving circuit includes a shift register and a signal processing circuit that processes a signal tapped off from the shift register. In partial-screen display, the signal processing circuit interrupts a signal tapped off from a predetermined stage of the shift register. This makes it possible to realize a driving circuit of a display device by which a high-quality display is possible with a small circuit area.

Abstract: A method for manufacturing a trench type power semiconductor device is provided. The method includes: forming a first silicon oxide film on a silicon substrate; forming a thermal oxidation-resistant film on the first silicon oxide film; forming an opening in the first silicon oxide film and the thermal oxidation-resistant film; forming a sidewall on an inner side surface of the opening; forming a trench in the silicon substrate by etching the silicon substrate using the first silicon oxide film, the thermal oxidation-resistant film, and the sidewall as a mask; removing the sidewall; forming a second silicon oxide film thicker than the first silicon oxide film on an inner surface of the trench by applying thermal oxidation to the silicon substrate; burying a trench gate electrode in the trench; removing the thermal oxidation-resistant film; and introducing impurities into at least part of a region of the silicon substrate between the trenches.

Abstract: A semiconductor device comprises: a first semiconductor region of a first conductivity type; a second semiconductor region of a second conductivity type provided on the first semiconductor region; a trench formed in the second semiconductor region; a thick gate insulating film selectively provided in a center area of a bottom surface of the trench; a thin gate insulating film provided along a periphery of the bottom surface and on a sidewall of the trench; a third semiconductor region of the first conductivity type that is selectively provided below the thin gate insulating film provided along the periphery of the bottom surface of the trench and that extends to the first semiconductor region; a fourth semiconductor region of the first conductivity type selectively provided in the surface of the second semiconductor region; and a gate electrode filling the trench via the gate insulating film.

Abstract: A semiconductor device, and particularly an MOS transistor device, wherein in order to increase a channel region density and to achieve a low resistance of a transistor device there is provided a first gate electrode group having a plurality of gate electrodes formed on a semiconductor substrate to be away from each other at first equal spacings, a second gate electrode group having a plurality of gate electrodes formed on the semiconductor substrate to be away from each other at the first equal spacings, a source contact portion formed away from the first or the second gate electrode group at a second spacing, and source regions for electrically interconnecting the first gate electrode group and the source contact. The source regions are connected to each other at one end of the first gate electrode group, and separated at the other end of the first gate electrode group. In addition, the gate electrodes of the first group are connected each other at the other end.

Abstract: A power semiconductor device comprises a semiconductor layer; a polysilicon-containing gate; a first semiconductor region formed in said semiconductor layer at one surface of said semiconductor layer and operative to serve as at least one of a source region and an emitter region; a second semiconductor region formed in said semiconductor layer at the other surface of said semiconductor layer and operative to serve as at least one of a drain region and a collector region; a gate routing wire commonly connected to a plurality of said gates and including a polysilicon portion and a metal portion formed adjacent to it in the direction of plane of said semiconductor layer; an interlayer insulator film formed to cover said first semiconductor region, said gate routing wire and a plurality of said gates; an electrode portion formed in said interlayer insulator film and connected to said first semiconductor region; and a strap electrode plate located to cover said interlayer insulator on said gate routing wire and co

Abstract: A source driver of the present invention includes a bypass switch which connects two source lines with each other. A video signal to one of the source lines is simultaneously supplied to the other source line. The source driver is thus capable of indirectly transmitting a video signal of a video line, supplied to one source line, to the other source line. Therefore, according to the source driver, it is possible to transmit video signals on fewer image lines than the number of source lines. As a result, it is possible to significantly lower power consumption.

Abstract: A semiconductor device comprises: a first semiconductor layer of a first conductivity type; a second semiconductor layer of a second conductivity type; a trench; a thick gate insulating film; a thin gate insulating film; a gate electrode; and a semiconductor region of a second conductivity type. The second semiconductor layer is provided on the first semiconductor layer. The trench penetrates the second semiconductor layer and intrudes into the first semiconductor layer. The thick gate insulating film is provided on a inner wall of the trench below an upper surface of the first semiconductor layer. The thin gate insulating film is provided on the inner wall of the trench at a part upper than the thick gate insulating film. The gate electrode fills the trench. The semiconductor region of a second conductivity type is selectively formed to adjoin the trench and to project from a bottom surface of the second semiconductor layer into the first semiconductor layer.

Abstract: There is provided a semiconductor device comprising a first semiconductor layer of a first conductivity type, a second semiconductor layer of a second conductivity type formed on the first semiconductor layer, the second conductivity type being different from the first conductivity type, a third semiconductor layer of the first conductivity type selectively formed on the second semiconductor layer, a trench formed through the third semiconductor layer and the second semiconductor layer to reach the first semiconductor layer, a gate dielectric film formed along side and bottom surfaces of the trench, and a gate electrode formed to be in contact with the gate dielectric film at the side surfaces of the trench, surfaces of the gate electrode that are opposite to the surfaces contacting the gate dielectric film, and the gate dielectric film at a bottom of the trench forming a hollow portion extending from the bottom to an opening side of the trench.

Abstract: A trench MIS device includes a drain region, a base region disposed on the drain region, the base region having a channel face, a source region disposed on the base region, the source region having a source end face, the source end face being continuous with the channel face, a gate insulator disposed along the channel face and the source end face, a gate electrode disposed opposite to the channel face through the gate insulator, and a cavity portion provided in the drain region, the cavity portion being opposite to the gate electrode.

Abstract: A semiconductor device comprises: a first semiconductor region of a first conductivity type; a second semiconductor region of a second conductivity type provided on the first semiconductor region; a trench formed in the second semiconductor region; a thick gate insulating film selectively provided in a center area of a bottom surface of the trench; a thin gate insulating film provided along a periphery of the bottom surface and on a sidewall of the trench; a third semiconductor region of the first conductivity type that is selectively provided below the thin gate insulating film provided along the periphery of the bottom surface of the trench and that extends to the first semiconductor region; a fourth semiconductor region of the first conductivity type selectively provided in the surface of the second semiconductor region; and a gate electrode filling the trench via the gate insulating film.

Abstract: A power semiconductor device comprises a semiconductor layer; a polysilicon-containing gate; a first semiconductor region formed in said semiconductor layer at one surface of said semiconductor layer and operative to serve as at least one of a source region and an emitter region; a second semiconductor region formed in said semiconductor layer at the other surface of said semiconductor layer and operative to serve as at least one of a drain region and a collector region; a gate routing wire commonly connected to a plurality of said gates and including a polysilicon portion and a metal portion formed adjacent to it in the direction of plane of said semiconductor layer; an interlayer insulator film formed to cover said first semiconductor region, said gate routing wire and a plurality of said gates; an electrode portion formed in said interlayer insulator film and connected to said first semiconductor region; and a strap electrode plate located to cover said interlayer insulator on said gate routing wire and co

Abstract: There is provided a semiconductor device comprising a first semiconductor layer of a first conductivity type, a second semiconductor layer of a second conductivity type formed on the first semiconductor layer, the second conductivity type being different from the first conductivity type, a third semiconductor layer of the first conductivity type selectively formed on the second semiconductor layer, a trench formed through the third semiconductor layer and the second semiconductor layer to reach the first semiconductor layer, a gate dielectric film formed along side and bottom surfaces of the trench, and a gate electrode formed to be in contact with the gate dielectric film at the side surfaces of the trench, surfaces of the gate electrode that are opposite to the surfaces contacting the gate dielectric film, and the gate dielectric film at a bottom of the trench forming a hollow portion extending from the bottom to an opening side of the trench.

Abstract: A semiconductor device comprises: a first semiconductor layer of a first conductivity type; a second semiconductor layer of a second conductivity type; a trench; a thick gate insulating film; a thin gate insulating film; a gate electrode; and a semiconductor region of a second conductivity type. The second semiconductor layer is provided on the first semiconductor layer. The trench penetrates the second semiconductor layer and intrudes into the first semiconductor layer. The thick gate insulating film is provided on a inner wall of the trench below an upper surface of the first semiconductor layer. The thin gate insulating film is provided on the inner wall of the trench at a part upper than the thick gate insulating film. The gate electrode fills the trench. The semiconductor region of a second conductivity type is selectively formed to adjoin the trench and to project from a bottom surface of the second semiconductor layer into the first semiconductor layer.

Abstract: A semiconductor device, and particularly an MOS transistor device, wherein in order to increase a channel region density and to achieve a low resistance of a transistor device there is provided a first gate electrode group having a plurality of gate electrodes formed on a semiconductor substrate to be away from each other at first equal spacings, a second gate electrode group having a plurality of gate electrodes formed on the semiconductor substrate to be away from each other at the first equal spacings, a source contact portion formed away from the first or the second gate electrode group at a second spacing, and source regions for electrically interconnecting the first gate electrode group and the source contact. The source regions are connected to each other at one end of the first gate electrode group, and separated at the other end of the first gate electrode group. In addition, the gate electrodes of the first group are connected each other at the other end.

Abstract: A source driver of the present invention includes a bypass switch which connects two source lines with each other. A video signal to one of the source lines is simultaneously supplied to the other source line. The source driver is thus capable of indirectly transmitting a video signal of a video line, supplied to one source line, to the other source line. Therefore, according to the source driver, it is possible to transmit video signals on fewer image lines than the number of source lines. As a result, it is possible to significantly lower power consumption.

Abstract: A semiconductor device is characterized in that source electrode contact regions, each of which is formed of a first conductivity type source layer and a second conductivity type base layer in a surface of a semiconductor surface, are formed at respective intersectional points of a diagonally-arranged lattice, and in that a trench having a gate electrode buried therein is formed so as to snake through the contact regions alternately. By virtue of the structure, the trench arrangement and source/base simultaneous contact quality are improved, to thereby increase a trench density (channel density) per unit area.

Abstract: The present invention relates to a schottky-barrier diode capable of decreasing a leakage current due to damage generated on inner walls of trenches, and securing a large operation region for itself. In the device, an N.sup.- -type epitaxial layer is formed on a N.sup.+ -type silicon substrate. In a predetermined region in the epitaxial layer, a P.sup.+ -type base diffusion layer having high impurity concentration is formed. Trenches are formed through from the surface of the base diffusion layer to the epitaxial layer. In each of the trenches, an N.sup.- -type selective epitaxial growth region is formed. A schottky metal is formed on a surface comprising the surfaces of the base diffusion layer, which includes the selective epitaxial growth regions, and the epitaxial layer. Surface regions as the surfaces of the selective epitaxial growth regions filling the trenches function as diode operation regions.

Abstract: In a vertical field effect transistor having a trench gate and a method of manufacturing the same according to the present invention, p-type base and n.sup.+ -type source diffusion layers are formed in this order in a surface region of an n.sup.31 -type epitaxial layer on an n.sup.+ -type semiconductor substrate. A trench is then provided to such a depth as to penetrate the diffusion layers. A dope polysilicon layer is deposited and buried into the trench with a gate insulation film interposed between them. The polysilicon layer is etched to have the same level as that of the entrance of the trench, and a dope polysilicon layer 18 is selectively grown thereon, thereby forming a trench gate in which an upper corner portion of the trench is not covered with a gate electrode. Consequently, the concentration of electric fields at the corner portion can be mitigated thereby to increase an absolute withstand voltage of the gate and the variations in threshold voltage can be suppressed in a BT test.

Abstract: In a vertical power MOSFET having a U-shaped trench gate and a method of manufacturing the same, a P-type base layer and an N.sup.+ -type emitter layer are formed on the surface of an N-type semiconductor substrate. A plurality of trenches are formed to such a depth as to reach the semiconductor substrate. After that, an oxide film and a nitride film are formed in this order on the surface of the resultant element and on the inner surfaces of the trenches. In this case, the oxide film and nitride film are each formed to have a thickness corresponding to the operating characteristics of the element at the stage of design. The nitride film of a gate wiring region is selectively removed to form an oxide film on the surface of the element. Consequently, a thick gate insulation film of the oxide films can be formed between the corner portions of the N.sup.

Abstract: In a vertical power MOSFET having a U-shaped trench gate and a method of manufacturing the same, a P-type base layer and an N.sup.+ -type emitter layer are formed on the surface of an N-type semiconductor substrate. A plurality of trenches are formed to such a depth as to reach the semiconductor substrate. After that, an oxide film and a nitride film are formed in this order on the surface of the resultant element and on the inner surfaces of the trenches. In this case, the oxide film and nitride film are each formed to have a thickness corresponding to the operating characteristics of the element at the stage of design. The nitride film of a gate wiring region is selectively removed to form an oxide film on the surface of the element. Consequently, a thick gate insulation film of the oxide films can be formed between the corner portions of the N.sup.