Patents by Inventor Noboru Morita

Noboru Morita has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8254472
    Abstract: A communication device includes a storage unit that stores a predetermined eye mask pattern indicating a receivable range, a receiving unit that receives data from the other communication device, a waveform comparing unit for comparing a waveform of the received data with the eye mask pattern to generate comparison result data and a transmission unit for transmitting the comparison result data to the other communication device.
    Type: Grant
    Filed: February 1, 2010
    Date of Patent: August 28, 2012
    Assignee: Fujitsu Limited
    Inventors: Noboru Morita, Michio Hibi, Manabu Yamazaki
  • Patent number: 7910474
    Abstract: An object of the present invention is to provide a semiconductor device which comprises a barrier film having a high etching selection ratio of the interlayer insulating film thereto, a good preventive function against the Cu diffusion, a low dielectric constant and excellent adhesiveness to the Cu interconnection and a manufacturing method thereof.
    Type: Grant
    Filed: April 4, 2008
    Date of Patent: March 22, 2011
    Assignees: NEC Corporation, Renesas Electronics Corporation
    Inventors: Tatsuya Usami, Noboru Morita, Koichi Ohto, Kazuhiko Endo
  • Patent number: 7833901
    Abstract: In a method of manufacturing a semiconductor device where at least one insulating layer structure having a metal wiring constitution is formed to thereby construct a multi-layered wiring arrangement, a first SiOCH layer is produced. Then, a surface section of the first SiOCH layer is treated to change the surface section of the first SiOCH layer to a second SiOCH layer which features a carbon (C) density lower than that of the first SiOCH layer, a hydrogen (H) density lower than that of the first SiOCH layer and an oxygen (O) density higher than that of the first SiOCH layer. Finally, a silicon dioxide (SiO2) layer is formed on the second SiOCH layer.
    Type: Grant
    Filed: November 2, 2006
    Date of Patent: November 16, 2010
    Assignee: NEC Electronics Corporation
    Inventors: Koichi Ohto, Tatsuya Usami, Noboru Morita, Sadayuki Ohnishi, Koji Arita, Ryohei Kitao, Yoichi Sasaki
  • Patent number: 7763979
    Abstract: The dielectric constants of SiC and SiCN that are currently the subjects of much investigation are both 4.5 to 5 or so and that of SiOC, 2.8 to 3.0 or so. With further miniaturization of the interconnection size and the spacing of interconnections brought about by the reduction in device size, there have arisen strong demands that dielectric constants should be further reduced. Furthermore, because the etching selection ratio of SiOC to SiCN as well as that of SiOC to SiC are small, if SiCN or SiC is used as the etching stopper film, the surface of the metal interconnection layer may be oxidized at the time of photoresist removal, which gives rise to a problem of high contact resistance.
    Type: Grant
    Filed: September 25, 2006
    Date of Patent: July 27, 2010
    Assignees: NEC Electronics Corporation, NEC Corporation
    Inventors: Koichi Ohto, Tatsuya Usami, Noboru Morita, Kazuhiko Endo
  • Publication number: 20100128763
    Abstract: A communication device includes a storage unit that stores a predetermined eye mask pattern indicating a receivable range, a receiving unit that receives data from the other communication device, a waveform comparing unit for comparing a waveform of the received data with the eye mask pattern to generate comparison result data and a transmission unit for transmitting the comparison result data to the other communication device.
    Type: Application
    Filed: February 1, 2010
    Publication date: May 27, 2010
    Applicant: FUJITSU LIMITED
    Inventors: Noboru Morita, Michio Hibi, Manabu Yamazaki
  • Patent number: 7634524
    Abstract: A cyclic equation setting unit transforms and sets a Taylor series equation for calculating a sine function into a single cyclic equation common to terms of the Taylor series equation, the single cyclic equation having a new known number Q that is defined by multiplying a known number Q and the square of a variable X, shifting the result by a shift number S and then adding a constant K thereto. An adjustment unit adjusts and prepares the shift number S such that within a variation range of the variable X the variable X has a maximum value 1 with the constant K being not greater than 1. A cyclic equation executing unit inputs and converts angle information i to the variable X, and executing the cyclic equation in sequence from higher order term to lower order term for the number of terms of the Taylor series equation to derive a sine function of the angle information i.
    Type: Grant
    Filed: April 14, 2004
    Date of Patent: December 15, 2009
    Assignee: Fujitsu Limited
    Inventors: Shigeaki Okutani, Toshiro Nakazuru, Noboru Morita
  • Patent number: 7620676
    Abstract: Input data is divided into a plurality of blocks, and the blocks are corresponded to each address of the lookup table, and a block is divided into a plurality of sections according to the change of the output data, and at this time position information to indicates the boundary of the section, and output data in each section are stored in an address corresponding to each block, so that the memory capacity required for the lookup table can be decreased.
    Type: Grant
    Filed: February 3, 2006
    Date of Patent: November 17, 2009
    Assignee: Fujitsu Limited
    Inventors: Shigeaki Okutani, Toshiro Nakazuru, Noboru Morita
  • Patent number: 7615498
    Abstract: A semiconductor device 200 comprises a SiCN film 202 formed on a semiconductor substrate (not shown), a first SiOC film 204 formed thereon, a SiCN film 208 formed thereon, a second SiOC film 210 formed thereon, a SiO2 film 212 and a SiCN film 214 formed thereon. The first SiOC film 204 has a barrier metal layer 216 and via 218 formed therein, and the second SiOC film 210 has a barrier metal layer 220 and wiring metal layer 222 formed therein. Carbon content of the second SiOC film 210 is adjusted larger than that of the first SiOC film 204. This makes it possible to improve adhesiveness of the insulating interlayer with other insulating layers, while keeping a low dielectric constant of the insulating interlayer.
    Type: Grant
    Filed: January 19, 2007
    Date of Patent: November 10, 2009
    Assignee: NEC Electronics Corporation
    Inventors: Yoichi Sasaki, Koichi Ohto, Noboru Morita, Tatsuya Usami, Hidenobu Miyamoto
  • Patent number: 7582970
    Abstract: A semiconductor device includes an interlayer insulating film formed on or over a semiconductor substrate. An opening is formed in the interlayer insulating film and reaches a lower layer metal wiring conductor. A metal plug is formed by filling the opening with Cu containing metal via a barrier metal. The interlayer insulating film includes the insulating film which includes a carbon containing silicon oxide (SiOCH) film which has Si—CH2 bond in the carbon containing silicon oxide film. The proportion of Si—CH2 bond (1360 cm-1) to Si—CH3 bond (1270 cm-1) in the insulating film is in a range from 0.03 to 0.05 measured as a peak height ratio of FTIR spectrum.
    Type: Grant
    Filed: July 28, 2008
    Date of Patent: September 1, 2009
    Assignee: NEC Electronics Corporation
    Inventors: Sadayuki Ohnishi, Kouichi Owto, Tatsuya Usami, Noboru Morita, Kouji Arita, Ryouhei Kitao, Youichi Sasaki
  • Patent number: 7563705
    Abstract: A manufacturing method of a semiconductor device including a step of forming a via hole in an insulation layer including an organic low dielectric film, such as MSQ, SiC, and SiCN, and then embedding a wiring material in the via hole through a barrier metal. According to this method, a plasma treatment is performed after the via hole is formed and before the barrier metal is deposited, using a He/H2 gas capable of replacing groups (methyl groups) made of organic constituents and covering the surface of the exposed organic low dielectric film (MSQ) with hydrogen, or a He gas capable decomposing the groups (methyl groups) without removing organic low dielectric molecules. As a result, the surface of the low dielectric film (MSQ) is reformed to be hydrophilic and adhesion to the barrier metal is hence improved, thereby making it possible to prevent the occurrence of separation of the barrier metal and scratches.
    Type: Grant
    Filed: February 23, 2006
    Date of Patent: July 21, 2009
    Assignee: NEC Electronics Corporation
    Inventors: Takashi Tonegawa, Koji Arita, Tatsuya Usami, Noboru Morita, Koichi Ohto, Yoichi Sasaki, Sadayuki Ohnishi, Ryohei Kitao
  • Patent number: 7482263
    Abstract: An object of the present invention is to improve the inter-layer adhesiveness of the diffusion barrier film while maintaining the lower dielectric constant of the diffusion barrier film. A diffusion barrier film for a copper interconnect comprises an insulating material containing silicon, carbon, hydrogen and nitrogen as constituent elements, and also containing Si—H bond, Si—C bond and methylene bond (—CH2—). The insulating material involves I2/I1 of not lower than 0.067 and I3/I1 of not higher than 0.0067 appeared in an infrared absorption spectrum; where I1 is defined as an absorption area of the infrared absorption band having a peak near 810 cm?1, I2 is defined as an absorption area of the infrared absorption band having a peak near 2,120 cm?1 and I3 is defined as an absorption area of the infrared absorption band having a peak near 1,250 cm?1.
    Type: Grant
    Filed: March 22, 2006
    Date of Patent: January 27, 2009
    Assignee: NEC Electronics Corporation
    Inventors: Tatsuya Usami, Noboru Morita
  • Patent number: 7473630
    Abstract: A technology for inhibiting the dielectric breakdown occurred in a semiconductor device is provided. A semiconductor device includes a semiconductor substrate (not shown), an interlayer insulating film 102 formed on the semiconductor substrate and a multiple-layered insulating film 140 provided on the interlayer insulating film 102. The semiconductor device also includes an electric conductor that extends through the multiple-layered insulating film 140 and includes a Cu film 120 and a barrier metal film 118. The barrier metal film 118 is covers side surfaces and a bottom surface of the Cu film 120. An insulating film 116 is disposed between the multiple-layered insulating film 140 and the electric conductor (i.e., Cu film 120 and barrier metal film 118).
    Type: Grant
    Filed: October 4, 2006
    Date of Patent: January 6, 2009
    Assignee: NEC Electronics Corporation
    Inventors: Tatsuya Usami, Noboru Morita, Koichi Ohto
  • Patent number: 7461114
    Abstract: A Fourier transform apparatus whose pipeline width is independent of transform point number of individual pipeline FFT circuits in each stage and composed of a preceding stage and a succeeding stage. Each of the stages includes M(power of 2)-point radix 2 pipeline FFT circuits each having two-parallel inputs/outputs in a number of a (divisor of M) which are equal in respect to the transform point number and data permutating means for data supply to the transform means of each stage so that the pipeline width of the Fourier transform apparatus is made independent of the transform point numbers of the individual pipeline FFT circuits in each stage.
    Type: Grant
    Filed: August 22, 2003
    Date of Patent: December 2, 2008
    Assignee: Fujitsu Limited
    Inventors: Toshiro Nakazuru, Shigeaki Okutani, Noboru Morita
  • Publication number: 20080290522
    Abstract: A semiconductor device includes an interlayer insulating film formed on or over a semiconductor substrate. An opening is formed in the interlayer insulating film and reaches a lower layer metal wiring conductor. A metal plug is formed by filling the opening with Cu containing metal via a barrier metal. The interlayer insulating film includes the insulating film which includes a carbon containing silicon oxide (SiOCH) film which has Si—CH2 bond in the carbon containing silicon oxide film. The proportion of Si—CH2 bond (1360 cm-1) to Si—CH3 bond (1270 cm-1) in the insulating film is in a range from 0.03 to 0.05 measured as a peak height ratio of FTIR spectrum.
    Type: Application
    Filed: July 28, 2008
    Publication date: November 27, 2008
    Applicant: NEC ELECTRONICS CORPORATION
    Inventors: Sadayuki Ohnishi, Kouichi Owto, Tatsuya Usami, Noboru Morita, Kouji Arita, Ryouhei Kitao, Youichi Sasaki
  • Patent number: 7420279
    Abstract: An insulating film used for an interlayer insulating film of a semiconductor device and having a low dielectric constant. The insulating film comprises a carbon containing silicon oxide (SiOCH) film which has Si—CH2 bond therein. The proportion of Si—CH2 bond (1360 cm?1) to Si—CH3 bond (1270 cm?1) in the insulating film is preferably in a range from 0.03 to 0.05 measured as a peak height ratio of FTIR spectrum. The insulating film according to the present invention has higher ashing tolerance and improved adhesion to SiO2 film, when compared with the conventional SiOCH film which only has CH3 group.
    Type: Grant
    Filed: June 28, 2006
    Date of Patent: September 2, 2008
    Assignee: NEC Electronics Corporation
    Inventors: Sadayuki Ohnishi, Kouichi Ohto, Tatsuya Usami, Noboru Morita, Kouji Arita, Ryouhei Kitao, Youichi Sasaki
  • Publication number: 20080194102
    Abstract: An object of the present invention is to provide a semiconductor device which comprises a barrier film having a high etching selection ratio of the interlayer insulating film thereto, a good preventive function against the Cu diffusion, a low dielectric constant and excellent adhesiveness to the Cu interconnection and a manufacturing method thereof.
    Type: Application
    Filed: April 4, 2008
    Publication date: August 14, 2008
    Applicants: NEC ELECTRONICS CORPORATION, NEC CORPORATION
    Inventors: Tatsuya USAMI, Noboru MORITA, Koichi OHTO, Kazuhiko ENDO
  • Patent number: 7391115
    Abstract: An object of the present invention is to provide a semiconductor device which comprises a barrier film having a high etching selection ratio of the interlayer insulating film thereto, a good preventive function against the Cu diffusion, a low dielectric constant and excellent adhesiveness to the Cu interconnection and a manufacturing method thereof.
    Type: Grant
    Filed: February 2, 2004
    Date of Patent: June 24, 2008
    Assignees: NEC Electronics Corporation, NEC Corporation
    Inventors: Tatsuya Usami, Noboru Morita, Koichi Ohto, Kazuhiko Endo
  • Publication number: 20070246804
    Abstract: The dielectric constants of SiC and SiCN that are currently the subjects of much investigation are both 4.5 to 5 or so and that of SiOC, 2.8 to 3.0 or so. With further miniaturization of the interconnection size and the spacing of interconnections brought about by the reduction in device size, there have arisen strong demands that dielectric constants should be further reduced. Furthermore, because the etching selection ratio of SiOC to SiCN as well as that of SiOC to SiC are small, if SiCN or SiC is used as the etching stopper film, the surface of the metal interconnection layer may be oxidized at the time of photoresist removal, which gives rise to a problem of high contact resistance.
    Type: Application
    Filed: September 25, 2006
    Publication date: October 25, 2007
    Inventors: Koichi Ohto, Tatsuya Usami, Noboru Morita, Kazuhiko Endo
  • Publication number: 20070117405
    Abstract: A semiconductor device 200 comprises a SiCN film 202 formed on a semiconductor substrate (not shown), a first SiOC film 204 formed thereon, a SiCN film 208 formed thereon, a second SiOC film 210 formed thereon, a SiO2 film 212 and a SiCN film 214 formed thereon. The first SiOC film 204 has a barrier metal layer 216 and via 218 formed therein, and the second SiOC film 210 has a barrier metal layer 220 and wiring metal layer 222 formed therein. Carbon content of the second SiOC film 210 is adjusted larger than that of the first SiOC film 204. This makes it possible to improve adhesiveness of the insulating interlayer with other insulating layers, while keeping a low dielectric constant of the insulating interlayer.
    Type: Application
    Filed: January 19, 2007
    Publication date: May 24, 2007
    Applicant: NEC ELECTRONICS CORPORATION
    Inventors: Yoichi Sasaki, Koichi Ohto, Noboru Morita, Tatsuya Usami, Hidenobu Miyamoto
  • Publication number: 20070045861
    Abstract: A semiconductor device has a semiconductor substrate, and a multi-layered wiring arrangement provided thereon. The multi-layered wring arrangement includes at least one insulating layer structure having a metal wiring pattern formed therein. The insulating layer structure includes a first SiOCH layer, a second SiOCH layer formed on the first SiOCH layer, and a silicon dioxide (SiO2) layer formed on the second SiOCH layer. The second SiOCH layer features a carbon (C) density lower than that of the first SiOCH layer, a hydrogen (H) density lower than that of the first SiOCH layer, and an oxygen (O) density higher than that of the first SiOCH layer.
    Type: Application
    Filed: November 2, 2006
    Publication date: March 1, 2007
    Applicant: NEC Electronics Corporation
    Inventors: Koichi Ohto, Tatsuya Usami, Noboru Morita, Sadayuki Ohnishi, Koji Arita, Ryohei Kitao, Yoichi Sasaki