Patents by Inventor Nobuhiko Ito

Nobuhiko Ito has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20050135161
    Abstract: A semiconductor readout circuit reads out a potential of each of plural data lines by comparing the potential with a potential of a common reference data line, using a sense amplifier provided for each of the data lines. This semiconductor readout circuit has a current control circuit provided for each of the data lines. The current control circuit controls the potential of the corresponding one of the data lines so that a potential difference between the potential of the corresponding data line and the potential of the reference data line can be reduced based on an output as to the potential difference detected by the sense amplifier.
    Type: Application
    Filed: December 14, 2004
    Publication date: June 23, 2005
    Applicant: SHARP KABUSHIKI KAISHA
    Inventors: Nobuhiko Ito, Kaoru Yamamoto, Yoshimitsu Yamauchi
  • Publication number: 20050057993
    Abstract: A semiconductor memory device comprises: a plurality of memory elements; at least one bit line, wherein a memory operation is performed via at least a portion of the bit line with respect to at least one of the plurality of memory elements; and a load resistance regulating circuit for changing a resistance value to reduce or eliminate a difference in bit line load resistance depending on a position of the memory element.
    Type: Application
    Filed: September 3, 2004
    Publication date: March 17, 2005
    Inventors: Naoki Ueda, Nobuhiko Ito, Yoshimitsu Yamauchi
  • Patent number: 6744667
    Abstract: There is provided a virtual ground type nonvolatile semiconductor storage device capable of effectively suppressing a leak current to the adjacent cell and thereby achieving high-speed read. During read operation, a ground potential GND is applied to a bit line SBL5 connected to the source region of one memory cell transistor MC04 subjected to read. Moreover, a read drain bias potential Vread is applied to a bit line SBL4 connected to the drain region of the memory cell transistor MC04. A bit line SBL3 connected to the drain region of a first adjacent memory cell transistor MC03 is put into a floating state. A potential Vdb equal to the read drain bias potential Vread is applied to a bit line SBL2 connected to the drain region of a second adjacent memory cell transistor MC02.
    Type: Grant
    Filed: September 27, 2002
    Date of Patent: June 1, 2004
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Kaoru Yamamoto, Nobuhiko Ito
  • Patent number: 6643175
    Abstract: A control signal MBPRG is inputted to individual block decoders that constitute a block decoder section 37 of an ACT type flash memory. Then, the level of the control signal MBPRG is set to “H” to select all the blocks regardless of the contents of address signals a5 through a13, and one word line WL is selected from all the blocks by the addresses a0 through a4. By thus selecting one word line WL every block that is electrically separated by the select transistor and simultaneously applying a write voltage during the test to the same number of word lines WL as the number of blocks, the possible occurrence of a bad influence exerted on the other memory cells is prevented even when the memory cells in which a write operation during the test has been executed include a memory cell that has a negative threshold voltage.
    Type: Grant
    Filed: December 17, 2002
    Date of Patent: November 4, 2003
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Yoshimitsu Yamauchi, Nobuhiko Ito
  • Patent number: 6639089
    Abstract: Anticancer agents containing, as an active ingredient, at least one compound selected from the group consisting of &ohgr;-hydroxy fatty acids and salts or esters thereof, hydroxy oxo-fatty acids and salts or esters thereof, lactones, macrocyclic ketones, and macrocyclic diesters having specific chemical structures.
    Type: Grant
    Filed: July 2, 2002
    Date of Patent: October 28, 2003
    Assignee: Soda Aromatic Co., Ltd.
    Inventors: Nobuhiko Ito, Hiroyuki Tsuji, Yoshio Fukuda
  • Publication number: 20030179676
    Abstract: A program product is used by a control computer of an optical disc apparatus. The apparatus accesses plural types of optical discs. The control computer recognizes one type of optical disc out of the plural types of optical discs based on history information including a type of optical disc used in times past according to the program. The control computer then judges whether the type of set optical disc is identified with the recognized type of optical disc.
    Type: Application
    Filed: February 24, 2003
    Publication date: September 25, 2003
    Inventor: Nobuhiko Ito
  • Patent number: 6600070
    Abstract: In industrial production of &ohgr;-hydroxyaliphatic acid being an important intermediate for large cyclic lactone-based perfumes, using dicarboxylate ester which is inexpensive and readily obtainable, a method, with high yield and improved selectively, for making a 2-(&ohgr;-alkoxycarbonylalkanoyl)-4-butanolide and an alkaline metal salt thereof, an ester of &ohgr;-hydroxy-(&ohgr;-3)-ketoaliphatic acid as a novel compound and a derivative thereof, and a method for making the same are provided.
    Type: Grant
    Filed: November 29, 2001
    Date of Patent: July 29, 2003
    Assignee: Soda Aromatic Co., Ltd.
    Inventors: Hideaki Takaoka, Sigeru Wada, Nobuhiko Ito, Akio Hasebe, Shinzo Imamura, Hideo Muraoka
  • Publication number: 20030086292
    Abstract: A control signal MBPRG is inputted to individual block decoders that constitute a block decoder section 37 of an ACT type flash memory. Then, the level of the control signal MBPRG is set to “H” to select all the blocks regardless of the contents of address signals a5 through a13, and one word line WL is selected from all the blocks by the addresses a0 through a4. By thus selecting one word line WL every block that is electrically separated by the select transistor and simultaneously applying a write voltage during the test to the same number of word lines WL as the number of blocks, the possible occurrence of a bad influence exerted on the other memory cells is prevented even when the memory cells in which a write operation during the test has been executed include a memory cell that has a negative threshold voltage.
    Type: Application
    Filed: December 17, 2002
    Publication date: May 8, 2003
    Applicant: Sharp Kabushiki Kaisha
    Inventors: Yoshimitsu Yamauchi, Nobuhiko Ito
  • Publication number: 20030058712
    Abstract: There is provided a virtual ground type nonvolatile semiconductor storage device capable of effectively suppressing a leak current to the adjacent cell and thereby achieving high-speed read. During read operation, a ground potential GND is applied to a bit line SBL5 connected to the source region of one memory cell transistor MC04 subjected to read. Moreover, a read drain bias potential Vread is applied to a bit line SBL4 connected to the drain region of the memory cell transistor MC04. A bit line SBL3 connected to the drain region of a first adjacent memory cell transistor MC03 is put into a floating state. A potential Vdb equal to the read drain bias potential Vread is applied to a bit line SBL2 connected to the drain region of a second adjacent memory cell transistor MC02.
    Type: Application
    Filed: September 27, 2002
    Publication date: March 27, 2003
    Applicant: Sharp Kabushiki Kaisha
    Inventors: Kaoru Yamamoto, Nobuhiko Ito
  • Publication number: 20030055105
    Abstract: The present invention relates to drugs and, particularly, to anticancer agents.
    Type: Application
    Filed: July 2, 2002
    Publication date: March 20, 2003
    Inventors: Nobuhiko Ito, Hiroyuki Tsuji, Yoshio Fukuda
  • Patent number: 6528668
    Abstract: Methods for making 2-(&ohgr;-alkoxycarbonylalkanoyl)-4-butanolide and derivatives thereof, esters of &ohgr;-hydroxy-(&ohgr;-3)-ketoaliphatic acid and derivatives thereof, which are useful as a variety of synthetic raw materials and intermediates, and are prepared as intermediates in the production step of &ohgr;-hydroxyaliphatic acid being important intermediates of large cyclic lactone-based perfumes in the perfume industry.
    Type: Grant
    Filed: January 14, 2002
    Date of Patent: March 4, 2003
    Assignee: Toray Industries, Inc.
    Inventors: Hideaki Takaoka, Sigeru Wada, Nobuhiko Ito, Akio Hasebe, Shinzo Imamura, Hideo Muraoka
  • Patent number: 6525207
    Abstract: This invention provides a process for producing an epoxy compound industrially advantageously at low cost in a short process. Furthermore, this invention provides a novel fruity, camphoric, floral, amber or woody fragrance-, flavor- or scent-imparting composition containing said epoxy compound, and foods & drinks, perfumes, cosmetics and tobaccos containing said composition. The epoxy compound can be produced by letting an &agr;-halocyclododecanone and an organic magnesium compound react with each other for Grignard reaction, hydrolyzing to obtain a halohydrin and letting the halohydrin and a base react with each other in the presence of an phase transfer catalyst or adding an aprotic polar solvent for reaction.
    Type: Grant
    Filed: April 17, 2002
    Date of Patent: February 25, 2003
    Assignee: Soda Aromatic Co., Ltd.
    Inventors: Nobuhiko Ito, Motoo Higashi, Yuki Konno, Hideaki Takaoka
  • Patent number: 6512692
    Abstract: A control signal MBPRG is inputted to individual block decoders that constitute a block decoder section. 37 of an ACT type flash memory. Then, the level of the control signal MBPRG is set to “H” to select all the blocks regardless of the contents of address signals a5 through a13, and one word line WL is selected from all the blocks by the addresses a0 through a4. By thus selecting one word line WL every block that is electrically separated by the select transistor and simultaneously applying a write voltage during the test to the same number of word lines WL as the number of blocks, the possible occurrence of a bad influence exerted on the other memory cells is prevented even when the memory cells in which a write operation during the test has been executed include a memory cell that has a negative threshold voltage.
    Type: Grant
    Filed: June 7, 2001
    Date of Patent: January 28, 2003
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Yoshimitsu Yamauchi, Nobuhiko Ito
  • Patent number: 6475133
    Abstract: In industrial production of &ohgr;-hydroxyaliphatic acid being an important intermediate for large cyclic lactone-based perfumes, using dicarboxylate ester which is inexpensive and readily obtainable, a method, with high yield and improved selectively, for making a 2-(&ohgr;-alkoxycarbonylalkanoyl)-4-butanolide and an alkaline metal salt thereof, an ester of &ohgr;-hydroxy-(&ohgr;-3)-ketoaliphatic acid as a novel compound and a derivative thereof, and a method for making the same are provided.
    Type: Grant
    Filed: June 28, 2001
    Date of Patent: November 5, 2002
    Assignee: Soda Aromatic Co., Ltd.
    Inventors: Hideaki Takaoka, Sigeru Wada, Nobuhiko Ito, Akio Hasebe, Shinzo Imamura, Hideo Muraoka
  • Publication number: 20020133028
    Abstract: In industrial production of &ohgr;-hydroxyaliphatic acid being an important intermediate for large cyclic lactone-based perfumes, using dicarboxylate ester which is inexpensive and readily obtainable, a method, with high yield and improved selectively, for making a 2-(&ohgr;-alkoxycarbonylalkanoyl)-4-butanolide and an alkaline metal salt thereof, an ester of &ohgr;-hydroxy-(&ohgr;-3)-ketoaliphatic acid as a novel compound and a derivative thereof, and a method for making the same are provided.
    Type: Application
    Filed: January 14, 2002
    Publication date: September 19, 2002
    Applicant: Soda Aromatic Co., Ltd.
    Inventors: Hideaki Takaoka, Sigeru Wada, Nobuhiko Ito, Akio Hasebe, Shinzo Imamura, Hideo Muraoka
  • Patent number: 6438035
    Abstract: There is provided a nonvolatile semiconductor storage device capable of securing sufficient read accuracy without providing superfluous sense time margin when there are variations in temperature and transistor characteristics. This nonvolatile semiconductor storage device includes a reference cell 2 whose threshold value is preparatorily set to a value between a lower limit of a threshold voltage distribution in a state 0 in which nonvolatile memory cells MC00 through MC12 have a high threshold value and an upper limit of a threshold voltage distribution in a state 1 in which the memory cells have a low threshold value. When the characteristics of the nonvolatile memory cells MC00 through MC12 shift due to the influence of a change in temperature or the like, the characteristics of the reference cell 2 shift so as to follow this characteristic shift.
    Type: Grant
    Filed: June 14, 2001
    Date of Patent: August 20, 2002
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Kaoru Yamamoto, Nobuhiko Ito, Yoshimitsu Yamauchi
  • Publication number: 20020068832
    Abstract: In industrial production of &ohgr;-hydroxyaliphatic acid being an important intermediate for large cyclic lactone-based perfumes, using dicarboxylate ester which is inexpensive and readily obtainable, a method, with high yield and improved selectively, for making a 2-(&ohgr;-alkoxycarbonylalkanoyl)-4-butanolide and an alkaline metal salt thereof, an ester of &ohgr;-hydroxy-(&ohgr;-3)-ketoaliphatic acid as a novel compound and a derivative thereof, and a method for making the same are provided.
    Type: Application
    Filed: November 29, 2001
    Publication date: June 6, 2002
    Applicant: Soda Aromatic Co., Ltd.
    Inventors: Hideaki Takaoka, Sigeru Wada, Nobuhiko Ito, Akio Hasebe, Shinzo Imamura, Hideo Muraoka
  • Publication number: 20020012280
    Abstract: There is provided a nonvolatile semiconductor storage device capable of securing sufficient read accuracy without providing superfluous sense time margin when there are variations in temperature and transistor characteristics. This nonvolatile semiconductor storage device includes a reference cell 2 whose threshold value is preparatorily set to a value between a lower limit of a threshold voltage distribution in a state 0 in which nonvolatile memory cells MC00 through MC12 have a high threshold value and an upper limit of a threshold voltage distribution in a state 1 in which the memory cells have a low threshold value. When the characteristics of the nonvolatile memory cells MC00 through MC12 shift due to the influence of a change in temperature or the like, the characteristics of the reference cell 2 shift so as to follow this characteristic shift.
    Type: Application
    Filed: June 14, 2001
    Publication date: January 31, 2002
    Inventors: Kaoru Yamamoto, Nobuhiko Ito, Yoshimitsu Yamauchi
  • Patent number: 6340020
    Abstract: A stroke identifying unit, for an electronic fuel injection control system of an engine, can identify cylinder strokes without detection of the rotation of the engine's camshaft. The stroke identifying unit includes a crank pulse generator for detecting a phase of a crankshaft of the engine. In a four cylinder engine, an intake pressure sensor detects the combined intake pressures in the second to fourth intake pipes, communicating with the second to fourth cylinders. A fuel injection control unit identifies strokes of the first to fourth cylinders on the basis of a relationship between the detected phase of the crankshaft and the detected intake pressures.
    Type: Grant
    Filed: December 22, 2000
    Date of Patent: January 22, 2002
    Assignee: Honda Giken Kogyo Kabushiki Kaisha
    Inventors: Ryutaro Yamazaki, Nobuhiko Ito, Yasuo Iwata
  • Publication number: 20010050861
    Abstract: A control signal MBPRG is inputted to individual block decoders that constitute a block decoder section 37 of an ACT type flash memory. Then, the level of the control signal MBPRG is set to “H” to select all the blocks regardless of the contents of address signals a5 through a13, and one word line WL is selected from all the blocks by the addresses a0 through a4. By thus selecting one word line WL every block that is electrically separated by the select transistor and simultaneously applying a write voltage during the test to the same number of word lines WL as the number of blocks, the possible occurrence of a bad influence exerted on the other memory cells is prevented even when the memory cells in which a write operation during the test has been executed include a memory cell that has a negative threshold voltage.
    Type: Application
    Filed: June 7, 2001
    Publication date: December 13, 2001
    Inventors: Yoshimitsu Yamauchi, Nobuhiko Ito