Patents by Inventor Nobuhiko Noto

Nobuhiko Noto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9496130
    Abstract: The invention provides a reclaiming processing method for a delaminated wafer, by which the delaminated wafer obtained as a by-produce at the time of producing a bonded wafer is subjected to reclaiming polishing and is again available as a bond wafer or a base wafer, wherein, in the reclaiming polishing, the delaminate wafer is polished with use of a double-side polisher in a state that oxide film is not formed on a delaminated surface of the delaminated wafer and oxide film is formed on a back side which is the opposite side of the delaminated surface. As a result, the reclaiming processing method for a delaminated wafer, by which the delaminated wafer obtained as a by-product at the time of manufacturing a bonded wafer based on an ion implantation delamination method is subjected to the reclaiming polishing, which enables sufficiently improving quality.
    Type: Grant
    Filed: August 29, 2012
    Date of Patent: November 15, 2016
    Assignee: SHIN-ETSU HANDOTAI CO., LTD.
    Inventors: Toru Ishizuka, Yuji Okubo, Takuya Sasaki, Akira Araki, Nobuhiko Noto
  • Patent number: 8987109
    Abstract: A method for manufacturing a bonded wafer includes: an ion implantation step of using a batch type ion implanter; a bonding step of bonding an ion implanted surface of a bond wafer to a surface of a base wafer directly or through an insulator film; and a delamination step of delaminating the bond wafer at an ion implanted layer, thereby manufacturing a bonded wafer having a thin film on the base wafer, wherein the ion implantation into the bond wafer carried out at the ion implantation step is divided into a plurality of processes, the bond wafer is rotated on its own axis a predetermined rotation angle after each ion implantation, and the next ion implantation is carried out at an arrangement position obtained by the rotation.
    Type: Grant
    Filed: April 25, 2012
    Date of Patent: March 24, 2015
    Assignee: Shin-Etsu Handotai Co., Ltd.
    Inventors: Hiroji Aga, Isao Yokokawa, Nobuhiko Noto
  • Publication number: 20140273400
    Abstract: The invention provides a reclaiming processing method for a delaminated wafer, by which the delaminated wafer obtained as a by-produce at the time of producing a bonded wafer is subjected to reclaiming polishing and is again available as a bond wafer or a base wafer, wherein, in the reclaiming polishing, the delaminate wafer is polished with use of a double-side polisher in a state that oxide film is not formed on a delaminated surface of the delaminated wafer and oxide film is formed on a back side which is the opposite side of the delaminated surface. As a result, the reclaiming processing method for a delaminated wafer, by which the delaminated wafer obtained as a by-product at the time of manufacturing a bonded wafer based on an ion implantation delamination method is subjected to the reclaiming polishing, which enables sufficiently improving quality.
    Type: Application
    Filed: August 29, 2012
    Publication date: September 18, 2014
    Applicant: SHIN-ETSU HANDOTAI CO., LTD.
    Inventors: Toru Ishizuka, Yuji Okubo, Takuya Sasaki, Akira Araki, Nobuhiko Noto
  • Patent number: 8823130
    Abstract: A silicon epitaxial wafer having a silicon epitaxial layer grown by vapor phase epitaxy on a main surface of a silicon single crystal substrate, wherein the main surface of the silicon single crystal substrate is tilted with respect to a [100] axis at an angle ? in a [011] direction or a [0-1-1] direction from a (100) plane and at an angle ? in a [01-1] direction or a [0-11] direction from the (100) plane, the angle ? and the angle ? are less than ten minutes, and a dopant concentration of the silicon epitaxial layer is equal to or more than 1×1019/cm3. Even when an epitaxial layer having a dopant concentration of 1×1019/cm3 or more is formed on the main surface of the silicon single crystal substrate, stripe-shaped surface irregularities on the epitaxial layer are inhibited.
    Type: Grant
    Filed: March 1, 2011
    Date of Patent: September 2, 2014
    Assignee: Shin-Etsu Handotai Co., Ltd.
    Inventors: Masahiro Kato, Satoshi Oka, Norihiro Kobayashi, Tohru Ishizuka, Nobuhiko Noto
  • Patent number: 8697544
    Abstract: The present invention is a method for manufacturing a bonded wafer including at least the steps of: forming an ion-implanted layer inside a bond wafer; bringing the ion-implanted surface of the bond wafer into close contact with a surface of a base wafer directly or through a silicon oxide film; and performing heat treatment for delaminating the bond wafer at the ion-implanted layer, wherein the heat treatment step for delaminating includes performing a pre-annealing at a temperature of less than 500° C. and thereafter performing a delamination heat treatment at a temperature of 500° C. or more, and the pre-annealing is performed at least by a heat treatment at a first temperature and a subsequent heat treatment at a second temperature higher than the first temperature.
    Type: Grant
    Filed: October 14, 2009
    Date of Patent: April 15, 2014
    Assignee: Shin-Etsu Handotai Co., Ltd.
    Inventors: Tohru Ishizuka, Norihiro Kobayashi, Nobuhiko Noto
  • Publication number: 20140097523
    Abstract: A method for manufacturing a bonded wafer includes: an ion implantation step of using a batch type ion implanter; a bonding step of bonding an ion implanted surface of a bond wafer to a surface of a base wafer directly or through an insulator film; and a delamination step of delaminating the bond wafer at an ion implanted layer, thereby manufacturing a bonded wafer having a thin film on the base wafer, wherein the ion implantation into the bond wafer carried out at the ion implantation step is divided into a plurality of processes, the bond wafer is rotated on its own axis a predetermined rotation angle after each ion implantation, and the next ion implantation is carried out at an arrangement position obtained by the rotation.
    Type: Application
    Filed: April 25, 2012
    Publication date: April 10, 2014
    Applicant: SHIN-ETSU HANDOTAI CO., LTD.
    Inventors: Hiroji Aga, Isao Yokokawa, Nobuhiko Noto
  • Patent number: 8691665
    Abstract: The present invention is directed to a method for producing a bonded wafer, the method in which heat treatment for flattening the surface of a thin film is performed on a bonded wafer made by the ion implantation delamination method in an atmosphere containing hydrogen or hydrogen chloride, wherein the surface of a susceptor on which the bonded wafer is to be placed, the susceptor used at the time of flattening heat treatment, is coated with a silicon film in advance. As a result, a method for producing a bonded wafer is provided, the method by which a bonded wafer having a thin film with good film thickness uniformity can be obtained even when heat treatment for flattening the surface of a thin film of a bonded wafer after delamination is performed in the ion implantation delamination method.
    Type: Grant
    Filed: November 18, 2010
    Date of Patent: April 8, 2014
    Assignee: Shin-Etsu Handotai Co., Ltd.
    Inventors: Satoshi Oka, Hiroji Aga, Masahiro Kato, Nobuhiko Noto
  • Patent number: 8466538
    Abstract: The present invention is an SOI wafer comprising at least: an SOI layer; a silicon oxide film; and a base wafer, wherein the SOI layer has a plane orientation of (100), and the base wafer has a resistivity of 100 ?·cm or more and a plane orientation different from (100). As a result, there is provided the SOI wafer and the manufacturing method thereof that have no complicated manufacturing step, defects on a bonding interface which are not practically a problem in number and a high interface state density (Dit) for trapping carriers on an interface of a BOX layer and the base wafer.
    Type: Grant
    Filed: February 19, 2009
    Date of Patent: June 18, 2013
    Assignee: Shin-Etsu Handotai Co., Ltd.
    Inventors: Tohru Ishizuka, Nobuhiko Noto, Norihiro Kobayashi, Masatake Nakano
  • Publication number: 20130102126
    Abstract: A method for manufacturing a bonded wafer including: forming an ion-implanted layer in a bond wafer, bonding the bond wafer to a base wafer, delaminating the bond wafer at the ion-implanted layer, and performing a flattening heat treatment on a surface after delamination, in which a silicon single crystal wafer is used as the bond wafer where the region to form the ion-implanted layer has a resistivity of 0.2 ?cm or less, the ion-implanted layer is formed where the ion dose for forming the layer is 4×1016/cm2 or less, and the flattening heat treatment is performed in an atmosphere including HCl gas. Therefore, a method for manufacturing a bonded wafer having a low resistivity thin film (SOI layer) that contains dopant, such as boron, with high concentration according to the ion-implantation delamination method, where outward diffusion of dopant and suction due to oxidation can be inhibited to maintain low resistivity.
    Type: Application
    Filed: April 21, 2011
    Publication date: April 25, 2013
    Applicant: SHIN-ETSU HANDOTAI CO., LTD.
    Inventors: Hiroji Aga, Satoshi Oka, Nobuhiko Noto
  • Patent number: 8410573
    Abstract: In a SOI structure semiconductor device using a SOI substrate, a lattice distortion layer is formed by implanting Ar ions into a silicon substrate as an active layer. The lattice distortion layer is capable of serving as a gettering site. The dose amount of Ar ions is adjusted in such a manner that tensile stress in the lattice distortion layer is equal to or greater than 11 MPa and equal to or less than 27 MPa. Thus, the lattice distortion layer can prevent occurrence of a leakage current while serving as the gettering site.
    Type: Grant
    Filed: October 20, 2008
    Date of Patent: April 2, 2013
    Assignees: DENSO CORPORATION, Shin-Etsu Handotai Co., Ltd.
    Inventors: Hiroshi Ohtsuki, Mitsutaka Katada, Nobuhiko Noto, Hiroshi Takeno, Kazuhiko Yoshida
  • Patent number: 8389382
    Abstract: A method for manufacturing a bonded wafer including the steps of: implanting at least one gas ion of a hydrogen ion and a rare gas ion into a bond wafer from a surface thereof to form an ion-implanted layer; bonding the ion-implanted surface of the bond wafer to a surface of a base wafer directly or through an oxide film; thereafter delaminating the bond wafer at the ion-implanted layer to prepare the bonded wafer having a silicon thin film formed on the base wafer; and performing a flattening heat treatment on the bonded wafer under an atmosphere containing hydrogen or hydrogen chloride, wherein a dopant gas is added into the atmosphere of the flattening heat treatment to perform the heat treatment, the dopant gas having the same conductivity type as a dopant contained in the silicon thin film.
    Type: Grant
    Filed: October 15, 2009
    Date of Patent: March 5, 2013
    Assignee: Shin-Etsu Handotai Co., Ltd.
    Inventors: Satoshi Oka, Nobuhiko Noto
  • Patent number: 8361888
    Abstract: The present invention provides a method for manufacturing an SOI wafer wherein an HCl gas is mixed in a reactive gas at a step of forming a silicon epitaxial layer on an entire surface of an SOI layer of the SOI wafer having an oxide film on a terrace portion. As a result, it is possible to provide the method for manufacturing an SOI wafer that can easily grow the silicon epitaxial layer on the SOI layer of the SOI wafer having the oxide film on the terrace portion, suppress warpage of the SOI wafer to be manufactured, reduce generation of particles even at subsequent steps, e.g., device manufacture, and decrease a cost for manufacturing such an SOI wafer.
    Type: Grant
    Filed: May 27, 2008
    Date of Patent: January 29, 2013
    Assignee: Shin-Etsu Handotai Co., Ltd.
    Inventors: Isao Yokokawa, Nobuhiko Noto
  • Publication number: 20120326268
    Abstract: A silicon epitaxial wafer having a silicon epitaxial layer grown by vapor phase epitaxy on a main surface of a silicon single crystal substrate, wherein the main surface of the silicon single crystal substrate is tilted with respect to a [100] axis at an angle ? in a [011] direction or a [0-1-1] direction from a (100) plane and at an angle ? in a [01-1] direction or a [0-11] direction from the (100) plane, the angle ? and the angle ? are less than ten minutes, and a dopant concentration of the silicon epitaxial layer is equal to or more than 1×1019/cm3. Even when an epitaxial layer having a dopant concentration of 1×1019/cm3 or more is formed on the main surface of the silicon single crystal substrate, stripe-shaped surface irregularities on the epitaxial layer are inhibited.
    Type: Application
    Filed: March 1, 2011
    Publication date: December 27, 2012
    Applicant: SHIN-ETSU HANDOTAI CO., LTD.
    Inventors: Masahiro Kato, Satoshi Oka, Norihiro Kobayashi, Tohru Ishizuka, Nobuhiko Noto
  • Patent number: 8338277
    Abstract: The present invention provides a method for manufacturing an SOI substrate including at least: an oxygen ion implantation step of ion-implanting oxygen ions from one main surface of a single-crystal silicon substrate to form an oxygen ion implanted layer; and a heat treatment step of performing a heat treatment with respect to the single-crystal silicon substrate having the oxygen ion implanted layer formed therein to change the oxygen ion implanted layer into a buried oxide film layer, wherein acceleration energy for the oxygen ion implantation is previously determined from a thickness of the buried oxide film layer to be obtained, and the oxygen ion implantation step is carried out with the determined acceleration energy to manufacture the SOI substrate. Thereby, it is possible to provide an SOI substrate manufacturing method that enables efficiently manufacturing an SOI substrate having a continuous and uniform thin buried oxide film layer.
    Type: Grant
    Filed: February 19, 2008
    Date of Patent: December 25, 2012
    Assignee: Shin-Etsu Handotai Co., Ltd.
    Inventors: Hiroshi Takeno, Tohru Ishizuka, Nobuhiko Noto
  • Publication number: 20120244679
    Abstract: The present invention is directed to a method for producing a bonded wafer, the method in which heat treatment for flattening the surface of a thin film is performed on a bonded wafer made by the ion implantation delamination method in an atmosphere containing hydrogen or hydrogen chloride, wherein the surface of a susceptor on which the bonded wafer is to be placed, the susceptor used at the time of flattening heat treatment, is coated with a silicon film in advance. As a result, a method for producing a bonded wafer is provided, the method by which a bonded wafer having a thin film with good film thickness uniformity can be obtained even when heat treatment for flattening the surface of a thin film of a bonded wafer after delamination is performed in the ion implantation delamination method.
    Type: Application
    Filed: November 18, 2010
    Publication date: September 27, 2012
    Applicant: SHIN-ETSU HANDOTAI CO., LTD.
    Inventors: Satoshi Oka, Hiroji Aga, Masahiro Kato, Nobuhiko Noto
  • Patent number: 8202787
    Abstract: A method for manufacturing an SOI wafer having a buried oxide film with a predetermined thickness including performing a heat treatment for reducing a thickness of the buried oxide film on an SOI wafer material having an SOI layer formed on the buried oxide film, wherein a thickness of the SOI layer of the SOI wafer material to be subjected to the heat treatment for reducing the thickness of the buried oxide film is calculated on the basis of a ratio of the thickness of the buried oxide film to be reduced by the heat treatment with respect to a permissible value of an amount of change in an in-plane range of the buried oxide film, the change being caused by the heat treatment, and the SOI wafer material obtained by thinning the thickness of the bond wafer so as to have the calculated thickness of the SOI layer is subjected to the heat treatment for reducing the thickness of the buried oxide film.
    Type: Grant
    Filed: November 11, 2009
    Date of Patent: June 19, 2012
    Assignee: Shin-Etsu Handotai Co., Ltd.
    Inventors: Tohru Ishizuka, Norihiro Kobayashi, Hiroji Aga, Nobuhiko Noto
  • Patent number: 8173521
    Abstract: The present invention is a method for manufacturing a bonded wafer by an ion implantation delamination method including at least the steps of, bonding a bond wafer having a micro bubble layer formed by gas ion implantation with a base wafer to be a supporting substrate, delaminating the bond wafer along the micro bubble layer as a boundary to form a thin film on the base wafer, the method comprising, cleaning the bonded wafer after delaminating the bond wafer using ozone water; performing rapid thermal anneal process under a hydrogen containing atmosphere; forming a thermal oxide film on a surface layer of the bonded wafer by subjecting to heat treatment under an oxidizing gas atmosphere and removing the thermal oxide film; subjecting to heat treatment under a non-oxidizing gas atmosphere.
    Type: Grant
    Filed: July 3, 2008
    Date of Patent: May 8, 2012
    Assignee: Shin-Etsu Handotai Co., Ltd.
    Inventors: Norihiro Kobayashi, Hiroji Aga, Yasuo Nagaoka, Nobuhiko Noto
  • Patent number: 8097523
    Abstract: A method for manufacturing a bonded wafer, including at least implanting at least one type of gas ion selected from a hydrogen ion and a rare gas ion from a surface of a bond wafer to form an ion-implanted layer in the wafer, bonding an ion-implanted surface of the bond wafer to a surface of a base wafer directly or through an insulator film, and then delaminating the bond wafer at the ion-implanted layer to fabricate a bonded wafer. A plasma treatment is applied to a bonding surface of one of the bond wafer and the base wafer to grow an oxide film, etching the grown oxide film is carried out, and bonding to the other wafer is performed. The method enables preventing defects by reducing particles on the bonding surface and performing strong bonding when effecting bonding directly or through the insulator film.
    Type: Grant
    Filed: February 17, 2009
    Date of Patent: January 17, 2012
    Assignee: Shin-Etsu Handotai Co., Ltd.
    Inventors: Norihiro Kobayashi, Tohru Ishizuka, Hiroji Aga, Nobuhiko Noto
  • Patent number: 8076223
    Abstract: The present invention is a method for producing a semiconductor substrate, including steps of forming a SiGe gradient composition layer and a SiGe constant composition layer on a Si single crystal substrate, flattening a surface of the SiGe constant composition layer, removing a natural oxide film on the flattened surface of the SiGe constant composition layer, and forming a strained Si layer on the surface of the SiGe constant composition layer from which the natural oxide film has been removed, wherein the formation of the SiGe gradient composition layer and the formation of the SiGe constant composition layer are performed at a temperature T1 that is higher than 800° C., the removal of the natural oxide film from the surface of the SiGe constant composition layer is performed in a reducing atmosphere through a heat treatment at a temperature T2 that is equal to or higher than 800° C.
    Type: Grant
    Filed: July 4, 2007
    Date of Patent: December 13, 2011
    Assignee: Shin-Etsu Handotai Co., Ltd.
    Inventors: Satoshi Oka, Nobuhiko Noto
  • Publication number: 20110281420
    Abstract: A method for manufacturing an SOI wafer including implanting a gas ion into a bond wafer from a surface thereof to form an ion-implanted layer; bonding the ion-implanted surface of the bond wafer to a surface of a base wafer through an insulator film; and delaminating the bond wafer at the ion-implanted layer to manufacture the SOI wafer. The method further includes immersing the bonded wafer prior to the delamination of the bond wafer at the ion-implanted layer into a liquid capable of dissolving the insulator film or exposing the bonded wafer to a gas capable of dissolving the insulator film so that the insulator film located between the bond wafer and the base wafer is etched from an outer circumferential edge toward a center of the bonded wafer.
    Type: Application
    Filed: January 8, 2010
    Publication date: November 17, 2011
    Applicant: SHIN-ETSU HANDOTAI CO., LTD.
    Inventors: Hiroji Aga, Isao Yokokawa, Nobuhiko Noto