Patents by Inventor Nobuhiko Noto
Nobuhiko Noto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20090305485Abstract: The present invention is a method for producing a semiconductor substrate, including steps of forming a SiGe gradient composition layer and a SiGe constant composition layer on a Si single crystal substrate, flattening a surface of the SiGe constant composition layer, removing a natural oxide film on the flattened surface of the SiGe constant composition layer, and forming a strained Si layer on the surface of the SiGe constant composition layer from which the natural oxide film has been removed, wherein the formation of the SiGe gradient composition layer and the formation of the SiGe constant composition layer are performed at a temperature T1 that is higher than 800° C., the removal of the natural oxide film from the surface of the SiGe constant composition layer is performed in a reducing atmosphere through a heat treatment at a temperature T2 that is equal to or higher than 800° C.Type: ApplicationFiled: July 4, 2007Publication date: December 10, 2009Applicant: Shin-Etsu Handotai Co., Ltd.Inventors: Satoshi Oka, Nobuhiko Noto
-
Publication number: 20090258474Abstract: Provided is a method for producing an SOI substrate having a thick-film SOI layer, in which an ion-implanted layer is formed by implanting at least one kind of ion of hydrogen ion and a rare gas ion into a surface of a bond wafer, an SOI substrate having an SOI layer is produced by, after the ion-implanted surface of the bond wafer and a surface of a base wafer are bonded together via an oxide film, delaminating the bond wafer along the ion-implanted layer, heat treatment is performed on the SOI substrate having the SOI layer in a reducing atmosphere containing hydrogen or an atmosphere containing hydrogen chloride gas, and, after the surface of the SOI layer is polished by CMP, a silicon epitaxial layer is grown on the SOI layer of the SOI substrate.Type: ApplicationFiled: March 4, 2009Publication date: October 15, 2009Applicant: SHIN-ETSU HANDOTAI CO., LTD.Inventors: Satoshi Oka, Nobuhiko Noto
-
Publication number: 20090170285Abstract: The present invention provides a method for manufacturing a bonded wafer by an ion implantation delamination method, the method including at least the steps of bonding a base wafer with a bond wafer having a microbubble layer formed by ion implantation, delaminating the wafers along the micro bubble layer as a boundary, and removing a periphery of a thin film formed on the base wafer by the delamination step, wherein at least the thin-film periphery removal step after the delamination step is performed by dry etching that supplies an etching gas from a nozzle, and the dry etching is performed by adjusting an inner diameter of the gas-jetting port of the nozzle, and a distance between the gas-jetting port of the nozzle and a surface of the thin film.Type: ApplicationFiled: May 14, 2007Publication date: July 2, 2009Applicant: SHIN-ETSU HANDOTAI CO., LTD.Inventors: Yasutsugu Soeta, Nobuhiko Noto
-
Patent number: 7553685Abstract: A light-emitting device 100 has ITO transparent electrode layers 8, 10 used for applying drive voltage for light-emission to a light-emitting layer section 24, and is designed so as to extract light from the light-emitting layer section 24 through the ITO transparent electrode layers 8, 10. The light-emitting device 100 also has contact layers composed of In-containing GaAs, formed between the light-emitting layer section 24 and the ITO transparent electrode layers 8, 10, so as to contact with the ITO transparent electrode layers respectively. The contact layers 7, 9 are formed by annealing a stack 13 obtained by forming GaAs layers 7?, 9? on the light-emitting layer section, and by forming the ITO transparent electrode layers 8, 10 so as to contact with the GaAs layers 7?, 9?, to thereby allow In to diffuse from the ITO transparent electrode layers 8, 10 into the GaAs layers 7?, 9?.Type: GrantFiled: August 6, 2003Date of Patent: June 30, 2009Assignee: Shin-Etsu Handotai Co., Ltd.Inventors: Nobuhiko Noto, Masato Yamada, Shinji Nozaki, Kazuo Uchida, Hiroshi Morisaki
-
Patent number: 7550309Abstract: The present invention is a method for producing a semiconductor wafer, comprising at least steps of, epitaxially growing a Si1-XGeX layer (0<X<1) on an SOI wafer, forming a Si1-YGeY layer (0?Y<X) on the epitaxially grown Si1-XGeX layer, and then enriching Ge in the epitaxially grown Si1-XGeX layer by an oxidation heat treatment so that the Si1-XGeX layer becomes an enriched SiGe layer, wherein, at least, the oxidation heat treatment is initiated from 950° C. or less under an oxidizing atmosphere, and the oxidation is performed so that the formed Si1-YGeY layer remains during a temperature rise to 950° C. Thereby, there can be provided a method for producing a semiconductor wafer by which the lattice relaxation of the SiGe layer in an SGOI wafer can be sufficiently performed by a heat treatment for a short time and its production cost can be reduced.Type: GrantFiled: September 16, 2005Date of Patent: June 23, 2009Assignee: Shin-Etsu Handotai Co., Ltd.Inventors: Isao Yokokawa, Nobuhiko Noto, Kiyoshi Mitani
-
Publication number: 20090042361Abstract: According to the present invention, there is provided a method for manufacturing an SOI substrate based on a bonding method, comprising at least: forming a silicon oxide film on a surface of at least one of a single-crystal silicon substrate that becomes an SOI layer and a single-crystal silicon substrate that becomes a support substrate; bonding the single-crystal silicon substrate that becomes the SOI layer to the single-crystal silicon substrate that becomes the support substrate through the silicon oxide film; and performing a heat treatment for holding at a temperature falling within the range of at least 950° C. to 1100° C. and then carrying out a heat treatment at a temperature higher than 1100° C. when effecting a bonding heat treatment for increasing bonding strength.Type: ApplicationFiled: October 20, 2006Publication date: February 12, 2009Applicant: SHIN-ETSU HANDOTAI CO., LTD.Inventors: Hiroshi Takeno, Nobuhiko Noto
-
Publication number: 20080315349Abstract: The present invention provides a method for manufacturing a bonded wafer prepared by bonding a base wafer and a bond wafer, comprising at least a step of etching an oxide film in a terrace region in an outer periphery of the bonded wafer wherein the oxide film in the terrace region is etched by spin-etching with holding and spinning the bonded wafer. Thereby, there is provided a method for manufacturing a bonded wafer in which an oxide film formed in a terrace region of a base wafer is efficiently etched without removing an oxide film on the back surface of the base wafer.Type: ApplicationFiled: November 2, 2005Publication date: December 25, 2008Applicant: SHIN-ETSU HANDOTAI CO., LTD.Inventors: Tokio Takei, Sigeyuki Yoshizawa, Susumu Miyazaki, Isao Yokokawa, Nobuhiko Noto
-
Publication number: 20080261411Abstract: The present invention provides a method for manufacturing an SOI substrate by which an oxygen ion is implanted from at least one of main surfaces of a single-crystal silicon substrate to form an oxygen-ion-implanted layer and then an oxide film-forming heat treatment that changes the formed oxygen-ion-implanted layer into a buried oxide film layer is performed with respect to the single-crystal silicon substrate to manufacture the SOI substrate, the method comprising: implanting a neutral element ion having a dose amount of 1×1012 atoms/cm2 or above and less than 1×1015 atoms/cm2 into a back surface to form an ion-implanted damage layer after performing the oxide film-forming heat treatment; and gettering a metal impurity in the ion-implanted damage layer by a subsequent heat treatment to enable reducing a metal impurity concentration on a front surface side.Type: ApplicationFiled: April 1, 2008Publication date: October 23, 2008Applicant: SHIN-ETSU HANDOTAI CO., LTD.Inventors: Tohru Ishizuka, Hiroshi Takeno, Nobuhiko Noto
-
Publication number: 20080003785Abstract: The present invention is a method for producing a semiconductor wafer, comprising at least steps of, epitaxially growing a Si1-XGeX layer (0<X<1) on an SOI wafer, forming a Si1-YGeY layer (0?Y<X) on the epitaxially grown Si1-XGeX layer, and then enriching Ge in the epitaxially grown Si1-XGeX layer by an oxidation heat treatment so that the Si1-XGeX layer becomes an enriched SiGe layer, wherein, at least, the oxidation heat treatment is initiated from 950° C. or less under an oxidizing atmosphere, and the oxidation is performed so that the formed Si1-YGeY layer remains during a temperature rise to 950° C. Thereby, there can be provided a method for producing a semiconductor wafer by which the lattice relaxation of the SiGe layer in an SGOI wafer can be sufficiently performed by a heat treatment for a short time and its production cost can be reduced.Type: ApplicationFiled: September 16, 2005Publication date: January 3, 2008Applicant: Shin-etsu Handotai Co., Ltd.Inventors: Isao Yokokawa, Nobuhiko Noto, Kiyoshi Mitani
-
Publication number: 20070287269Abstract: The present invention is a method for producing a semiconductor wafer, comprising at least steps of: epitaxially growing a SiGe layer on a surface of a silicon single crystal wafer that is to be a bond wafer; implanting at least one kind of hydrogen ion and rare gas ion through the SiGe layer, so that an ion implanted layer is formed inside the bond wafer; closely contacting and bonding a surface of the SiGe layer and a surface of a base wafer through an insulator film; then performing delamination at the ion implanted layer, removing a Si layer in a delaminated layer transferred to a side of the base wafer by the delamination, so that the SiGe layer is exposed; and then subjecting the exposed SiGe layer to a heat treatment for enriching Ge under an oxidizing atmosphere and/or a heat treatment for relaxing lattice strain under a non-oxidizing atmosphere.Type: ApplicationFiled: October 14, 2005Publication date: December 13, 2007Applicant: SHIN-ETSU HANDOTAI CO., LTD.Inventors: Isao Yokokawa, Nobuhiko Noto
-
Publication number: 20060185581Abstract: The present invention provides a method for producing a semiconductor wafer comprising at least steps of, forming a Si1-XGeX layer (0<X<1) with a critical film-thickness at a deposition temperature of the layer or thinner on a surface of a silicon single crystal wafer and then forming a Si layer with a critical film-thickness at a temperature of later relaxing heat-treatment or thinner thereon, forming an ion-implanted layer for relaxation inside the silicon single crystal wafer by implanting at least one kind of hydrogen ion, rare gas ion, and Si ion through the Si layer, thereafter performing the relaxing heat-treatment, thereby to make the Si1-XGeX layer lattice-relaxed and to form a strained Si layer by introducing lattice strain in the Si layer, thereafter depositing Si on a surface of the strained Si layer, and thereby to increase a thickness of the strained Si layer.Type: ApplicationFiled: February 14, 2006Publication date: August 24, 2006Applicant: SHIN-ETSU HANDOTAI CO., LTD.Inventors: Hiroji Aga, Nobuhiko Noto, Kiyoshi Mitani
-
Patent number: 7041529Abstract: In a light-emitting device, a light-emitting layer portion composed of a compound semiconductor is bonded on one main surface of a transparent conductive semiconductor substrate while placing a substrate-bonding conductive oxide layer composed of a conductive oxide in between. Between the light-emitting layer portion and the substrate-bonding conductive oxide layer, a contact layer for reducing junction resistance with the substrate-bonding conductive oxide layer so as to contact with the substrate-bonding conductive oxide layer. This is successful in providing the light-emitting device which is producible at low costs, has a low series resistance, and can attain a sufficient emission efficiency despite it has a thick current-spreading layer.Type: GrantFiled: October 22, 2003Date of Patent: May 9, 2006Assignees: Shin-Etsu Handotai Co., Ltd., Nanoteco CorporationInventors: Masato Yamada, Jun-ya Ishizaki, Nobuhiko Noto, Kazunori Hagimoto, Shinji Nozaki, Kazuo Uchida, Hiroshi Morisaki
-
Patent number: 6995401Abstract: A light emitting device having an oxide transparent electrode layer as an emission drive electrode, and designed so that damage possibly occurs during bonding of electrode wires to the bonding pads is less influential to a light emitting layer portion is disclosed. The light emitting device has the light emitting layer portion composed of a compound semiconductor and has a double heterostructure in which a first-conductivity-type cladding layer, an active layer and a second-conductivity-type cladding layer are stacked in this order; and the light emitting layer portion is applied with emission drive voltage through an oxide transparent electrode layer formed so as to cover the main surface of the second-conductivity-type cladding layer. A bonding pad composed of a metal is disposed on the oxide transparent electrode layer, and to the bonding pad an electrode wire for current supply is bonded.Type: GrantFiled: October 22, 2003Date of Patent: February 7, 2006Assignees: Shin-Etsu Handotai Co., Ltd., Nanoteco CorporationInventors: Masato Yamada, Nobuhiko Noto, Masanobu Takahashi, Kingo Suzuki, Shinji Nozaki, Kazuo Uchida, Hiroshi Morisaki
-
Publication number: 20050285127Abstract: A light-emitting device 100 has ITO transparent electrode layers 8, 10 used for applying drive voltage for light-emission to a light-emitting layer section 24, and is designed so as to extract light from the light-emitting layer section 24 through the ITO transparent electrode layers 8, 10. The light-emitting device 100 also has contact layers composed of In-containing GaAs, formed between the light-emitting layer section 24 and the ITO transparent electrode layers 8, 10, so as to contact with the ITO transparent electrode layers respectively. The contact layers 7, 9 are formed by annealing a stack 13 obtained by forming GaAs layers 7?, 9? on the light-emitting layer section, and by forming the ITO transparent electrode layers 8, 10 so as to contact with the GaAs layers 7?, 9?, to thereby allow In to diffuse from the ITO transparent electrode layers 8, 10 into the GaAs layers 7?, 9?.Type: ApplicationFiled: August 6, 2003Publication date: December 29, 2005Applicants: Shin-Etsu Handotai Co., Ltd., Nanoteco CorporationInventors: Nobuhiko Noto, Masato Yamada, Shinji Nozaki, Kazuo Uchida, Hiroshi Morisaki
-
Patent number: 6847056Abstract: A light emitting device 100 has a structure in which a p type InGaAs layer 7 as an electrode contact layer and an ITO electrode layer 8 as an oxide transparent electrode layer are formed in the order in a first major surface 17 side of a light emitting layer section 24. In a second major surface 18 side of the light emitting layer section 24, an n type InGaAs layer 9 as an electrode contact layer and an ITO electrode layer 10 as an oxide transparent electrode layer are formed in the order. The ITO electrode layers 8 and 10 together with the p type InGaAs layer 7 and the n type InGaAs layer 9 are formed on the respective both major surfaces 17 and 18 of the light emitting layer section 24 so as to cover the respective both major surfaces 17 and 18 in the entirety thereof.Type: GrantFiled: January 29, 2002Date of Patent: January 25, 2005Assignees: Shin-Etsu Handotai Co., Ltd., Nanoteco CorporationInventors: Nobuhiko Noto, Masato Yamada, Masahisa Endo, Hitoshi Ikeda, Shinji Nozaki, Kazuo Uchida, Hiroshi Morisaki
-
Publication number: 20040206961Abstract: A light emitting device having an oxide transparent electrode layer as an emission drive electrode, and designed so that damage possibly occurs during bonding of electrode wires to the bonding pads is less influential to a light emitting layer portion is disclosed. The light emitting device has the light emitting layer portion composed of a compound semiconductor and has a double heterostructure in which a first-conductivity-type cladding layer, an active layer and a second-conductivity-type cladding layer are stacked in this order; and the light emitting layer portion is applied with emission drive voltage through an oxide transparent electrode layer formed so as to cover the main surface of the second-conductivity-type cladding layer. A bonding pad composed of a metal is disposed on the oxide transparent electrode layer, and to the bonding pad an electrode wire for current supply is bonded.Type: ApplicationFiled: October 22, 2003Publication date: October 21, 2004Applicants: Shin-Etsu Handotai Co., Ltd., Nanoteco CorporationInventors: Masato Yamada, Nobuhiko Noto, Masanobu Takahashi, Kingo Suzuki, Shinji Nozaki, Kazuo Uchida, Hiroshi Morisaki
-
Patent number: 6787383Abstract: The light-emitting device 100 has an ITO electrode layer 8 for applying drive voltage for light emission to a light emitting layer section 24, where the light from the light emitting layer section 24 is extracted as being passed through the ITO electrode layer 8. Between the light emitting layer section 24 and the ITO electrode layer 8, an electrode contact layer 7 composed of In-containing GaAs is located so as to contact with such ITO electrode layer 8, where occupied areas and unoccupied areas for the electrode contact layer 7 are arranged in a mixed manner on the contact interface with the transparent electrode layer 8. The electrode contact layer 7 can be obtained by annealing a stack 13, which comprises a GaAs layer 7″ formed on the light emitting layer section 24 and the ITO electrode layer 8 formed so as to contact with the GaAs layer 7″, to thereby allow In to diffuse from the ITO electrode layer to the GaAs layer 7″.Type: GrantFiled: September 26, 2002Date of Patent: September 7, 2004Assignees: Shin-Etsu Hanotai Co., Ltd., Nanoteco CorporationInventors: Shunichi Ikeda, Masato Yamada, Nobuhiko Noto, Shinji Nozaki, Kazuo Uchida, Hiroshi Morisaki
-
Publication number: 20040135166Abstract: In a light-emitting device, a light-emitting layer portion composed of a compound semiconductor is bonded on one main surface of a transparent conductive semiconductor substrate while placing a substrate-bonding conductive oxide layer composed of a conductive oxide in between. Between the light-emitting layer portion and the substrate-bonding conductive oxide layer, a contact layer for reducing junction resistance with the substrate-bonding conductive oxide layer so as to contact with the substrate-bonding conductive oxide layer. This is successful in providing the light-emitting device which is producible at low costs, has a low series resistance, and can attain a sufficient emission efficiency despite it has a thick current-spreading layer.Type: ApplicationFiled: October 22, 2003Publication date: July 15, 2004Applicants: Shin-Etsu Handotai Co., Ltd., Nanoteco CorporationInventors: Masato Yamada, Jun-ya Ishizaki, Nobuhiko Noto, Kazunori Hagimoto, Shinji Nozaki, Kazuo Uchida, Hiroshi Morisaki
-
Patent number: 6759689Abstract: A metal layer 3, a light emitting layer section 4 and a first electrode 5 are formed in the order on a first main surface 7 side of a conductive substrate 2 and a current is supplied to the light emitting layer section 4 through the first electrode 5 and the conductive substrate 2. By using reflection on the metal layer 3, not only can good external quantum efficiency be realized, but electrodes or terminals can also be formed on both sides of the light emitting element. Thus, provided is a light emitting element excellent in external quantum efficiency thereof and in addition, not only simple in structure of a terminal lead thereof but excellent in convenience.Type: GrantFiled: August 7, 2002Date of Patent: July 6, 2004Assignee: Shin-Etsu Handotai Co., Ltd.Inventors: Keizo Adomi, Masanobu Takahashi, Nobuhiko Noto
-
Publication number: 20040104395Abstract: A light-emitting device which uses a reflective metal layer, and thereby has a large light extraction efficiency and a small wavelength dependence is disclosed. The device uses one main surface of a light-emitting layer portion as a light extraction surface, and has a device substrate bonded on other main surface of the light-emitting layer portion. The device also has an Ag-base metal layer disposed between the device substrate and the light-emitting layer portion, wherein the Ag-base reflective metal layer has Ag as a major component over the entire portion thereof, and is intended for reflecting the light from the light-emitting layer portion back towards the light extraction surface side.Type: ApplicationFiled: November 24, 2003Publication date: June 3, 2004Applicant: Shin-Etsu Handotai Co., Ltd.Inventors: Kazunori Hagimoto, Nobuhiko Noto