Abstract: A metallic contaminant detecting method and apparatus according to the present invention detect metallic contaminants mixed in objects under inspection, such as food products, pharmaceuticals, and materials for industrial use, which are wrapped in electrically conductive packaging materials, e.g. aluminum. A small magnetic field is generated by applying a voltage to coils (10, 11) or supplying an electric current to the coils. A detection magnetic field generated from a metallic contaminant in response to the small magnetic field is detected as a detection voltage or a detection current of the coils (10, 11), and a detection signal is output. The detection signal is analyzed to detect the metallic contaminant. The small magnetic field is created by applying a small voltage or supplying a small electric current to the coils (10, 11) and using a non-linear portion of the magnetic field characteristics of cores constituting the coils (10, 11).

Abstract: A metallic contaminant detecting method and apparatus according to the present invention detect metallic contaminants mixed in objects under inspection, such as food products, pharmaceuticals, and materials for industrial use, which are wrapped in electrically conductive packaging materials, e.g. aluminum. A small magnetic field is generated by applying a voltage to coils (10, 11) or supplying an electric current to the coils. A detection magnetic field generated from a metallic contaminant in response to the small magnetic field is detected as a detection voltage or a detection current of the coils (10, 11), and a detection signal is output. The detection signal is analyzed to detect the metallic contaminant. The small magnetic field is created by applying a small voltage or supplying a small electric current to the coils (10, 11) and using a non-linear portion of the magnetic field characteristics of cores constituting the coils (10, 11).

Abstract: In an LSI system using an on-chip bus, when a transfer on the bus is delayed due to a fully loaded buffer in a destination module, a source module cannot proceed to the next processing. Such an unwanted situation is eliminated by a transferring buffer which is provided on a transfer path in an on-chip bus on the LSI for temporarily storing transfer data. With this transferring buffer, even if a buffer within a slave module, specified as the destination, is fully loaded and cannot accept any more transfer, a bus master can transfer data to the transferring buffer provided on the on-chip bus. Thus, the bus master is not kept waiting for execution of a transfer, irrespective of the state of the buffer within the slave, thereby improving the processing performance of the entire system.

Abstract: A terminal device stores in a nonvolatile memory a video encoding method, a size expressed by pixels, a frame rate, a bit rate, and a key frame insertion interval suitable for reception. A receiving side terminal device notifies information to a sending side terminal. According to the information, the sending side terminal device encodes video data obtained by shooting an object and transmits encoded video data. Also, the sending side terminal device cuts, from the video data, video data of a size not exceeding a least size among a size of the video data obtained by the sending side terminal device, a size expressed by pixels suitable for transmission in the sending side terminal device, and a size expressed by pixels suitable for reception in the reception side terminal device. The sending side terminal device encodes and transmits the video data.

Abstract: An information processing apparatus includes a master module serving as a transfer source, a slave module serving as a transfer destination, a bus of a source clock synchronous system, and a means for transferring a signal based upon a protocol of an acknowledge type from the slave module to the master module via the bus of the source clock synchronous system. In the information processor, the signals of the acknowledge type are also transferred in the source clock synchronous system by using a source clock signal dedicated to signals of the acknowledge type. Therefore, it is prevented that the master side fails in acquiring signals of the acknowledge type from the slave side, and the reliability of the source clock synchronous bus and the data efficiency can be improved.

Abstract: A communication system including a network and at least two terminal units connected thereto. Each terminal unit includes a session controlling unit for controlling a session for enabling transmission/receiving of voice, image, handwritten data to/from the remote terminal unit individually, and a display unit for displaying the image and the handwritten data. The image data and the handwritten data are overlapped and displayed on a display of the display unit.

Abstract: For improving data efficiency of a bus in a system using address/data multiplex bus, in a processor for information processing equipment, there are provided buffers which store plural sets of write addresses and data for a system bus, a comparator for deciding whether write addresses in succession forming a continuous write address exist in the write addresses stored in the buffers, and apparatus for converting access corresponding to writing operations for the continuous write addresses into a fixed length burst transfer protocol which can be transferred with a series of continuing data cycles following one address cycle, when the comparator 27 decides that write addresses in succession exist.

Abstract: A metallic contaminant detecting method and apparatus according to the present invention detect metallic contaminants mixed in objects under inspection, such as food products, pharmaceuticals, and materials for industrial use, which are wrapped in electrically conductive packaging materials, e.g. aluminum.

Abstract: A circuit includes a transmission function of transmitting data together with a source clock synchronized to the data to another module, a reception circuit for receiving the data outputted by the module and a source clock synchronized to the data, and a synchronization circuit for connecting the circuit having a transmission function to the reception circuit are formed on a single-chip integrated circuit. Even if the module connected to the bus is changed, i.e., even if the operation clock frequency of the module of the other party is changed, other modules can be used as they are without making any change. The cost needed at the time of system construction can thus be reduced. Furthermore, as for the aspect of performance, only one synchronization circuit is needed. The increase of latency caused by synchronization can also be suppressed to the minimum.

Abstract: A terminal device stores in a nonvolatile memory a video encoding method, a size expressed by pixels, a frame rate, a bit rate, and a key frame insertion interval suitable for reception. A receiving side terminal device notifies information to a sending side terminal. According to the information, the sending side terminal device encodes video data obtained by shooting an object and transmits encoded video data. Also, the sending side terminal device cuts, from the video data, video data of a size not exceeding a least size among a size of the video data obtained by the sending side terminal device, a size expressed by pixels suitable for transmission in the sending side terminal device, and a size expressed by pixels suitable for reception in the reception side terminal device. The sending side terminal device encodes and transmits the video data.

Abstract: An object is to provide a video recording/playing apparatus for facilitating recording/playing of motion pictures.

Abstract: An information processing system is configured such that which when an application handling multimedia, especially, moving images is performed by an information processor such as a personal computer, a sufficient processing performance is realized with the conventional CPU and bus capabilities. The information processing system includes a bus adaptor or bus converter for connecting a CPU bus and a system bus. The bus converter includes an operation processing unit (ALU) capable of performing a portion of an operating function performed by the conventional CPU or a portion of an operating function performed by an image processing board connected to the system bus, whereby the bus converter takes over a portion of a processing to be performed by the CPU or I/O module. Thereby, an overhead time for data transfer through the buses is reduced so that the total performance of the system is improved.

Abstract: The present invention provides a means for preventing execution of a transaction such as main storage access from obstruction by bus competition with low-speed IO access and improving the bus occupation efficiency. Apparatus for preventing execution of a transaction such as storage access from obstruction by bus competition with low-speed IO access. The invention includes a first bus, a second bus, a plurality of modules connected to both buses, a bus conversion unit for performing protocol conversion of information between both buses, a bus arbiter for arbitrating a bus occupation right request of a bus master, and a storage for storing access data up to a predetermined amount when the access destination is a predetermined module.

Abstract: An information processing apparatus includes a master module serving as a transfer source, a slave module serving as a transfer destination, a bus of a source clock synchronous system, and a means for transferring a signal based upon a protocol of an acknowledge type from the slave module to the master module via the bus of the source clock synchronous system. In the information processor, the signals of the acknowledge type are also transferred in the source clock synchronous system by using a source clock signal dedicated to signals of the acknowledge type. Therefore, it is prevented that the master side fails in acquiring signals of the acknowledge type from the slave side, and the reliability of the source clock synchronous bus and the data efficiency can be improved.

Abstract: An information processing system wherein a module to operate as a master which executes a read access to a module to operate as a slave requests a bus arbiter to afford the mastership of a bus with a bus mastership request signal, and it simultaneously asserts a last cycle signal so as to notify the bus arbiter of the fact that the next cycle will be the last cycle to be used by the master. Subsequently, when the master has had the use of the bus granted by a bus use grant signal from the bus arbiter, it transfers an address to the slave by the use of the bus in the next cycle, thereby starting the read access. After the read access, the master releases the bus mastership. Only when the slave has failed to accept the transferred address, does it assert a retry request signal two cycles after the transfer cycle of the address not accepted. In this case, the module having executed the transfer two cycles before the cycle of the asserted signal executes again the transfer executed before.

Abstract: An object is to provide a video recording/playing apparatus for facilitating recording/playing of motion pictures.

Abstract: In a data processing system, a plurality of modules connected to a system bus thereof are assigned with identifiers. When a source module initiates a split read access to another module, the source module sends an address of the access destination module and an identifier of the source module. When sending a response to the source module, the destination module returns response data and the identifier of the source module thereto. Checking the identifier from the destination module, the source module determines the response data returned as a response to the initiated access.

Abstract: An information processing apparatus includes a master module serving as a transfer source, a slave module serving as a transfer destination, a bus of a source clock synchronous system, and a means for transferring a signal based upon a protocol of an acknowledge type from the slave module to the master module via the bus of the source clock synchronous system. In the information processor, the signals of the acknowledge type are also transferred in the source clock synchronous system by using a source clock signal dedicated to signals of the acknowledge type. Therefore, it is prevented that the master side fails in acquiring signals of the acknowledge type from the slave side, and the reliability of the source clock synchronous bus and the data efficiency can be improved.

Abstract: In a data processing system, a plurality of modules connected to a system bus thereof are assigned with identifiers. When a source module initiates a split read access to another module, the source module sends an address of the access destination module and an identifier of the source module. When sending a response to the source module, the destination module returns response data and the identifier of the source module thereto. Checking the identifier from the destination module, the source module determines the response data returned as a response to the initiated access.

Abstract: The present invention provides a means for preventing execution of a transaction such as main storage access from obstruction by bus competition with low-speed IO access and improving the bus occupation efficiency.