Patents by Inventor Nobukazu Kondo
Nobukazu Kondo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 6425037Abstract: The present invention provides a means for preventing execution of a transaction such as main storage access from obstruction by bus competition with low-speed IO access and improving the bus occupation efficiency. The present invention includes a first bus, a second bus, a plurality of modules connected to both buses, a bus conversion means for performing protocol conversion of information between both buses, a bus arbiter for arbitrating a bus occupation right request of a bus master, and a storage means for storing access data up to a predetermined amount when the access destination is a predetermined module. Each bus master outputs access destination information and when the bus arbiter judges that one of the bus masters issues a bus occupation right request when it performs an access operation, the bus arbiter refers to the access destination information and the data storage status of the storage means and decides whether or not to give a bus occupation right to the bus master.Type: GrantFiled: September 28, 1999Date of Patent: July 23, 2002Assignee: Hitachi, Ltd.Inventors: Nobukazu Kondo, Koichi Okazawa, Yukihiro Seki, Ryuichi Hattori, Masaya Umemura, Shigemi Adachi, Kouichi Nakai, Takashi Moriyama
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Publication number: 20020032818Abstract: An information processing system is configured such that which when an application handling multimedia, especially, moving images is performed by an information processor such as a personal computer, a sufficient processing performance is realized with the conventional CPU and bus capabilities. The information processing system includes a bus adaptor or bus converter for connecting a CPU bus and a system bus. The bus converter includes an operation processing unit (ALU) capable of performing a portion of an operating function performed by the conventional CPU or a portion of an operating function performed by an image processing board connected to the system bus, whereby the bus converter takes over a portion of a processing to be performed by the CPU or I/O module. Thereby, an overhead time for data transfer through the buses is reduced so that the total performance of the system is improved.Type: ApplicationFiled: November 16, 2001Publication date: March 14, 2002Inventors: Nobukazu Kondo, Setsuko Kojima, Tomohisa Kohiyama, Shigeto Oeda
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Publication number: 20020032817Abstract: In a data processing system, a plurality of modules connected to a system bus thereof are assigned with identifiers. When a source module initiates a split read access to another module, the source module sends an address of the access destination module and an identifier of the source module. When sending a response to the source module, the destination module returns response data and the identifier of the source module thereto. Checking the identifier from the destination module, the source module determines the response data returned as a response to the initiated access.Type: ApplicationFiled: November 26, 2001Publication date: March 14, 2002Applicant: Hitachi, Ltd.Inventors: Nobukazu Kondo, Seiji Kaneko, Koichi Okazawa, Hideaki Gemma, Tetsuya Mochida, Takehisa Hayashi
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Patent number: 6341323Abstract: In a data processing system, a plurality of modules connected to a system bus thereof are assigned with identifiers. When a source module initiates a split read access to another module, the source module sends an address of the access destination module and an identifier of the source module. When sending a response to the source module, the destination module returns response data and the identifier of the source module thereto. Checking the identifier from the destination module, the source module determines the response data returned as a response to the initiated access.Type: GrantFiled: February 7, 2001Date of Patent: January 22, 2002Assignee: Hitachi, Ltd.Inventors: Nobukazu Kondo, Seiji Kaneko, Koichi Okazawa, Hideaki Gemma, Tetsuya Mochida, Takehisa Hayashi
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Publication number: 20010053271Abstract: An object is to provide a video recording/playing apparatus for facilitating recording/playing of motion pictures.Type: ApplicationFiled: June 8, 2001Publication date: December 20, 2001Applicant: HITACHI, LTD.Inventors: Masataka Okayama, Tomohisa Kohiyama, Nobukazu Kondo, Kazutoshi Katoh, Kazuaki Tanaka, Yoshihiro Harada
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Patent number: 6330629Abstract: An information processing system is configured such that which when an application handling multimedia, especially, moving images is performed by an information processor such as a personal computer, a sufficient processing performance is realized with the conventional CPU and bus capabilities. The information processing system includes a bus adaptor or bus converter for connecting a CPU bus and a system bus. The bus converter includes an operation processing unit (ALU) capable of performing a portion of an operating function performed by the conventional CPU or a portion of an operating function performed by an image processing board connected to the system bus, whereby the bus converter takes over a portion of a processing to be performed by the CPU or I/O module. Thereby, an overhead time for data transfer through the buses is reduced so that the total performance of the system is improved.Type: GrantFiled: April 1, 1998Date of Patent: December 11, 2001Assignee: Hitachi, Ltd.Inventors: Nobukazu Kondo, Setsuko Kojima, Tomohisa Kohiyama, Shigeto Oeda
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Publication number: 20010023462Abstract: In a data processing system, a plurality of modules connected to a system bus thereof are assigned with identifiers. When a source module initiates a split read access to another module, the source module sends an address of the access destination module and an identifier of the source module. When sending a response to the source module, the destination module returns response data and the identifier of the source module thereto. Checking the identifier from the destination module, the source module determines the response data returned as a response to the initiated access.Type: ApplicationFiled: February 7, 2001Publication date: September 20, 2001Applicant: Hitachi, Ltd.Inventors: Nobukazu Kondo, Seiji Kaneko, Koichi Okazawa, Hideaki Gemma, Tetsuya Mochida, Takehisa Hayashi
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Publication number: 20010016888Abstract: An information processing system wherein a module to operate as a master which executes a read access to a module to operate as a slave requests a bus arbiter to afford the mastership of a bus with a bus mastership request signal, and it simultaneously asserts a last cycle signal so as to notify the bus arbiter of the fact that the next cycle will be the last cycle to be used by the master. Subsequently, when the master has had the use of the bus granted by a bus use grant signal from the bus arbiter, it transfers an address to the slave by the use of the bus in the next cycle, thereby starting the read access. After the read access, the master releases the bus mastership. Only when the slave has failed to accept the transferred address, does it assert a retry request signal two cycles after the transfer cycle of the address not accepted. In this case, the module having executed the transfer two cycles before the cycle of the asserted signal executes again the transfer executed before.Type: ApplicationFiled: April 17, 2001Publication date: August 23, 2001Applicant: HITACHI, LTD.Inventors: Nobukazu Kondo, Seiji Kaneko, Hideaki Gemma, Tetsuhiko Okada, Kazuhiko Komori, Koichi Okazawa
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Patent number: 6269215Abstract: An object is to provide a video recording/playing apparatus for facilitating recording/playing of motion pictures.Type: GrantFiled: March 16, 2000Date of Patent: July 31, 2001Assignee: Hitachi, Ltd.Inventors: Masataka Okayama, Tomohisa Kohiyama, Nobukazu Kondo, Kazutoshi Katoh, Kazuaki Tanaka, Yoshihiro Harada
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Patent number: 6219735Abstract: An information processing system wherein a module to operate as a master which executes a read access to a module to operate as a slave requests a bus arbiter to afford the mastership of a bus with a bus mastership request signal, and it simultaneously asserts a last cycle signal so as to notify the bus arbiter of the fact that the next cycle will be the last cycle to be used by the master. Subsequently, when the master has had the use of the bus granted by a bus use grant signal from the bus arbiter, it transfers an address to the slave by the use of the bus in the next cycle, thereby starting the read access. After the read access, the master releases the bus mastership. Only when the slave has failed to accept the transferred address, does it assert a retry request signal two cycles after the transfer cycle of the address not accepted. In this case, the module having executed the transfer two cycles before the cycle of the asserted signal executes again the transfer executed before.Type: GrantFiled: January 5, 2000Date of Patent: April 17, 2001Assignee: Hitachi, Ltd.Inventors: Nobukazu Kondo, Seiji Kaneko, Hideaki Gemma, Tetsuhiko Okada, Kazuhiko Komori, Koichi Okazawa
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Patent number: 6219738Abstract: In a data processing system, a plurality of modules connected to a system bus thereof are assigned with identifiers. When a source module initiates a split read access to another module, the source module sends an address of the access destination module and an identifier of the source module. When sending a response to the source module, the destination module returns response data and the identifier of the source module thereto. Checking the identifier from the destination module, the source module determines the response data returned as a response to the initiated access.Type: GrantFiled: February 28, 2000Date of Patent: April 17, 2001Assignee: Hitachi, Ltd.Inventors: Nobukazu Kondo, Seiji Kaneko, Koichi Okazawa, Hideaki Gemma, Tetsuya Mochida, Takehisa Hayashi
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Patent number: 6128688Abstract: In a data processing system, a plurality of modules connected to a system bus thereof are assigned with identifiers. When a source module initiates a split read access to another module, the source module sends an address of the access destination module and an identifier of the source module. When sending a response to the source module, the destination module returns response data and the identifier of the source module thereto. Checking the identifier from the destination module, the source module determines the response data returned as a response to the initiated access.Type: GrantFiled: April 23, 1999Date of Patent: October 3, 2000Assignee: Hitachi, Ltd.Inventors: Nobukazu Kondo, Seiji Kaneko, Koichi Okazawa, Hideaki Gemma, Tetsuya Mochida, Takehisa Hayashi
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Patent number: 6094234Abstract: An information processing apparatus for processing video data and video data with audio data includes a scene change detecting device for particularly detecting a scene change of video data. The video data scene change detecting device includes an intra-coded frame detecting device for detecting a scene change between an intra-coded frame contained in video data and an intra-coded frame preceding the frame and a scene change information recording device for recording scene change information detected by the intra-coded frame detecting device.Type: GrantFiled: May 29, 1997Date of Patent: July 25, 2000Assignee: Hitachi, Ltd.Inventors: Itaru Nonomura, Takeo Tomokane, Nobukazu Kondo, Kazuaki Tanaka
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Patent number: 6094521Abstract: An object is to provide a video recording/playing apparatus for facilitating recording/playing of motion pictures.Type: GrantFiled: March 2, 1999Date of Patent: July 25, 2000Assignee: Hitachi, Ltd.Inventors: Masataka Okayama, Tomohisa Kohiyama, Nobukazu Kondo, Kazutoshi Katoh, Kazuaki Tanaka, Yoshihiro Harada
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Patent number: 6047345Abstract: An information processing system wherein a module to operate as a master which executes a read access to a module to operate as a slave requests a bus arbiter to afford the mastership of a bus with a bus mastership request signal, and it simultaneously asserts a last cycle signal so as to notify the bus arbiter of the fact that the next cycle will be the last cycle to be used by the master. Subsequently, when the master has had the use of the bus granted by a bus use grant signal from the bus arbiter, it transfers an address to the slave by the use of the bus in the next cycle, thereby starting the read access. After the read access, the master releases the bus mastership. Only when the slave has failed to accept the transferred address, does it assert a retry request signal two cycles after the transfer cycle of the address not accepted. In this case, the module having executed the transfer two cycles before the cycle of the asserted signal executes again the transfer executed before.Type: GrantFiled: May 14, 1998Date of Patent: April 4, 2000Assignee: Hitachi, Ltd.Inventors: Nobukazu Kondo, Seiji Kaneko, Hideaki Gemma, Tetsuhiko Okada, Kazuhiko Komori, Koichi Okazawa
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Patent number: 6021455Abstract: An information processing system includes a first bus, a second bus, a plurality of modules connected to both buses, a bus arbiter for arbitrating a bus access request of a bus master, and a storage means for storing access data up to a predetermined amount for one of modules when access destination information indicates that said module is the access destination. Each bus master outputs access destination information and when the bus arbiter judges that one of the bus masters issues a bus access request when it performs an access operation, the bus arbiter refers to whether the predetermined amount of access destination information is fully stored in the storage means, and decides whether or not to give a bus access to the bus master.Type: GrantFiled: September 5, 1996Date of Patent: February 1, 2000Assignee: Hitachi, Ltd.Inventors: Nobukazu Kondo, Koichi Okazawa, Yukihiro Seki, Ryuichi Hattori, Masaya Umemura, Shigemi Adachi, Kouichi Nakai, Takashi Moriyama
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Bus control system incorporating the coupling of two split-transaction busses of different hierarchy
Patent number: 5941973Abstract: In a data processing system, a plurality of modules connected to a system bus thereof are assigned with identifiers. When a source module initiates a split read access to another module, the source module sends an address of the access destination module and an identifier of the source module. When sending a response to the source module, the destination module returns response data and the identifier of the source module thereto. Checking the identifier from the destination module, the source module determines the response data returned as a response to the initiated access.Type: GrantFiled: December 1, 1998Date of Patent: August 24, 1999Assignee: Hitachi, Ltd.Inventors: Nobukazu Kondo, Seiji Kaneko, Koichi Okazawa, Hideaki Gemma, Tetsuya Mochida, Takehisa Hayashi -
Patent number: 5899575Abstract: An object is to provide a video recording/playing apparatus for facilitating recording/playing of motion pictures.Type: GrantFiled: December 13, 1996Date of Patent: May 4, 1999Assignee: Hitachi, Ltd.Inventors: Masataka Okayama, Tomohisa Kohiyama, Nobukazu Kondo, Kazutoshi Katoh, Kazuaki Tanaka, Yoshihiro Harada
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Bus control system incorporating the coupling of two split-transaction busses of different hierarchy
Patent number: 5881255Abstract: In a data processing system, a plurality of modules connected to a system bus thereof are assigned with identifiers. When a source module initiates a split read access to another module, the source module sends an address of the access destination module and an identifier of the source module. When sending a response to the source module, the destination module returns response data and the identifier of the source module thereto. Checking the identifier from the destination module, the source module determines the response data returned as a response to the initiated access.Type: GrantFiled: April 21, 1997Date of Patent: March 9, 1999Assignee: Hitachi, Ltd.Inventors: Nobukazu Kondo, Seiji Kaneko, Koichi Okazawa, Hideaki Gemma, Tetsuya Mochida, Takehisa Hayashi -
Patent number: 5774679Abstract: An information processing system wherein a module to operate as a master which executes a read access to a module to operate as a slave requests a bus arbiter to afford the mastership of a bus with a bus mastership request signal, and it simultaneously asserts a last cycle signal so as to notify the bus arbiter of the fact that the next cycle will be the last cycle to be used by the master. Subsequently, when the master has had the use of the bus granted by a bus use grant signal from the bus arbiter, it transfers an address to the slave by the use of the bus in the next cycle, thereby starting the read access. After the read access, the master releases the bus mastership. Only when the slave has failed to accept the transferred address, does it assert a retry request signal two cycles after the transfer cycle of the address not accepted. In this case, the module having executed the transfer two cycles before the cycle of the asserted signal executes again the transfer executed before.Type: GrantFiled: December 30, 1996Date of Patent: June 30, 1998Assignee: Hitachi, Ltd.Inventors: Nobukazu Kondo, Seiji Kaneko, Hideaki Gemma, Tetsuhiko Okada, Kazuhiko Komori, Koichi Okazawa