Patents by Inventor Nobuo Hayasaka

Nobuo Hayasaka has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20040043596
    Abstract: Form a trench in a major surface of a semiconductor substrate, then bury a paste in the trench. The paste contains solids having a conductive substance and a resin, and solvent for dissolving the resin. The solids content of the paste is not less than 60 vol % and a viscosity ratio thereof is not more than 2.
    Type: Application
    Filed: August 25, 2003
    Publication date: March 4, 2004
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Keiichi Sasaki, Manabu Kimura, Yoshimi Hisatsune, Nobuo Hayasaka
  • Publication number: 20040043602
    Abstract: A method of manufacturing semiconductor device which comprises the steps of forming an insulating film on an Si substrate provided with a wiring layer, forming a contact hole connected to the wiring layer and a wiring groove in the insulating film, filling the contact hole with an Si film, successively forming an Al film and a Ti film all over the substrate, performing a heat treatment thereby to substitute the Al film for the Ti film, and to allow the Si film to be absorbed by the Ti film, whereby filling the contact hole and wiring groove with the Al film, and removing a Ti/Ti silicide which is consisting of Ti silicide formed through the absorption of the Si film by the Ti film and a superfluous Ti, whereby filling the contact hole with an Al plug and filling the wiring groove with an Al wiring.
    Type: Application
    Filed: August 29, 2003
    Publication date: March 4, 2004
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Junichi Wada, Atsuko Sakata, Tomio Katata, Takamasa Usui, Masahiko Hasunuma, Hideki Shibata, Hisashi Kaneko, Nobuo Hayasaka, Katsuya Okumura
  • Patent number: 6673704
    Abstract: A method of manufacturing semiconductor device which comprises the steps of forming an insulating film on an Si substrate provided with a wiring layer, forming a contact hole connected to the wiring layer and a wiring groove in the insulating film, filling the contact hole with an Si film, successively forming an Al film and a Ti film all over the substrate, performing a heat treatment thereby to substitute the Al film for the Ti film, and to allow the Si film to be absorbed by the Ti film, whereby filling the contact hole and wiring groove with the Al film, and removing a Ti/Ti silicide which is consisting of Ti silicide formed through the absorption of the Si film by the Ti film and a superfluous Ti, whereby filling the contact hole with an Al plug and filling the wiring groove with an Al wiring.
    Type: Grant
    Filed: July 8, 2002
    Date of Patent: January 6, 2004
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Junichi Wada, Atsuko Sakata, Tomio Katata, Takamasa Usui, Masahiko Hasunuma, Hideki Shibata, Hisashi Kaneko, Nobuo Hayasaka, Katsuya Okumura
  • Patent number: 6657306
    Abstract: Form a trench in a major surface of a semiconductor substrate, then bury a paste in the trench. The paste contains solids having a conductive substance and a resin, and solvent for dissolving the resin. The solids content of the paste is not less than 60 vol % and a viscosity ratio thereof is not more than 2.
    Type: Grant
    Filed: November 28, 2000
    Date of Patent: December 2, 2003
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Keiichi Sasaki, Manabu Kimura, Yoshimi Hisatsune, Nobuo Hayasaka
  • Publication number: 20030210063
    Abstract: A contact probe is fabricated by a method including a lithography step and a plating step. The contact probe includes a plunger unit to form contact with a circuit to be tested, a spring unit, and a lead wire connection unit, all formed integrally so as to have a three dimensional configuration with uniform thickness with respect to a predetermined plane configuration in a thickness direction perpendicular to the predetermined plane configuration. Preferably, a guide unit parallel to the spring unit is also formed integrally. Further preferably, the contact probe is formed integrally also including a stopper for each unitary configuration of the spring unit constituted by a leaf spring.
    Type: Application
    Filed: May 23, 2003
    Publication date: November 13, 2003
    Applicants: SUMITOMO ELECTRIC INDUSTRIES, LTD., KABUSHIKI KAISHA TOSHIBA
    Inventors: Tsuyoshi Haga, Katsuya Okumura, Nobuo Hayasaka, Hideki Shibata, Noriaki Matsunaga
  • Patent number: 6632335
    Abstract: A plating method and apparatus for a substrate fills a metal, e.g., copper, into a fine interconnection pattern formed in a semiconductor substrate. The apparatus has a substrate holding portion 36 horizontally holding and rotating a substrate with its surface to be plated facing upward. A seal material 90 contacts a peripheral edge portion of the surface, sealing the portion in a watertight manner. A cathode electrode 88 passes an electric current upon contact with the substrate. A cathode portion 38 rotates integrally with the substrate holding portion 36. An electrode arm portion 30 is above the cathode portion 38 and movable horizontally and vertically and has an anode 98 face-down. Plating liquid is poured into a space between the surface to be plated and the anode 98 brought close to the surface to be plated. Thus, plating treatment and treatments incidental thereto can be performed by a single unit.
    Type: Grant
    Filed: December 22, 2000
    Date of Patent: October 14, 2003
    Assignees: Ebara Corporation, Kabushiki Kaisha Toshiba
    Inventors: Junji Kunisawa, Mitsuko Odagaki, Natsuki Makino, Koji Mishima, Kenji Nakamura, Hiroaki Inoue, Norio Kimura, Tetsuo Matsuda, Hisashi Kaneko, Nobuo Hayasaka, Katsuya Okumura, Manabu Tsujimura, Toshiyuki Morita
  • Publication number: 20030181041
    Abstract: There is provided a semiconductor device including a semiconductor substrate and a conductive layer above the semiconductor substrate, wherein the conductive layer contains copper, a surface region of the conductive layer contains at least one of C—H bonds and C—C bonds, and a total amount of C atoms forming the C—H bonds and C atoms forming the C—C bonds in the surface region is 30 atomic % or more of a whole amount of elements in the surface region.
    Type: Application
    Filed: March 21, 2003
    Publication date: September 25, 2003
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Hiroshi Ikegami, Rempei Nakata, Takashi Yoda, Nobuo Hayasaka, Yoshimi Hisatsune
  • Patent number: 6614106
    Abstract: A stacked circuit device comprises a base substrate having a terminal, an interposer arranged on the base substrate and formed of a semiconductor substrate, the interposer having a first terminal connected to the terminal of the base substrate, a second terminal, and a circuit coupled to the second terminal and including an active element, and an integrated circuit chip arranged on the interposer and having a terminal connected to the second terminal.
    Type: Grant
    Filed: September 21, 2001
    Date of Patent: September 2, 2003
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Mie Matsuo, Nobuo Hayasaka
  • Publication number: 20030162396
    Abstract: A gate insulation film is formed on a semiconductor substrate, gate electrodes are formed on the gate insulation film, and source/drain diffusion layers are formed. A silicon nitride films is formed on a side wall of the gate electrodes, a silicon oxide film is formed on the overall surface, and the silicon oxide film is etched back to have the same height as that of the gate electrodes so that the surface is flattened, and then the surface of the gate electrodes are etched by a predetermined thickness to form a first stepped portion from the silicon oxide film, the first stepped portion is filled up by a tungsten film, the surface of the tungsten film is etched by a predetermined thickness so that a second stepped portion is formed, and then the second stepped portion is filled by a silicon nitride films.
    Type: Application
    Filed: March 17, 2003
    Publication date: August 28, 2003
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Yusuke Kohyama, Nobuo Hayasaka, Katsuya Okumura
  • Patent number: 6608356
    Abstract: A gate insulation film is formed on semiconductor substrate, a gate electrodes are formed on the gate insulation film, and source/drain diffusion layers are formed. Silicon nitride films are formed on a side wall of the gate electrodes, a silicon oxide film is formed on the overall surface, and the silicon oxide film is etched back to have the same height as that of the gate electrodes so that the surface is flattened, and then the surface of the gate electrodes are etched by a predetermined thickness to form a first stepped portion from the silicon oxide film, the first stepped portion is filled up by a tungsten film, the surface of the tungsten film is etched by a predetermined thickness so that a second stepped portion is formed, and then the second stepped portion is filled by a silicon nitride film.
    Type: Grant
    Filed: July 14, 1997
    Date of Patent: August 19, 2003
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yusuke Kohyama, Nobuo Hayasaka, Katsuya Okumura
  • Publication number: 20030122252
    Abstract: After a barrier film is formed on a pad electrode, Ni particles having a diameter of 2 &mgr;m or less are selectively deposited on the barrier film, thereby forming a Ni fine particle film. Then, a bump electrode made of a solder ball is provided on the pad electrode through the Ni fine particle film. Thereafter, the bump electrode is melted by a heat treatment to join the Ni fine particle film to the bump electrode. Thus, a bump electrode structure is finished.
    Type: Application
    Filed: December 9, 2002
    Publication date: July 3, 2003
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Atsuko Sakata, Keiichi Sasaki, Nobuo Hayasaka, Katsuya Okumura, Hirotaka Nishino
  • Patent number: 6566261
    Abstract: There is provided a semiconductor device including a semiconductor substrate and a conductive layer above the semiconductor substrate, wherein the conductive layer contains copper, a surface region of the conductive layer contains at least one of C—H bonds and C—C bonds, and a total amount of C atoms forming the C—H bonds and C atoms forming the C—C bonds in the surface region is 30 atomic % or more of a whole amount of elements in the surface region.
    Type: Grant
    Filed: September 6, 2001
    Date of Patent: May 20, 2003
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hiroshi Ikegami, Rempei Nakata, Takashi Yoda, Nobuo Hayasaka, Yoshimi Hisatsune
  • Patent number: 6566632
    Abstract: An electrostatic chuck type of hot plate is disclosed which permits the temperature of a semiconductor substrate to be measured with good repeatability. In addition to an electrostatic chuck electrode and a heating electrode as provided in conventional hot plates, the inventive hot plate is further provided with two or more temperature measuring probes.
    Type: Grant
    Filed: February 15, 2000
    Date of Patent: May 20, 2003
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tomio Katata, Nobuo Hayasaka, Katsuya Okumura
  • Publication number: 20030067052
    Abstract: The present invention provides an integrated circuit, comprising a semiconductor substrate, an active element formed on the side of one main surface of the semiconductor substrate, an insulating region formed on the side of the main surface of the semiconductor substrate by burying an insulating material in a groove having a depth of at least 20 &mgr;m, and a passive element formed directly or indirectly on the insulating region. It is desirable for the passive element to be an inductor.
    Type: Application
    Filed: November 18, 2002
    Publication date: April 10, 2003
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Mie Matsuo, Nobuo Hayasaka, Noriaki Matsunaga, Katsuya Okumura
  • Patent number: 6538323
    Abstract: After a barrier film is formed on a pad electrode, Ni particles having a diameter of 2 &mgr;m or less are selectively deposited on the barrier film, thereby forming a Ni fine particle film. Then, a bump electrode made of a solder ball is provided on the pad electrode through the Ni fine particle film. Thereafter, the bump electrode is melted by a heat treatment to join the Ni fine particle film to the bump electrode. Thus, a bump electrode structure is finished.
    Type: Grant
    Filed: November 29, 1999
    Date of Patent: March 25, 2003
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Atsuko Sakata, Keiichi Sasaki, Nobuo Hayasaka, Katsuya Okumura, Hirotaka Nishino
  • Patent number: 6504227
    Abstract: The present invention provides an integrated circuit, comprising a semiconductor substrate, an active element formed on the side of one main surface of the semiconductor substrate, an insulating region formed on the side of the main surface of the semiconductor substrate by burying an insulating material in a groove having a depth of at least 20 &mgr;m, and a passive element formed directly or indirectly on the insulating region. It is desirable for the passive element to be an inductor.
    Type: Grant
    Filed: June 29, 2000
    Date of Patent: January 7, 2003
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Mie Matsuo, Nobuo Hayasaka, Noriaki Matsunaga, Katsuya Okumura
  • Publication number: 20020192938
    Abstract: A method of manufacturing semiconductor device which comprises the steps of forming an insulating film on an Si substrate provided with a wiring layer, forming a contact hole connected to the wiring layer and a wiring groove in the insulating film, filling the contact hole with an Si film, successively forming an Al film and a Ti film all over the substrate, performing a heat treatment thereby to substitute the Al film for the Ti film, and to allow the Si film to be absorbed by the Ti film, whereby filling the contact hole and wiring groove with the Al film, and removing a Ti/Ti silicide which is consisting of Ti silicide formed through the absorption of the Si film by the Ti film and a superfluous Ti, whereby filling the contact hole with an Al plug and filling the wiring groove with an Al wiring.
    Type: Application
    Filed: July 8, 2002
    Publication date: December 19, 2002
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Junichi Wada, Atsuko Sakata, Tomio Katata, Takamasa Usui, Masahiko Hasunuma, Hideki Shibata, Hisashi Kaneko, Nobuo Hayasaka, Katsuya Okumura
  • Patent number: 6475285
    Abstract: A deposition apparatus includes a chemical discharging nozzle for continuously discharging chemicals to a substrate to be processed, a gas spraying section arranged below the chemical discharging nozzle, for spraying gas on the chemicals discharged from the chemical discharging nozzle and changing an orbit of the chemicals by pressure of the gas, a chemical collecting section for collecting the chemicals the orbit of which is changed by the gas spraying section, the chemical collecting section being arranged so as to interpose the chemicals between the gas spraying section and the chemical collecting section, and a moving section for moving the chemical discharging nozzle and the substrate relatively with each other. The gas spraying section includes a laser oscillator for emitting a laser beam, and a gas generating film that generates the gas when heated and gasified by the laser beam emitted from the laser oscillator.
    Type: Grant
    Filed: March 27, 2001
    Date of Patent: November 5, 2002
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hiroshi Ikegami, Nobuo Hayasaka, Shinichi Ito, Katsuya Okumura
  • Publication number: 20020143656
    Abstract: There is provided a method for trading electronic products by transmitting/receiving electronic data by way of a communication network, the method comprising prompting an expected buyer of an electronic product to input a specification of the electronic product the expected buyer wants to buy, extracting the electronic product which meets the specification of the electronic product from a database, and outputting information of the electronic product to a manufacturer.
    Type: Application
    Filed: March 8, 2002
    Publication date: October 3, 2002
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Mie Matsuo, Nobuo Hayasaka
  • Publication number: 20020136971
    Abstract: A laser processing apparatus comprises a laser oscillator for producing a laser beam to selectively remove part of a substrate to be processed, a scanning system for applying the laser beam to an arbitrary position of the substrate and incident means for applying the laser beam to the substrate substantially at right angle.
    Type: Application
    Filed: March 8, 2002
    Publication date: September 26, 2002
    Applicant: KABUSHIKI KAISHA
    Inventors: Shinichi Ito, Tatsuhiko Higashiki, Hiroshi Ikegami, Nobuo Hayasaka