Patents by Inventor Nobuo Hayasaka
Nobuo Hayasaka has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20010015133Abstract: In a gas recovery system, before gases including PFC are diluted with nitrogen gas, a cooling mechanism trap separates the gases into PFC and the other gases, and the separated PFC is stored temporarily in a temporary storage mechanism until it reaches a concentration at which an efficient recovery of PFC is possible, and thereafter, the temporarily stored PFC is packed in a cylinder.Type: ApplicationFiled: December 21, 2000Publication date: August 23, 2001Inventors: Itsuko Sakai, Junko Ohuchi, Tokuhisa Ohiwa, Nobuo Hayasaka, Katsuya Okumura
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Patent number: 6239495Abstract: A multichip semiconductor device comprises a plurality of semiconductor chips, each including elements integrated in a semiconductor substrate. The semiconductor chips have substantially the same structure. Each semiconductor chip includes a connecting plug inserted in a through hole made through the semiconductor substrate. The semiconductor chips are stacked in layers. The connecting plugs of the semiconductor chips are selectively connected through metal bumps. Allocation of addresses of the semiconductor chips is designated by a connecting pattern of the bumps.Type: GrantFiled: July 29, 1999Date of Patent: May 29, 2001Assignee: Kabushiki Kaisha ToshibaInventors: Koji Sakui, Junichi Miyamoto, Nobuo Hayasaka, Katsuya Okumura
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Patent number: 6235624Abstract: Form a trench in a major surface of a semiconductor substrate, then bury a paste in the trench. The paste contains solids having a conductive substance and a resin, and solvent for dissolving the resin. The solids content of the paste is not less than 60 vol % and a viscosity ratio thereof is not more than 2.Type: GrantFiled: May 28, 1999Date of Patent: May 22, 2001Assignee: Kabushiki Kaisha ToshibaInventors: Keiichi Sasaki, Manabu Kimura, Nobuo Hayasaka
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Patent number: 6224464Abstract: According to the present invention, there is provided a polishing method having the steps of forming a film to be polished, having a depressed portion and a protruding portion on a surface of a substrate, and polishing the film to be polished by relatively moving the substrate and a polishing table, while pressing the substrate having the film to be polished, onto a polishing cloth of the polishing table and supplying a polishing solution containing polishing grains, between the film to be polished and the polishing cloth, wherein an organic compound having a molecular weight of 100 or more, and containing at least one hydrophilic group selected from the group consisting of COOM1 (M represents an atom or a functional group which can form a salt when substituted with a hydrogen atom of a carboxyl group), SO3H (sulfo group) and SO3M2 (M2 represents an atom or a functional group which can form a salt when substituted with a hydrogen atom of a carboxyl group) is added to the polishing solution.Type: GrantFiled: December 11, 1996Date of Patent: May 1, 2001Assignee: Kabushiki Kaisha ToshibaInventors: Haruki Nojo, Rempei Nakata, Masako Kodera, Nobuo Hayasaka
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Patent number: 6164295Abstract: There is provided a CVD apparatus and a cleaning method which can precisely perform cleaning at a high speed, in order to increase the throughput of a CVD apparatus. A film formation gas (e.g., SiH.sub.4 and O.sub.2 gases) is introduced from a source gas supply pipe into a chamber to form a silicon oxide film (SiO.sub.2) on a wafer placed on a susceptor by using a plasma or the like. A thin film (SiO.sub.2) mainly consisting of silicon and oxygen, an imperfect oxide film of silicon, or the like also attaches to a wall surface and the respective surfaces of a window plate, a vacuum seal portion, the susceptor, an electrode, an insulator, an exhaust pipe, and the like in the chamber. An HF-based gas supply system for a cleaning etching gas is arranged to clean the interior of the chamber of the CVD apparatus. Particularly, a film formed with a source gas of Si.sub.x H.sub.2x+2 (x=1, 2, 3) and O.sub.2 is more perfect than an imperfect oxide film (e.g.Type: GrantFiled: April 29, 1997Date of Patent: December 26, 2000Assignee: Kabushiki Kaisha ToshibaInventors: Akio Ui, Naruhiko Kaji, Hideshi Miyajima, Nobuo Hayasaka
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Patent number: 6165617Abstract: A resin-coated copper foil for use in a multilayer printed wiring board, characterized by having on one surface thereof a resin composition comprising, based on the total amount of the resin components, 50 to 90% by weight of epoxy resins, 5 to 20% by weight of a polyvinyl acetal resin, and 0.1 to 20% by weight of an urethane resin, with the proviso that 0.5 to 40% by weight of the epoxy resins is a rubber-modified epoxy resin; and a multilayer printed wiring board using the resin-coated copper foil therein.Type: GrantFiled: December 31, 1997Date of Patent: December 26, 2000Assignee: Mitsui Mining & Smelting Co., Ltd.Inventors: Tetsurou Satoh, Hiroaki Tsuyoshi, Nobuo Hayasaka
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Patent number: 6096631Abstract: The present invention provides a method of manufacturing a semiconductor device, including the steps of forming a first film on an entire surface of a substrate having a recessed portion, including a bottom surface and a side wall of the recessed portion, without completely filling the recessed portion, forming a second film on an entire surface of the first film such that the recessed portion, on the bottom surface and the side wall of which the first film is formed, is completely filled, and polishing the first and second films by a chemical-mechanical polishing method such that the substrate is exposed and the first and second films in the recessed portion remain.Type: GrantFiled: May 19, 1998Date of Patent: August 1, 2000Assignee: Kabushiki Kaisha ToshibaInventors: Kenro Nakamura, Rempei Nakata, Yusuke Kohyama, Nobuo Hayasaka
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Patent number: 6090701Abstract: A method for the production of a semiconductor device having an electrode line formed in a semiconducting substrate is disclosed which comprises preparing a semiconducting substrate having trenches and/or contact holes formed preparatorily in a region destined to form the electrode line, forming a conductive film formed mainly of at least one member selected from among Cu, Ag, and Au on the surface of the semiconducting substrate, heat-treating the superposed Cu film while supplying at least an oxidizing gas thereto thereby flowing the Cu film to fill the trenches and/or contact holes, and removing by polishing the part of the conductive film which falls outside the region of the electrode line and completing the electrode lines consequently. During the heat treatment, a reducing gas is supplied in addition to the oxidizing gas to induce a local oxidation-reduction reaction and fluidify and/or flow the conductive film and consequently accomplish the embodiment of the conductive film in the trenches.Type: GrantFiled: June 20, 1995Date of Patent: July 18, 2000Assignee: Kabushiki Kaisha ToshibaInventors: Masahiko Hasunuma, Sachiyo Ito, Keizo Shimamura, Hisashi Kaneko, Nobuo Hayasaka, Junsei Tsutsumi, Akihiro Kajita, Junichi Wada, Haruo Okano
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Patent number: 6071810Abstract: A method of manufacturing semiconductor device which comprises the steps of forming an insulating film on an Si substrate provided with a wiring layer, forming a contact hole connected to the wiring layer and a wiring groove in the insulating film, filling the contact hole with an Si film, successively forming an Al film and a Ti film all over the substrate, performing a heat treatment thereby to substitute the Al film for the Ti film, and to allow the Si film to be absorbed by the Ti film, whereby filling the contact hole and wiring groove with the Al film, and removing a Ti/Ti silicide which is consisting of Ti silicide formed through the absorption of the Si film by the Ti film and a superfluous Ti, whereby filling the contact hole with an Al plug and filling the wiring groove with an Al wiring.Type: GrantFiled: December 23, 1997Date of Patent: June 6, 2000Assignee: Kabushiki Kaisha ToshibaInventors: Junichi Wada, Atsuko Sakata, Tomio Katata, Takamasa Usui, Masahiko Hasunuma, Hideki Shibata, Hisashi Kaneko, Nobuo Hayasaka, Katsuya Okumura
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Patent number: 5851842Abstract: The measurement system comprises a holder for holding a dielectric film formed on at least a semiconductive substrate and sandwiched between the substrate and a conductive film, voltage application terminals for applying voltage between the substrate and the conductive film, variable voltage source for supplying the voltage to the voltage application terminals, a light source for irradiating the dielectric film with light including wavelength of an infrared region and transmitting the light through the dielectric film, light absorbance detector receiving the light transmitted through the dielectric film, for detecting absorbance of an absorbed light component in an absorption wavelength region intrinsic to the dielectric film, and a potential difference measurement unit for measuring a potential difference between the substrate and the conductive film of the dielectric film on the basis of change in absorbance of the light component when the voltage is changed by the variable voltage source.Type: GrantFiled: May 15, 1997Date of Patent: December 22, 1998Assignee: Kabushiki Kaisha ToshibaInventors: Ryota Katsumata, Nobuo Hayasaka, Naoki Yasuda, Hideshi Miyajima, Iwao Higashikawa, Masaki Hotta
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Patent number: 5775980Abstract: This invention provides a polishing method including the steps of forming a film to be polished on a substrate having a recessed portion in its surface so as to fill at least the recessed portion, and selectively leaving the film to be polished behind in the recessed portion by polishing the film by using a polishing agent containing polishing particles and a solvent, and having a pH of 7.5 or more. The invention also provides a polishing apparatus including a polishing agent storage vessel for storing a polishing agent, a turntable for polishing an object to be polished, a polishing agent supply pipe for supplying the polishing agent from the polishing agent storage vessel onto the turntable, a polishing object holding jig for holding the object to be polished such that the surface to be polished of the object opposes the turntable, and a polishing agent supply pipe temperature adjusting unit, connected to the polishing agent supply pipe, for adjusting the temperature of the polishing agent.Type: GrantFiled: November 4, 1996Date of Patent: July 7, 1998Assignee: Kabushiki Kaisha ToshibaInventors: Yasutaka Sasaki, Mie Matsuo, Rempei Nakata, Junichi Wada, Nobuo Hayasaka, Hiroyuki Yano, Haruo Okano
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Patent number: 5770095Abstract: The present invention provides a polishing method including the steps of forming a film made of material containing a metal as a main component over a substrate having depressed portions on a surface thereof so as to fill the depressed portions with the film, and polishing the film by a chemical mechanical polishing method using a polishing agent containing a chemical agent responsible for forming a protection film on a surface of the film by reacting with the material containing a metal as a main component, thereby forming a conductive film in the depressed portions.Type: GrantFiled: July 11, 1995Date of Patent: June 23, 1998Assignee: Kabushiki Kaisha ToshibaInventors: Yasutaka Sasaki, Nobuo Hayasaka, Hisashi Kaneko, Hideaki Hirabayashi, Masatoshi Higuchi
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Patent number: 5731634Abstract: The present invention provides a method of manufacturing a semiconductor device, including the steps of forming a metal oxide film made of a metal oxide having a decrease in standard free energy smaller than a decrease in standard free energy of hydrogen oxide or of carbon oxide, on an insulating film formed on a semiconductor substrate, forming a metal oxide film pattern by subjecting a treatment to the metal oxide film, and converting said metal oxide pattern into at least one of an electrode and a wiring made of a metal which is a main component constituting the metal oxide, by reducing the metal oxide film pattern at a temperature of 80.degree. to 500.degree. C.Type: GrantFiled: June 6, 1996Date of Patent: March 24, 1998Assignee: Kabushiki Kaisha ToshibaInventors: Mie Matsuo, Haruo Okano, Nobuo Hayasaka, Kyoichi Suguro, Hideshi Miyajima, Jun-ichi Wada
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Patent number: 5664989Abstract: A polishing pad comprises at least a first layer having a first main surface serving to polish a substrate to be polished and a second main surface, and a second layer positioned to face the second main surface of the first layer and having fine bags arranged therein, fluid being hermetically sealed in the fine bag.Type: GrantFiled: July 18, 1996Date of Patent: September 9, 1997Assignee: Kabushiki Kaisha ToshibaInventors: Rempei Nakata, Hisashi Kaneko, Nobuo Hayasaka, Takeshi Nishioka, Yoshikuni Tateyama, Yutaka Nakano, Yasutaka Sasaki
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Patent number: 5661345Abstract: The method of producing a semiconductor device includes the steps of forming a groove having a predetermined pattern shape on the surface of a substrate; forming a metal film on the substrate while reaction with the surface of the substrate is suppressed; and agglomerating the metal film by in-situ annealing, wherein agglomeration of the metal film is started before the metal film reacts with the surface of the substrate due to annealing, while formation of a native oxide on the metal film is suppressed, and whereby the metal film is filled into the groove by annealing at a predetermined temperature for a predetermined period of time. The structure of the semiconductor device includes an insulator in which there is formed a groove portion having a predetermined pattern shape and an electrode interconnection made of a single-crystal metal which is filled in the groove portion.Type: GrantFiled: December 1, 1994Date of Patent: August 26, 1997Assignee: Kabushiki Kaisha ToshibaInventors: Junichi Wada, Hisashi Kaneko, Kyoichi Suguro, Nobuo Hayasaka, Haruo Okano
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Patent number: 5641581Abstract: Disclosed is a method of manufacturing a semiconductor device, in which a silicon oxide film containing fluorine, said film exhibiting a low dielectric constant and a low hygroscopicity and acting as an insulating film for electrically isolating wirings included in a semiconductor device, is formed by a plasma CVD method using a source gas containing at least silicon, oxygen and fluorine, under the conditions that the relationship between the gas pressure P (Torr) and the ion energy E (eV) satisfies formula A given below:P.gtoreq.5.times.10.sup.-4, P.ltoreq.10.sup.-1.times.10.sup.-E/45( A)and the relationship between the ion energy E (eV) and the plasma density D (/cm.sup.3) satisfies the formula B given below:D.gtoreq.2.times.10.sup.11.times.10.sup.-E/45, 10 .ltoreq.Type: GrantFiled: March 28, 1995Date of Patent: June 24, 1997Assignee: Kabushiki Kaisha ToshibaInventors: Yukio Nishiyama, Rempei Nakata, Nobuo Hayasaka, Haruo Okano, Riichirou Aoki, Takahito Nagamatsu, Akemi Satoh, Masao Toyosaki, Hitoshi Ito
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Patent number: 5629236Abstract: The method of manufacturing a semiconductor device, according to the present invention, includes the steps of forming a polycrystal lower-level Al wiring layer on a silicon substrate, forming an interlayer insulation film for covering the lower-level Al wiring layer on the entire surface, forming a connection hole which reaches the lower-level Al wiring layer in the interlayer insulation film, forming a polycrystal upper-level Al wiring layer on a surface of the interlayer insulation film, forming an interlayer insulation film for covering the upper-level Al wiring layer on the entire surface, and forming a single-crystal lower-level Al wiring layer and upper-layer Al wiring layer which are connected to each other in the connection hole by heating the silicon substrate so that the lower-level Al wiring layer and the upper-level Al wiring layer are converted from a polycrystal phase to an amorphous phase, and then cooling the silicon substrate so that the upper-level Al wiring layer is set in a supercooling stType: GrantFiled: July 25, 1995Date of Patent: May 13, 1997Assignee: Kabushiki Kaisha ToshibaInventors: Jun-ichi Wada, Hisashi Kaneko, Nobuo Hayasaka
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Patent number: 5607718Abstract: This invention provides a polishing method including the steps of forming a film to be polished on a substrate having a recessed portion in its surface so as to fill at least the recessed portion, and selectively leaving the film to be polished behind in the recessed portion by polishing the film by using a polishing agent containing polishing particles and a solvent, and having a pH of 7.5 or more. The invention also provides a polishing apparatus including a polishing agent storage vessel for storing a polishing agent, a turntable for polishing an object to be polished, a polishing agent supply pipe for supplying the polishing agent from the polishing agent storage vessel onto the turntable, a polishing object holding jig for holding the object to be polished such that the surface to be polished of the object opposes the turntable, and a polishing agent supply pipe temperature adjusting unit, connected to the polishing agent supply pipe, for adjusting the temperature of the polishing agent.Type: GrantFiled: September 2, 1994Date of Patent: March 4, 1997Assignee: Kabushiki Kaisha ToshibaInventors: Yasutaka Sasaki, Mie Matsuo, Rempei Nakata, Junichi Wada, Nobuo Hayasaka, Hiroyuki Yano, Haruo Okano
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Patent number: 5561082Abstract: The present invention provides a method of manufacturing a semiconductor device, including the steps of forming a metal oxide film made of a metal oxide having a decrease in standard free energy smaller than a decrease in standard free energy of hydrogen oxide or of carbon oxide, on an insulating film formed on a semiconductor substrate, forming a metal oxide film pattern by subjecting a treatment to the metal oxide film, and converting said metal oxide pattern into at least one of an electrode and a wiring made of a metal which is a main component constituting the metal oxide, by reducing the metal oxide film pattern at a temperature of 80.degree. to 500.degree. C.Type: GrantFiled: March 17, 1995Date of Patent: October 1, 1996Assignee: Kabushiki Kaisha ToshibaInventors: Mie Matsuo, Haruo Okano, Nobuo Hayasaka, Kyoichi Suguro, Hideshi Miyajima, Jun-ichi Wada
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Patent number: 5514425Abstract: A thin film-forming method according to the present invention is characterized by comprising the steps of introducing TiCl.sub.4, hydrogen, nitrogen and NF.sub.3 into a film-forming chamber containing a semiconductor substrate (1) having a groove made in its surface, after the chamber has been evacuated to 10.sup.-4 Torr or less; and converting these gases into plasma, thereby forming a thin TiN film on only that portion of the groove which is other than the wall surfaces of the groove.Type: GrantFiled: March 6, 1995Date of Patent: May 7, 1996Assignees: Kabushiki Kaisha Toshiba, Tokyo Electron Limited, Tokyo Electron Yamanashi LimitedInventors: Hitoshi Ito, Kyoichi Suguro, Nobuo Hayasaka, Haruo Okano, Shinji Himori, Kazuya Nagaseki, Syuji Mochizuki