Patents by Inventor Nobuo Hayasaka

Nobuo Hayasaka has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20020127812
    Abstract: A probe pin for testing electric characteristics of a semiconductor device comprises a silicon pin core (3, 23, 33), and a conductive film (4, 24, 34) covering the entire surface, including the bottom face, of the pin core. The bottom face of the probe pin is connected directly to an electrode (7, 37) positioned in or on a print wiring board. A number of probe pins can be connected to the associated electrodes at a high density, thereby forming a fine-pitch probe card having a superior high-frequency signal characteristic.
    Type: Application
    Filed: December 8, 2000
    Publication date: September 12, 2002
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Noriaki Matsunaga, Hideki Shibata, Nobuo Hayasaka
  • Patent number: 6440843
    Abstract: A method of manufacturing semiconductor device which comprises the steps of forming an insulating film on an Si substrate provided with a wiring layer, forming a contact hole connected to the wiring layer and a wiring groove in the insulating film, filling the contact hole with an Si film, successively forming an Al film and a Ti film all over the substrate, performing a heat treatment thereby to substitute the Al film for the Ti film, and to allow the Si film to be absorbed by the Ti film, whereby filling the contact hole and wiring groove with the Al film, and removing a Ti/Ti silicide which is consisting of Ti silicide formed through the absorption of the Si film by the Ti film and a superfluous Ti, whereby filling the contact hole with an Al plug and filling the wiring groove with an Al wiring.
    Type: Grant
    Filed: April 21, 2000
    Date of Patent: August 27, 2002
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Junichi Wada, Atsuko Sakata, Tomio Katata, Takamasa Usui, Masahiko Hasunuma, Hideki Shibata, Hisashi Kaneko, Nobuo Hayasaka, Katsuya Okumura
  • Patent number: 6419557
    Abstract: A polishing method including applying a polishing agent containing polishing grains and a surfactant onto an oxide film, which is formed on a substrate having a depressed portion and a protruding portion, wherein the surfactant is an organic compound including at least one hydrophilic group selected from the group consisting of COOH, COOM1, wherein M1 represents an atom or a functional group which can form a salt when substituted for a hydrogen atom of a carboxyl group, SO3H and SO3M2, wherein M2 represents an atom or a functional group which can form a salt when substituted for a hydrogen atom of a sulfo group; and polishing the film until the film is flattened without the occurrence of dishing.
    Type: Grant
    Filed: April 16, 2001
    Date of Patent: July 16, 2002
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Haruki Nojo, Rempei Nakata, Masako Kodera, Nobuo Hayasaka
  • Publication number: 20020081863
    Abstract: A method of manufacturing a semiconductor device comprises preparing a substrate to be treated, and forming an insulation film above the substrate, which includes applying an insulation film raw material above the substrate, the insulation film raw material including a substance or a precursor of the substance, the insulation film comprising the substance, curing the insulation film raw material by irradiating an electron beam on the substrate while heating the substrate in a reactor chamber, changing at least one of parameter selected from the group consisting of pressure in the reactor chamber, temperature of the substrate, type of gas having the substrate exposed thereto, flow rate of gas introduced into the reactor chamber, position of the substrate, and quantity of electrons incident to the substrate per unit time when the electron beam is being irradiated on the substrate.
    Type: Application
    Filed: October 19, 2001
    Publication date: June 27, 2002
    Inventors: Miyoko Shimada, Hideshi Miyajima, Rempei Nakata, Hideto Matsuyama, Katsuya Okumura, Masahiko Hasunuma, Nobuo Hayasaka
  • Patent number: 6409780
    Abstract: Water-laden solid matter is provided which is obtained by adding 40 to 300 weight parts of water to 100 weight parts of inorganic oxide particles synthesized by fumed process or metal evaporation oxidation process, slurry for polishing is provided which is manufactured by using the water-laden solid matter, and a method for manufacturing a semiconductor device using the above slurry. Said water-laden solid matter is within a range of 0.3 to 3 g/cm3 in bulk density and within a range of 0.5 to 100 mm&phgr; in average particle size when manufactured granular. Said slurry for polishing is manufactured from the water-laden solid matter, and the average particle size thereof after being dispersed in water is within a range of 0.05 to 1.0 &mgr;m.
    Type: Grant
    Filed: January 14, 2000
    Date of Patent: June 25, 2002
    Assignees: Kabushiki Kaisha Toshiba, JSR Corporation
    Inventors: Hiroyuki Yano, Nobuo Hayasaka, Katsuya Okumura, Akira Iio, Masayuki Hattori, Kiyonobu Kubota
  • Publication number: 20020061657
    Abstract: A method of manufacturing a semiconductor device according to an aspect of the present invention comprises forming a low dielectric constant insulating film having a siloxane bond as main skeleton on a semiconductor substrate, causing a surfactant to permeate the low dielectric constant insulating film, and conducting a predetermined step on the low dielectric constant insulating film permeated with the surfactant in a state adapted to be exposed to water.
    Type: Application
    Filed: September 25, 2001
    Publication date: May 23, 2002
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Hideshi Miyajima, Nobuhide Yamada, Nobuo Hayasaka, Nobuyuki Kurashima
  • Publication number: 20020050489
    Abstract: In a laser beam machining method, a liquid, through which a laser beam can be transmitted, is supplied to the target surface of an object to be processed. A laser beam is guided to the target surface through the liquid. The laser beam processes the target surface under the application of ultrasonic vibration.
    Type: Application
    Filed: October 25, 2001
    Publication date: May 2, 2002
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Hiroshi Ikegami, Nobuo Hayasaka
  • Publication number: 20020050647
    Abstract: There is provided a semiconductor device including a semiconductor substrate and a conductive layer above the semiconductor substrate, wherein the conductive layer contains copper, a surface region of the conductive layer contains at least one of C—H bonds and C—C bonds, and a total amount of C atoms forming the C—H bonds and C atoms forming the C—C bonds in the surface region is 30 atomic % or more of a whole amount of elements in the surface region.
    Type: Application
    Filed: September 6, 2001
    Publication date: May 2, 2002
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Hiroshi Ikegami, Rempei Nakata, Takashi Yoda, Nobuo Hayasaka, Yoshimi Hisatsune
  • Patent number: 6376894
    Abstract: There is provided a semiconductor device in which redundancy fuses formed in an upper layer wiring region can be cut without damaging an underlying Si substrate or adjacent regions. The semiconductor device comprises a lower layer wiring formed within an interlayer insulating film on the Si substrate, and an upper layer metal wiring made of Al, Cu or the like, formed above the lower layer wiring and connected thereto through a via metal, wherein the redundancy fuses are formed in the same wiring layer as the upper layer metal wiring. For cutting a fuse by irradiating with a laser having a wavelength in a range of 1,000 to 1,100 nm and a beam diameter D (&mgr;m), the fuse may be designed to have a film thickness T (&mgr;m) and a width W (&mgr;m) which satisfy T≦(−0.15 (D+2&sgr;)+0.
    Type: Grant
    Filed: March 14, 2000
    Date of Patent: April 23, 2002
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hiroshi Ikegami, Keiichi Sasaki, Nobuo Hayasaka
  • Patent number: 6375545
    Abstract: It is an object of the present invention to provide an aqueous dispersion and CMP slurry that can achieve polishing at an adequate rate without producing scratches in the polishing surfaces of wafer working films, and a polishing process for wafer surfaces and a process for manufacture of a semiconductor device using them. A CMP slurry and the like of the present invention contains polymer particles with a crosslinked structure and a mean particle size of 0.13-0.8 &mgr;m. The CMP slurry may contain no surfactant, and may contain the surfactant of not greater than 0.15 wt %. A CMP slurry and the like of another present invention contains polymer particles and inorganic particles of silica, aluminum and the like. A mean particle size of the polymer particles may be not greater than a mean particle size of the inorganic particles. And the mean particle size of the inorganic coagulated particles may be 0.1-1.0 &mgr;m, and may be smaller than the mean particle size of the polymer particles.
    Type: Grant
    Filed: January 18, 2000
    Date of Patent: April 23, 2002
    Assignees: Kabushiki Kaisha Toshiba, JSR Corporation
    Inventors: Hiroyuki Yano, Gaku Minamihaba, Yukiteru Matsui, Nobuo Hayasaka, Katsuya Okumura, Akira Iio, Masayuki Hattori, Masayuki Motonari
  • Publication number: 20020036340
    Abstract: A stacked circuit device comprises a base substrate having a terminal, an interposer arranged on the base substrate and formed of a semiconductor substrate, the interposer having a first terminal connected to the terminal of the base substrate, a second terminal, and a circuit coupled to the second terminal and including an active element, and an integrated circuit chip arranged on the interposer and having a terminal connected to the second terminal.
    Type: Application
    Filed: September 21, 2001
    Publication date: March 28, 2002
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Mie Matsuo, Nobuo Hayasaka
  • Publication number: 20020036338
    Abstract: Provided is a stacked type semiconductor device formed of a plurality of semiconductor integrated circuit devices stacked, each having a specification and including a semiconductor integrated circuit chip, wherein at least three of the semiconductor integrated circuit devices are stacked in the order of a value of the specification.
    Type: Application
    Filed: September 25, 2001
    Publication date: March 28, 2002
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Mie Matsuo, Nobuo Hayasaka, Tsunetoshi Arikado, Hidemi Ishiuchi, Koji Sakui, Chiaki Takubo
  • Publication number: 20020020627
    Abstract: This invention relates, particularly, to a plating method and apparatus for a substrate for uses, such as the filling of a metal, e.g., copper (Cu), into a fine interconnection pattern (recesses) formed in a semiconductor substrate.
    Type: Application
    Filed: December 22, 2000
    Publication date: February 21, 2002
    Inventors: Junji Kunisawa, Mitsuko Odagaki, Natsuki Makino, Koji Mishima, Kenji Nakamura, Hiroaki Inoue, Norio Kimura, Tetsuo Matsuda, Hisashi Kaneko, Nobuo Hayasaka, Katsuya Okumura, Manabu Tsujimura, Toshiyuki Morita
  • Publication number: 20020000821
    Abstract: A contact probe is fabricated by a method including a lithography step and a plating step. The contact probe includes a plunger unit to form contact with a circuit to be tested, a spring unit, and a lead wire connection unit, all formed integrally so as to have a three dimensional configuration with uniform thickness with respect to a predetermined plane configuration in a thickness direction perpendicular to the predetermined plane configuration. Preferably, a guide unit parallel to the spring unit is also formed integrally. Further preferably, the contact probe is formed integrally also including a stopper for each unitary configuration of the spring unit constituted by a leaf spring.
    Type: Application
    Filed: May 30, 2001
    Publication date: January 3, 2002
    Inventors: Tsuyoshi Haga, Katsuya Okumura, Nobuo Hayasaka, Hideki Shibata, Noriaki Matsunaga
  • Patent number: 6334928
    Abstract: A semiconductor wafer etching system exhausts an exhaust gas including fluorocarbon gas to an exhaust line. Two traps, that are capable of trapping the fluorocarbon gas in the exhaust gas by cooled adsorption and releasing the adsorbed fluorocarbon gas by heating, are alternately arranged on the exhaust line. The two traps are alternately separated from the exhaust gas and regenerated on a regeneration line which serves to release the adsorbed fluorocarbon gas from the traps. The trap which is in the trap mode to adsorb the fluorocarbon gas is cooled to −120° C. or less. The trap which is in the regeneration mode to release the adsorbed fluorocarbon gas is heated to −100° C. or more.
    Type: Grant
    Filed: January 29, 1999
    Date of Patent: January 1, 2002
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Makoto Sekine, Nobuo Hayasaka, Katsuya Okumura
  • Patent number: 6333215
    Abstract: A method of manufacturing a semiconductor device, which comprises the steps of subjecting a solid material to a first treatment consisting of a thermal treatment and/or a chemical treatment thereby to obtain a treated solid material having desired properties, and adhering the treated solid material onto a substrate for the semiconductor device, thereby to form a thin film on the substrate.
    Type: Grant
    Filed: June 17, 1998
    Date of Patent: December 25, 2001
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tetsuo Matsuda, Nobuo Hayasaka
  • Publication number: 20010034191
    Abstract: According to the present invention, there is provided a polishing method having the steps of forming a film to be polished, having a depressed portion and a protruding portion on a surface of a substrate, and polishing the film to be polished by relatively moving the substrate and a polishing table, while pressing the substrate having the film to be polished, onto a polishing cloth of the polishing table and supplying a polishing solution containing polishing grains, between the film to be polished and the polishing cloth, wherein an organic compound having a molecular weight of 100 or more, and containing at least one hydrophilic group selected from the group consisting of COOM1 (M represents an atom or a functional group which can form a salt when substituted with a hydrogen atom of a carboxyl group), SO3H (sulfo group) and SO3M2 (M2 represents an atom or a functional group which can form a salt when substituted with a hydrogen atom of a carboxyl group) is added to the polishing solution.
    Type: Application
    Filed: April 16, 2001
    Publication date: October 25, 2001
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Haruki Nojo, Rempei Nakata, Masako Kodera, Nobuo Hayasaka
  • Patent number: 6306756
    Abstract: A method for the production of a semiconductor device having an electrode line formed in a semiconducting substrate is disclosed which comprises preparing a semiconducting substrate having trenches and/or contact holes formed preparatorily in a region destined to form the electrode line, forming a conductive film formed mainly of at least one member selected from among Cu, Ag, and Au on the surface of the semiconducting substrate, heat-treating the superposed Cu film while supplying at least an oxidizing gas thereto thereby flowing the Cu film and causing never melting to fill the trenches and/or contact holes, and removing by polishing the part of the conductive film which falls outside the region of the electrode line and completing the electrode lines consequently.
    Type: Grant
    Filed: May 26, 2000
    Date of Patent: October 23, 2001
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Masahiko Hasunuma, Sachiyo Ito, Keizo Shimamura, Hisashi Kaneko, Nobuo Hayasaka, Junsei Tsutsumi, Akihiro Kajita, Junichi Wada, Haruo Okano
  • Publication number: 20010027748
    Abstract: A deposition apparatus includes a chemical discharging nozzle for continuously discharging chemicals to a substrate to be processed, a gas spraying section arranged below the chemical discharging nozzle, for spraying gas on the chemicals discharged from the chemical discharging nozzle and changing an orbit of the chemicals by pressure of the gas, a chemical collecting section for collecting the chemicals the orbit of which is changed by the gas spraying section, the chemical collecting section being arranged so as to interpose the chemicals between the gas spraying section and the chemical collecting section, and a moving section for moving the chemical discharging nozzle and the substrate relatively with each other. The gas spraying section includes a laser oscillator for emitting a laser beam, and a gas generating film that generates the gas when heated and gasified by the laser beam emitted from the laser oscillator.
    Type: Application
    Filed: March 27, 2001
    Publication date: October 11, 2001
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Hiroshi Ikegami, Nobuo Hayasaka, Shinichi Ito, Katsuya Okumura
  • Publication number: 20010024691
    Abstract: This invention relates to a semiconductor substrate processing apparatus and method for forming interconnects by filling a circuit pattern groove and/or a hole formed in a semiconductor substrate with a plated metal film, and removing the plated metal film while leaving the metal film at the filled portion. The apparatus comprises a carry-in and carry-out section for carrying in and carrying out a semiconductor substrate, which has a circuit formed on a surface thereof, in a dry state; a plated metal film forming unit for forming a plated metal film on the semiconductor substrate which has been carried in; a bevel etching unit for etching a peripheral edge portion of the semiconductor substrate; a polishing unit for polishing at least part of the plated metal film on the semiconductor substrate; and a transport mechanism for transporting the semiconductor substrate between the above units.
    Type: Application
    Filed: May 25, 2001
    Publication date: September 27, 2001
    Inventors: Norio Kimura, Koji Mishima, Junji Kunisawa, Mitsuko Odagaki, Natsuki Makino, Manabu Tsujimura, Hiroaki Inoue, Kenji Nakamura, Moriji Matsumoto, Tetsuo Matsuda, Hisashi Kaneko, Toshiyuki Morita, Nobuo Hayasaka, Katsuya Okumura