Abstract: A 32-bit instruction 50 is composed of a 4-bit format field 51, a 4-bit operation field 52, and two 12-bit operation fields 59 and 60. The 4-bit operation field 52 can only include (1) an operation code "cc" that indicates a branch operation which uses a stored value of the implicitly indicated constant register 36 as the branch address, or (2) a constant "const". The content of the 4-bit operation field 52 is specified by a format code provided in the format field 51.

Abstract: A microprocessor used in an image information processing system is provided. The microprocessor includes: decryption unit 59 for decrypting the encrypted compressed AV data; IDCT unit 58 for performing an inverse DCT to decompress the decrypted compressed AV data; and microprogram memory 54 for storing microprograms for executing the AV data reproduction instruction which performs decryption and decompression of the encrypted compressed AV data inseparably by using the decryption unit 59 and IDCT unit 58.

Abstract: A data processor comprises a processing unit which processes an instruction in pipeline stages, the number of which is switchable between n and m, m being a larger number than n. The data processor also comprises a switching unit for switching the number of the pipeline stages of the processing unit between n and m. The switching unit comprises an indicating unit for indicating whether the data processor is in a first operating condition or in a second operating condition, depending either on the frequency of the operation clock provided for the data processor or on the power source voltage supplied to the data processor, and a pipeline control unit for ordering a processing unit to operate in n stages under the first operation condition, and for ordering the processing unit to operate in m stages under the second operating condition.

Abstract: A program translating apparatus is composed of a translation unit 103 and a link unit 108. The translation unit 103 includes a determination unit 105 which detects the stack size to be needed for each subroutine included in a source program to be translated into a machine instruction sequence and the name of a register to be retrieved in the process of each subroutine. The determination unit 105 then stores the stack size and the name detected into a file together with the machine instruction sequence. The link unit 108 includes the following units: A branch instruction detection unit 109 detects a branch instruction from the machine instruction sequence when machine instruction sequences stored in different files are linked each other. A file detection unit 110 and an acquisition unit 111 retrieve the stack size and the register name from the file which has the branch target subroutine.

Abstract: A processor which executes positive conversion processing, which converts coded data into uncoded data, and saturation calculation processing, which rounds a value to an appropriate number of bits, at high speed. When a positive conversion saturation calculation instruction "MCSST D1" is decoded, the sum-product result register 6 outputs its held value to the path P1. The comparator 22 compares the magnitude of the held value of the sum-product result register 6 with the coded 32-bit integer "0x0000.sub.-- 00FF". The polarity judging unit 23 judges whether the eighth bit of the value held by the sum-product result register 6 is "ON". The multiplexer 24 outputs one of the maximum value "0x0000.sub.-- 00FF" generated by the constant generator 21, the zero value "0x0000.sub.-- 0000" generated by the zero generator 25, and the held value of the sum-product result register 6 to the data bus 18.

Abstract: A branch instruction includes a set of branch prediction information 13b and a set of branch history information 13c. The set of branch prediction information 13b is made up of 1 bit which predicts whether a branch will be performed during the next execution of the instruction. The set of branch history information 13c is made up of 2 bits showing a frequency, with which the branch has been taken, is "very high", "high", "low" or "very low". An instruction fetching unit 12 prefetches an instruction from a cache memory 11a in accordance with the set of branch prediction information 13b. After an instruction executing unit 15 completes an execution of the branch instruction, a branch history information generating unit 16 generates a new set of branch history information and a branch prediction information generating unit 17 generates a new set of branch prediction information, in accordance with the execution result and the preceding branch history information 13c.

Abstract: An information processing device, including a main processor and a coprocessor for processing data according to instructions stored in memory, which is composed of an instruction bus for transmitting instructions from memory to the main processor and coprocessor; a first bus used for transmitting data from the main processor to the coprocessor; a second bus used for transmitting data from the coprocessor to the main processor; instruction detecting means for detecting coprocessor calculation instructions out of the instructions received from memory; operand identifying means for identifying source registers and destination registers specified by operands in a detected instruction; data supplying means for supplying data from the identified source registers to the coprocessor via the first bus; data storing means for storing coprocessor calculation results in the identified destination registers; coprocessor instruction detecting means for detecting coprocessor calculation instructions out of all of the instru

Abstract: The present data processing apparatus effects the pipeline operation for each of the machine cycle time with a plurality of pipeline stages processed in parallel. With respect to a load & extension instruction for instructing with the single instruction a first processing portion for reading the data shorter than the register length from RAM 19 and a second processing portion for zero-extending or the sign-extending the data into the register length, a zero-extension or a sign-extension operation in the second processing operation is executed, in a pipeline stream different from the pipeline stream where a first processing operation is executed or in a pipeline stage different from the pipeline stage where the reading from the storage portion of the first processing operation is executed.

Abstract: A compiler comprises a loop detecting unit for extracting information of loops, and a high-speed loop applying unit generating a first loop exclusive instruction, placing the instruction immediately before the entry of a loop, generating second loop exclusive instructions, and placing the instruction at each place to branch to the entry of the loop.

Abstract: A processor including an arithmetic operation circuit and a saturation operation correction circuit both of which are connected in parallel to a register and a data bus and are activated by respective operation instructions. The saturation operation correction circuit judges whether an output from a register file exceeds either of a predetermined upper-most value and a predetermined lower-most value, and selectively outputs one of an operation result, the upper-most value, and the lower-most value.

Abstract: An information processing apparatus for executing a program, the apparatus including: a register set made up of a plurality of registers; a decoding unit for decoding machine language instructions in the program and extracting a selected instruction which indicates data transfer between a plurality of registers designated by a first operand, which is made up of a single field of at least one bit which shows whether an individual register out of the register set is designated and a group field which shows whether a plurality of other registers out of the register set are designated as a group, and consecutive addresses of memory designated by a second operand as an effective address of memory; a determining unit for determining whether each bit in the single field and group field of the first operand of the extracted machine language instruction is valid; a first generating unit for generating a register number for a register corresponding to a bit determined as being valid in the single field, a second genera

Abstract: A program translating apparatus is composed of a translation unit 103 and a link unit 108. The translation unit 103 includes a determination unit 105 which detects the stack size to be needed for each subroutine included in a source program to be translated into a machine instruction sequence and the name of a register to be retrieved in the process of each subroutine. The determination unit 105 then stores the stack size and the name detected into a file together with the machine instruction sequence. The link unit 108 includes the following units: A branch instruction detection unit 109 detects a branch instruction from the machine instruction sequence when machine instruction sequences stored in different files are linked each other. A file detection unit 110 and an acquisition unit 111 retrieve the stack size and the register name from the file which has the branch target subroutine.

Abstract: An interrupt control device of an embedded microcomputer including I/O devices and a processor core comprising: a program storage unit for storing interrupt processing programs, each corresponding to an interrupt level of an interrupt request signal, in sequential areas; a start address hold unit for holding start addresses, which can be updated, of the interrupt processing programs; a level hold unit for holding an interrupt level, which can be updated, of each interrupt signal inputted from the I/O devices; an interrupt reception unit for, when at least one of the interrupt signals is inputted, receiving an interrupt signal of a highest interrupt level out of the inputted interrupt signals and outputting an interrupt request signal of the same interrupt level; and a control unit for controlling a branch, when the interrupt request signal is outputted, by fetching one of the start addresses which corresponds to the interrupt level of the interrupt request signal from the start address hold unit and setting t

Abstract: The data processors of the present invention transfer the contents of address registers and program registers through an unused bus during the cycle of writing into registers and execute, in one cycle, a load instruction or a store instruction that requires address calculation, although the processors have two buses and one arithmetic/logic unit. Also, the data processors assign basic arithmetic instructions between registers and load/store instructions instruction codes having a basic instruction word length of one byte by functionally dividing general purpose-registers into four address registers and four data registers.

Abstract: The object of the present invention is to provide an interruption processing apparatus which allows for improvements in operational speed and offers flexibility for a variety of systems, while using a lower amount of hardware. When an interruption occurs, then for the present invention shown in FIG. 2 , the corresponding interruption request flag in the interruption control register 1 in the group interruption control unit 5 is set. The interruption request unit 2 then outputs the interruption signal to the CPU 6 based on the interruption request flag. The interruption level arbitration unit 3 adjusts any conflict with other group control units and outputs, as the arbitration result, a signal showing whether output is possible or not for the interruption signal. The group number output unit 4 then outputs the fixed group number for the group in accordance with the arbitration result in response to access from the CPU 6.

Abstract: A data processing apparatus is described, including a first bus connecting an instruction storage unit and an instruction preparation unit, a second bus connecting an instruction execution unit and a data storage unit, a bus switch selectively connecting and disconnecting the first and second buses electrically, and a control unit controlling the operation of the bus switch responding to the operations of the instruction preparation unit and the instruction execution unit. When the first and second buses are connected by the bus switch, access from the instruction preparation unit to the data storage unit and access from the instruction execution unit to the instruction storage unit can be performed. On the other hand when the buses are not connected, instruction fetch from the instruction preparation unit and data access from the instruction execution unit can be concurrently performed.