Abstract: In order to overcome the problem that conditionally executed instructions are executed as no-operation instructions if their condition is not fulfilled, leading to poor utilization efficiency of the hardware and lowering the effective performance, the processor decodes a number of instructions that is greater than the number of provided computing units and judges their execution conditions with an instruction issue control portion before the execution stage, Instructions for which the condition is false are invalidated, and subsequent valid instructions are assigned so that the computing units (hardware) is used efficiently. A compiler performs scheduling such that the number of instructions whose execution condition is true does not exceed the upper limit of the degree of parallelism of the hardware. The number of instructions arranged in parallel at each cycle may exceed the degree of parallelism of the hardware.

Abstract: When a branch instruction is decoded by the instruction decoders 409a˜409c, the upper 29 bits of the PC relative value included in the branch instruction are sent to the upper PC calculator 411 and the lower 3 bits are sent to the lower PC calculator 405. The lower PC calculator 405 adds the lower 3 bits of the PC relative value and the lower 3 bits of the present lower PC 404 and sends the result to the lower PC 404 as the updated lower PC. The upper PC calculator 411 adds the upper 29 bits of the PC relative value, the upper 29 bits of the present upper PC 403, and a carry that may be received from the lower PC calculator 405, and sends the result to the upper PC 403 as the updated upper PC.

Abstract: In order to overcome the problem that conditionally executed instructions are executed as no-operation instructions if their condition is not fulfilled, leading to poor utilization efficiency of the hardware and lowering the effective performance, the processor decodes a number of instructions that is greater than the number of provided computing units and judges their execution conditions with an instruction issue control portion before the execution stage, Instructions for which the condition is false are invalidated, and subsequent valid instructions are assigned so that the computing units (hardware) is used efficiently. A compiler performs scheduling such that the number of instructions whose execution condition is true does not exceed the upper limit of the degree of parallelism of the hardware. The number of instructions arranged in parallel at each cycle may exceed the degree of parallelism of the hardware.

Abstract: A compiler device includes a conditional-executable-instruction generation unit and a branch instruction insertion unit. The conditional-executable-instruction generation unit generates a conditional executable instruction that is executed when a condition that the conditional executable instruction refers to is satisfied. In the case where there is a section containing a non-executive condition under which no instruction is executed in one cycle or a plurality of cycles in series, the branch instruction insertion unit inserts a conditional branch instruction that refers to the non-executive condition and instructs to branch to a cycle immediately after a last cycle of the section, to after an instruction of a cycle immediately before a start of the section.

Abstract: The invention provides a face region estimating device capable of extracting a person's face region even when an illumination environment, for example, is changed and persons with different skin colors are contained in a picked-up image taken by a camera. The face region estimating device includes: a mobile body detecting unit for extracting the outline of a mobile body from the picked-up image and for generating an object distance image composed of pixels corresponding to a distance in which the mobile body exists; a head region setting unit for setting a head region based on the pixel distribution in the object distance image corresponding to a predetermined range on the basis of a pixel position at the upper part of the outline; and a face region extracting unit for extracting the person's face region from the picked-up image based on the color distribution in the picked-up image corresponding to the head region.

Abstract: The control apparatus for a movable robot comprises: environment information acquisition means (such as video camera 3 and microphone 4); a current position detecting means (15); a map storage (7); a control parameter storage (9) for storing control parameters adjusted to different environments; and control means (11, 12) for determining a current position of the robot on the map data based on a signal from the current position detecting means, retrieving control parameters suitable for the current position from the parameter storage, and controlling the environment information acquisition means or actuators for moving the robot by using the retrieved control parameters.

Abstract: When a branch instruction is decoded by the instruction decoders 409a-409c, the upper 29 bits of the PC relative value included in the branch instruction are sent to the upper PC calculator 411 and the lower 3 bits are sent to the lower PC calculator 405. The lower PC calculator 405 adds the lower 3 bits of the PC relative value and the lower 3 bits of the present lower PC 404 and sends the result to the lower PC 404 as the updated lower PC. The upper PC calculator 411 adds the upper 29 bits of the PC relative value, the upper 29 bits of the present upper PC 403, and a carry that may be received from the lower PC calculator 405, and sends the result to the upper PC 403 as the updated upper PC.

Abstract: When a branch instruction is decoded by the instruction decoders 409a˜409c, the upper 29 bits of the PC relative value included in the branch instruction are sent to the upper PC calculator 411 and the lower 3 bits are sent to the lower PC calculator 405. The lower PC calculator 405 adds the lower 3 bits of the PC relative value and the lower 3 bits of the present lower PC 404 and sends the result to the lower PC 404 as the updated lower PC. The upper PC calculator 411 adds the upper 29 bits of the PC relative value, the upper 29 bits of the present upper PC 403, and a carry that may be received from the lower PC calculator 405, and sends the result to the upper PC 403 as the updated upper PC.

Abstract: When a branch instruction is decoded by the instruction decoders 409a˜409c, the upper 29 bits of the PC relative value included in the branch instruction are sent to the upper PC calculator 411 and the lower 3 bits are sent to the lower PC calculator 405. The lower PC calculator 405 adds the lower 3 bits of the PC relative value and the lower 3 bits of the present lower PC 404 and sends the result to the lower PC 404 as the updated lower PC. The upper PC calculator 411 adds the upper 29 bits of the PC relative value, the upper 29 bits of the present upper PC 403, and a carry that may be received from the lower PC calculator 405, and sends the result to the upper PC 403 as the updated upper PC.

Abstract: A face identification apparatus for identifying a face is designed to have a face region expectation measure for expecting his/her face region within the image; a pupil-candidate-point detection measure for converting the face region to an image of a standard size, making it a standard image, and detecting his/her right/left pupil candidate points out of a search region within the standard image; a reference data generation measure for generating a normalization image from the standard image with making it a standard a distance of the right/left pupil candidate points and making reference data for evaluating advisability of the face region from the normalization image; and a face region evaluation measure for obtaining a degree of approximation between the reference data and standard data prepared in advance and evaluating the advisability of the face region.

Abstract: A contour detecting apparatus for accurately detecting a contour of a target object without increasing the detection time is disclosed. The apparatus comprises a section for storing a contour model consisting of nodes, which surrounds at least one target object in a captured image and is used for detecting a contour of the target object; a deforming section for contracting or expanding the contour model by shifting the nodes based on a predetermined rule; a section for calculating a distance between two non-adjacent nodes of the contour model which was deformed by the deforming section, and determining that the contour model is to be split when the calculated distance is equal to or smaller than a predetermined threshold; and a section for splitting the contour model according to a result of the above determination, wherein the splitting operation is executed in the vicinity of said non-adjacent nodes.

Abstract: The present invention detects a moving object by generating the distance information of the moving object, detecting the object motion, determining the object distance, detecting the object image area and the object contour from the video image that includes the object image and contour, and provides a moving object detection apparatus to carry out such detection as well as detecting a contour of the specific moving object by detecting the center of the moving object in high precision.

Abstract: A compound device has the structural hardware of a digital television, is connected to an antenna and a telephone station, and by reading out and running either a digital television (DTV) program or a base station program with a general processor, it has both the function of a digital television and the function of a portable telephone base station. The owner of the compound device receives discounts in their subscribed telephone fee or their power fee based on records in a communication record portion. Thus, a compound device in which a digital television is given the function of a portable telephone base station is provided, so that a novel infrastructure can be achieved in which insufficiencies in base stations are made up for without requiring equipment investment expenditures and portable device owners are given financial benefits in compensation for allowing the public use of their private possession as a portable telephone base station.

Abstract: A circuit group control system which receives from a master processor a first command sequence and a second command sequence each of which is composed of a plurality of commands, each command being to be executed by one of a plurality of circuits, and causes any available circuits to execute the commands one by one in order of arrangement in each command sequence. The circuit group control system achieves concurrent execution of a plurality of command sequences by causing a circuit (a second circuit) to execute a command in the second command sequence while another circuit (a first circuit) is executing another command in the first command sequence.

Abstract: A circuit group control system which receives from a master processor a first command sequence and a second command sequence each of which is composed of a plurality of commands, each command being to be executed by one of a plurality of circuits, and causes any available circuits to execute the commands one by one in order of arrangement in each command sequence. The circuit group control system achieves concurrent execution of a plurality of command sequences by causing a circuit (a second circuit) to execute a command in the second command sequence while another circuit (a first circuit) is executing another command in the first command sequence.

Abstract: A processor which decodes and executes an instruction sequence includes: a state hold unit for holding, when a predetermined instruction is executed, a renewal state for an execution result of the predetermined instruction; an obtaining unit for obtaining an instruction sequence composed of instructions matching instructions assigned to an instruction set of the processor, where the instruction set is assigned first conditional instructions, a first state condition for a first conditional instruction being mutually exclusive with a second state condition for a second conditional instruction which has a same operation code as the first conditional instruction, the instruction set not being assigned the second conditional instruction, and the first state condition and the second state condition specifying either of one state and a plurality of states; a decoding unit for decoding each instruction in the obtained instruction sequence one by one; a judging unit for judging whether the renewal state is included in

Abstract: When a branch instruction is decoded by the instruction decoders 409a˜409c, the upper 29 bits of the PC relative value included in the branch instruction are sent to the upper PC calculator 411 and the lower 3 bits are sent to the lower PC calculator 405. The lower PC calculator 405 adds the lower 3 bits of the PC relative value and the lower 3 bits of the present lower PC 404 and sends the result to the lower PC 404 as the updated lower PC. The upper PC calculator 411 adds the upper 29 bits of the PC relative value, the upper 29 bits of the present upper PC 403, and a carry that may be received from the lower PC calculator 405, and sends the result to the upper PC 403 as the updated upper PC.

Abstract: A signal-processing apparatus comprises an instruction-parallel processor, a first data-parallel processor, a second data-parallel processor, and a motion detection unit, a de-blocking filtering unit and a variable-length coding/decoding unit which are dedicated hardware. With this structure, in signal processing of an image compression and decompression algorithm with a large processing amount, the load is distributed between software and hardware, so that the signal-processing apparatus can realize high processing capability and flexibility.

Abstract: In an event site or the like, a visitor may waste time and effort trying to find a spot where an event of interest may be taking place because the visitor is unable to look through the entire site from any particular spot. An information gathering robot roams in such an event site typically along a prescribed route, and notes spots of interest to transmit this information to a data server. The visitor can access the data server to find a spot of interest of his or her choice substantially on a real time basis.

Abstract: A processor which executes positive conversion processing, which converts coded data into uncoded data, and saturation calculation processing, which rounds a value to an appropriate number of bits, at high speed. When a positive conversion saturation calculation instruction “MCSST D1” is decoded, the sum-product result register 6 outputs its held value to the path P1. The comparator 22 compares the magnitude of the held value of the sum-product result register 6 with the coded 32-bit integer “0x0000_00FF”. The polarity judging unit 23 judges whether the eighth bit of the value held by the sum-product result register 6 is “ON”. The multiplexer 24 outputs one of the maximum value “0x0000_00FF” generated by the constant generator 21, the zero value “0x0000_0000” generated by the zero generator 25, and the held value of the sum-product result register 6 to the data bus 18.