Abstract: A compiler device includes a conditional-executable-instruction generation unit and a branch instruction insertion unit. The conditional-executable-instruction generation unit generates a conditional executable instruction that is executed when a condition that the conditional executable instruction refers to is satisfied. In the case where there is a section containing a non-executive condition under which no instruction is executed in one cycle or a plurality of cycles in series, the branch instruction insertion unit inserts a conditional branch instruction that refers to the non-executive condition and instructs to branch to a cycle immediately after a last cycle of the section, to after an instruction of a cycle immediately before a start of the section.

Abstract: A compound device has the structural hardware of a digital television, is connected to an antenna and a telephone station, and by reading out and running either a digital television (DTV) program or a base station program with a general processor, it has both the function of a digital television and the function of a portable telephone base station. The owner of the compound device receives discounts in their subscribed telephone fee or their power fee based on records in a communication record portion. Thus, a compound device in which a digital television is given the function of a portable telephone base station is provided, so that a novel infrastructure can be achieved in which insufficiencies in base stations are made up for without requiring equipment investment expenditures and portable device owners are given financial benefits in compensation for allowing the public use of their private possession as a portable telephone base station.

Abstract: The present invention provides a system for recognizing gestures made by a moving subject. The system comprises a sound detector for detecting sound, one or more image sensors for capturing an image of the moving subject, a human recognizer for recognizing a human being from the image captured by said one or more image sensors, and a gesture recognizer, activated when human voice is identified by said sound detector, for recognizing a gesture of the human being.

Abstract: A 32-bit instruction 50 is composed of a 4-bit format field 51, a 4-bit operation field 52, and two 12-bit operation fields 59 and 60. The 4-bit operation field 52 can only include (1) an operation code “cc” that indicates a branch operation which uses a stored value of the implicitly indicated constant register 36 as the branch address, or (2) a constant “const”. The content of the 4-bit operation field 52 is specified by a format code provided in the format field 51.

Abstract: A 32-bit instruction 50 is composed of a 4-bit format field 51, a 4-bit operation field 52, and two 12-bit operation fields 59 and 60. The 4-bit operation field 52 can only include (1) an operation code “cc” that indicates a branch operation which uses a stored value of the implicitly indicated constant register 36 as the branch address, or (2) a constant “const”. The content of the 4-bit operation field 52 is specified by a format code provided in the format field 51.

Abstract: When a branch instruction is decoded by the instruction decoders 409a˜409c, the upper 29 bits of the PC relative value included in the branch instruction are sent to the upper PC calculator 411 and the lower 3 bits are sent to the lower PC calculator 405. The lower PC calculator 405 adds the lower 3 bits of the PC relative value and the lower 3 bits of the present lower PC 404 and sends the result to the lower PC 404 as the updated lower PC. The upper PC calculator 411 adds the upper 29 bits of the PC relative value, the upper 29 bits of the present upper PC 403, and a carry that may be received from the lower PC calculator 405, and sends the result to the upper PC 403 as the updated upper PC.

Abstract: When a branch instruction is decoded by the instruction decoders 409a˜409c, the upper 29 bits of the PC relative value included in the branch instruction are sent to the upper PC calculator 411 and the lower 3 bits are sent to the lower PC calculator 405. The lower PC calculator 405 adds the lower 3 bits of the PC relative value and the lower 3 bits of the present lower PC 404 and sends the result to the lower PC 404 as the updated lower PC. The upper PC calculator 411 adds the upper 29 bits of the PC relative value, the upper 29 bits of the present upper PC 403, and a carry that may be received from the lower PC calculator 405, and sends the result to the upper PC 403 as the updated upper PC.

Abstract: A 32-bit instruction 50 is composed of a 4-bit format field 51, a 4-bit operation field 52, and two 12-bit operation fields 59 and 60. The 4-bit operation field 52 can only include (1) an operation code “cc” that indicates a branch operation which uses a stored value of the implicitly indicated constant register 36 as the branch address, or (2) a constant “const”. The content of the 4-bit operation field 52 is specified by a format code provided in the format field 51.

Abstract: When a branch instruction is decoded by the instruction decoders 409a˜409c, the upper 29 bits of the PC relative value included in the branch instruction are sent to the upper PC calculator 411 and the lower 3 bits are sent to the lower PC calculator 405. The lower PC calculator 405 adds the lower 3 bits of the PC relative value and the lower 3 bits of the present lower PC 404 and sends the result to the lower PC 404 as the updated lower PC. The upper PC calculator 411 adds the upper 29 bits of the PC relative value, the upper 29 bits of the present upper PC 403, and a carry that may be received from the lower PC calculator 405, and sends the result to the upper PC 403 as the updated upper PC.

Abstract: A contour detecting apparatus for accurately detecting a contour of a target object without increasing the detection time is disclosed. The apparatus comprises a section for storing a contour model consisting of nodes, which surrounds at least one target object in a captured image and is used for detecting a contour of the target object; a deforming section for contracting or expanding the contour model by shifting the nodes based on a predetermined rule; a section for calculating a distance between two non-adjacent nodes of the contour model which was deformed by the deforming section, and determining that the contour model is to be split when the calculated distance is equal to or smaller than a predetermined threshold; and a section for splitting the contour model according to a result of the above determination, wherein the splitting operation is executed in the vicinity of said non-adjacent nodes.

Abstract: A processor can decode short instructions with a word length equal to one unit field and long instructions with a word length equal to two unit fields. An opcode of each kind of instruction is arranged into the first unit field assigned to the instruction. The number of instructions to be executed by the processor in parallel is s. When the ratio of short to long instructions is s-1:1, the s-1 short instructions are assigned to the first unit field to the s-1th unit field in the parallel execution code, and the long instruction is assigned to the sth unit field to the (s+k−1)th unit field in the same parallel execution code.

Abstract: The processor according to the present invention includes a flag register that stores a first flag group and a second flag group. The second flag group includes the same operation flags (a carry flag and an overflow flag) as the first flag group. The processor executes first-type instructions and second-type instructions. The first-type instruction instructs to perform an operation and to update the first flag group according to the result of the operation. The second-type instruction instructs to perform an operation different from the operation in the first-type instruction and updates the second flag group according to the result of the operation.

Abstract: A processor which executes positive conversion processing, which converts coded data into uncoded data, and saturation calculation processing, which rounds a value to an appropriate number of bits, at high speed. When a positive conversion saturation calculation instruction “MCSST D1” is decoded, the sum-product result register 6 outputs its held value to the path P1. The comparator 22 compares the magnitude of the held value of the sum-product result register 6 with the coded 32-bit integer “0x0000_00FF”. The polarity judging unit 23 judges whether the eighth bit of the value held by the sum-product result register 6 is “ON”. The multiplexer 24 outputs one of the maximum value “0x0000_00FF” generated by the constant generator 21, the zero value “0x0000_0000” generated by the zero generator 25, and the held value of the sum-product result register 6 to the data bus 18.

Abstract: A processor which decodes and executes an instruction sequence includes: a state hold unit for holding, when a predetermined instruction is executed, a renewal state for an execution result of the predetermined instruction; an obtaining unit for obtaining an instruction sequence composed of instructions matching instructions assigned to an instruction set of the processor, where the instruction set is assigned first conditional instructions, a first state condition for a first conditional instruction being mutually exclusive with a second state condition for a second conditional instruction which has a same operation code as the first conditional instruction, the instruction set not being assigned the second conditional instruction, and the first state condition and the second state condition specifying either of one state and a plurality of states; a decoding unit for decoding each instruction in the obtained instruction sequence one by one; a judging unit for judging whether the renewal state is included in

Abstract: An instruction conversion apparatus and method for converting instruction sequences not including conditional instructions into instruction sequences including conditional instructions wherein the conditional instructions include both a condition and an operation code for execution by the processor when the condition is satisfied. An obtaining unit receives an instruction sequence that does not include a conditional instruction whereby an instruction sequence detection unit detects a conversion target instruction sequence which transfers different transfer objects to the same storage resource when a predetermined condition is satisfied. A judging unit judges whether the instruction set of a specialized processor is assigned a conditional instruction including the same condition as the precondition whereby a conversion unit can then convert the conversion target instruction sequence into the instruction sequence including a conditional instruction with the predetermined condition.

Abstract: A processor includes a constant register 36 for storing a constant, a format decoder 21 for decoding a format code located in the P0.0 field of an instruction stored in the instruction register 10, and a constant register control unit 32 which, when the format decoder 21 has decoded that the instruction includes a constant to be stored in the constant register 36, shifts the presently stored value in the constant register 36 and stores the constant into the constant register 36.

Abstract: A processor for executing operations based on instructions includes an operation constant register 361, a branching constant register 362, a decoding unit 20 for decoding an instruction stored in an instruction register 10, a constant register control unit 32, and an execution unit 30. When the decoding unit 20 finds that the instruction includes a constant to be stored in the branching constant register 362, the constant register control unit 32 shifts a present value in the branching constant register 362 and inserts the constant to be stored, thereby storing a new constant in the branching constant register 362. When the decoding unit 20 finds that a constant is to be stored in the operation constant register 361, the constant register control unit 32 shifts the present value in the operation constant register 361 and inserts the constant to be stored, thereby storing a new constant in the operation constant register 361.

Abstract: A processor for decoding and executing an instruction includes: an instruction register 10 for storing an instruction; a format decoder 21 for decoding a format code located in the P0.0 field 11 of the instruction stored in the instruction register 10; a constant storage unit including a storage region; a constant register control unit 32 which, when the format decoder 21 has referred to the format code and decoded that an operation field includes a constant to be stored in the constant register 36, transfers the constant from the instruction register 10 to the constant storage unit 36; and a constant register output unit 41 which, when the format decoder 21 has referred to the format code and decoded that an operation field includes an operation code showing an operation that should be executed and a piece of an operand that should be used for the operation, links the constant stored in the constant register 36 with the piece of the operand.

Abstract: A processor detects a function which includes no function call instruction and no update of the return address /calculation register from an assembler program. After the detection, the processor outputs a special return address to the end of the function detected, and executes the assembler program. The processor stores a return address not only on the stack but in the return address/calculation register. When the special return instruction has been fetched, the return address is moved from the return address/calculation register without accessing to the stack.

Abstract: A first instruction requiring that a data word should be read out from a data memory and be stored in a certain register in a register set, and then a second instruction requiring that two operands, respectively read out from the register and another register in the register set, should be added are pipeline-processed. In a high-speed mode in which an operation clock having a higher frequency is supplied, a data cache intervened between an instruction execution circuit and the data memory is controlled to supply a data word to a WB (write back) stage of the instruction execution circuit within two cycles with respect to an input address associated with the first instruction. In order to execute the second instruction, the data word is supplied from the WB stage to an EX (operation execution) stage of the instruction execution circuit.