Abstract: The present invention provides a solid-state image pickup apparatus which is able to easily discharge signal charges in a signal accumulating section and which is free from reduction in the dynamic range of the element, thermal noise in a dark state, an image-lag and so forth even if the pixel size of the MOS solid-state image pickup apparatus is reduced, the voltage of a reading gate is lowered and the concentration in the well is raised. The solid-state image pickup apparatus according to the present invention incorporates a p-type silicon substrate having a surface on which a p+ diffusion layer for constituting a photoelectric conversion region and a drain of a reading MOS field effect transistor are formed. A signal accumulating section formed by an n-type diffusion layer is formed below the p+ diffusion layer. A gate electrode of the MOS field effect transistor is, on the surface of the substrate, formed between the p+ diffusion layer and the drain.

Abstract: Forming a back-illuminated type CMOS image sensor, includes process for formation of a registration mark on the wiring side of a silicon substrate during formation of an active region or a gate electrode. A silicide film using an active region may also be used for the registration mark. Thereafter, the registration mark is read from the back side by use of red light or near infrared rays, and registration of the stepper is accomplished. It is also possible to form a registration mark in a silicon oxide film on the back side (illuminated side) in registry with the registration mark on the wiring side, and to achieve the desired registration by use of the registration mark thus formed.

Abstract: A photodiode and a FD portion are arranged in parallel with a transfer gate portion interposed therebetween, and a transfer electrode is arranged above the transfer gate portion. The transfer electrode has a body portion and an expanded portion and is expanded in the gate lengthwise direction. Where the partial expanded portion is provided on the transfer electrode in this manner, the modulation degree of the transfer electrode can be increased while the amount of reduction of the area of a light reception portion of the photodiode is reduced (the numerical aperture is increased). As a result, a solid-state image pickup device with which transfer residual is less likely to occur and which is suitable for complete transfer can be configured.

Abstract: P type semiconductor well regions 8 and 9 for device separation are provided in an upper and lower two layer structure in conformity with the position of a high sensitivity type photodiode PD, and the first P type semiconductor well region 8 at the upper layer is provided in the state of being closer to the pixel side than an end portion of a LOCOS layer 1A, for limiting a dark current generated at the end portion of the LOCOS layer 1A. In addition, the second P type semiconductor well region 9 at the lower layer is formed in a narrow region receding from the photodiode PD, so that the depletion layer of the photodiode PD is prevented from being obstructed, and the depletion is secured in a sufficiently broad region, whereby enhancement of the sensitivity of the photodiode PD can be achieved.

Abstract: In an analog front end (FE) IC chip having a CDS (Correlated Double Sampling) function and an AGC (Automatic Gain Control) function, a clamp circuit for clamping an output signal during a black reference signal period is equipped with a mechanism for suppressing the effect of noises contaminated from a power source, external circuits, etc.

Abstract: A solid-state imaging device with a variable (continuous) electronic shutter function comprises an imaging area where unit cells with photodiodes acting as pixels are arranged two-dimensionally, read lines for driving the read transistors in each pixel row, vertical selection lines for driving the vertical selection transistors in each pixel row, a vertical driving circuit for selectively driving vertical selection lines, vertical signal lines for outputting the signal from each unit cell in the pixel rows driven sequentially, and a row selection circuit for controlling the vertical driving circuit in such a manner that the vertical driving circuit drives the read transistors in each pixel row with the desired signal storage timing and signal read timing twice in that order and thereby drives the vertical selection transistors in the pixel row in synchronization with the signal read timing.

Abstract: A digital signal processing apparatus for processing a plurality of video signals and a plurality of audio signals is provided, and comprises a computer comprising a system bus and a main CPU connected to the system bus and an extension processor comprising a plurality of signal processing circuits for processing the plurality of video signals and/or the plurality of audio signals, and a local CPU for controlling the plurality of signal processing circuits so as to allow for the processing of the video signals and audio signals in real time. The extension processor further comprises an extension system bus extended from the system bus, a digital audio video (DAV) bus for transmitting the plurality of video signals and the plurality of audio signals between the plurality of signal processing circuits and a local CPU bus for transmitting control signals outputted from the local CPU.

Abstract: An MOS-type solid-state imaging apparatus includes an imaging region formed by two-dimensionally arranging unit cells serving as photoelectric conversion portions on a semiconductor substrate, a plurality of vertical address lines arranged in a row direction of the imaging region to select a row of unit cells to be addressed, a plurality of vertical signal lines arranged in a column direction of the imaging region to read out signals from the unit cells in each column, a plurality of load transistors each connected to one end of each of the vertical signal lines, and a plurality of horizontal selection transistors each connected to the other end of each of the vertical signal lines.

Abstract: An image system uses an amplification-type MOS sensor for receiving an optical image through a photoelectric conversion element, converting the image into an electrical signal, and outputting the signal. This system includes an optical system for guiding this optical image to a predetermined position, an image processing means having a sensor for photoelectrically converting the optical image guided to the predetermined position by the optical system into an electrical signal in units of pixels, and a signal process device for processing an output from the image processing means, and outputting the resultant data.

Abstract: An MOS-type solid-state imaging apparatus includes unit cells arranged in a two-dimensional matrix, each unit cell being constituted by a photodiode, an amplification transistor having a gate to which an output from the photodiode is input, a vertical selection transistor connected in series with the amplification transistor, and a reset transistor connected between the drain and gate of the amplification transistor to discharge the signal from the photodiode, a plurality of vertical address lines connected to the gates of the vertical selection transistors and arranged in a row direction, a vertical address circuit for driving the vertical address lines, a plurality of vertical signal lines arranged in a column direction in which currents are read out from the amplification transistors, a plurality of load transistors each connected to one end of a corresponding one of the vertical signal lines, a plurality of horizontal selection transistors each connected to the other end of a corresponding one of the vert

Abstract: An MOS-type solid-state imaging apparatus includes an imaging region formed by two-dimensionally arranging unit cells serving as photoelectric conversion portions on a semiconductor substrate, a plurality of vertical address lines arranged in a row direction of the imaging region to select a row of unit cells to be addressed, a plurality of vertical signal lines arranged in a column direction of the imaging region to read out signals from the unit cells in each column, a plurality of load transistors each connected to one end of each of the vertical signal lines, and a plurality of horizontal selection transistors each connected to the other end of each of the vertical signal lines.

Abstract: A solid-state imaging device includes unit cells, arranged in a matrix of rows and columns, each having a photodiode for photoelectrically converting incident light to store signal charges, a readout transistor Td for reading out the signal charges and amplifying transistor Tb for amplifying signals readout at a detection node, a plurality of vertical shift registers for generating signal charge readout pulses ESi, DRi, ROi and a voltage switching circuit for setting a voltage VDR of the readout pulse DRi for dynamic range control lower than voltages of both a readout pulse ESi for an electronic shutter and a usual readout pulse ROi. The solid-state imaging device provides excellent images without clipping from a small signal region to large signal region.

Abstract: An MOS-type solid-state imaging apparatus includes an imaging region formed by two-dimensionally arranging unit cells serving as photoelectric conversion portions on a semiconductor substrate, a plurality of vertical address lines arranged in a row direction of the imaging region to select a row of unit cells to be addressed, a plurality of vertical signal lines arranged in a column direction of the imaging region to read out signals from the unit cells in each column, a plurality of load transistors each connected to one end of each of the vertical signal lines, and a plurality of horizontal selection transistors each connected to the other end of each of the vertical signal lines.

Abstract: A MOS-type solid-state image sensor has a plurality of pixel units arranged on a p-type Si substrate in a matrix format. Each pixel unit has a photoelectric conversion portion including a photodiode, and a signal extraction portion including an amplification MOS transistor. Each element isolation region for isolating the pixel units from each other has a field oxide film formed on the substrate and a p-type diffusion layer formed in the substrate layer immediately below the oxide film to have a higher carrier impurity concentration than the substrate layer. The bottom portion of each element isolation region is positioned deeper than the bottom portion of a depletion layer extending from the p-n junction of the photodiode to the substrate in an equilibrium state.

Abstract: In an MOS-type solid-state imaging apparatus, plural unit cells are arranged in a two-dimensional matrix, unit cells in one horizontal line (row) are selected by a vertical address circuit, and vertical signal lines to which outputs from the unit cells in one vertical line (column) are supplied are selected by a horizontal address circuit, thereby sequentially outputting signals from the respective unit cells. Each unit cell includes an output circuit for outputting an output from a photodiode to a vertical signal line, photodiodes connected in parallel to the output circuit, and a selection switch for selecting one of the photodiodes and connecting it to the output circuit. The output circuit comprising an amplification transistor for amplifying an output from the photodiode, a selection transistor for selecting the unit cell, and a reset transistor for resetting the charge in the photodiode.

Abstract: An amplifying solid-state image pickup device comprises an image pickup region formed by two-dimensionally arranging photosensitive cells, each of the photosensitive cells including photoelectric conversion means, signal charge storage means, signal charge ejection means, row select means, and amplification means on a semiconductor substrate, a plurality of vertical select lines arranged in the image pickup region in a row direction, vertical select means for driving the plurality of vertical select lines, a plurality of vertical signal lines arranged in the column direction to read the outputs of the amplification means, noise suppression means provided at the ends of the plurality of vertical signal lines to capture and deduct noises and signals appearing on the plurality of vertical signal lines at time differences, horizontal select lines arranged in a column direction, horizontal read means for relaying the outputs of the horizontal select lines and the noise suppression means, horizontal select means fo

Abstract: A brittle-material machining method and apparatus achieves grinding in a ductile mode region using an ordinary grinding apparatus. Grinding or polishing of a workpiece consisting of a brittle material is performed by relative movement between the workpiece and a grinding wheel, which includes innumerable abrasive grains provided on a support base, while the grinding wheel is brought into pressured contact with the workpiece at a prescribed pressure. The grinding or polishing is carried out upon setting the prescribed pressure in such a manner that depth of cut d, into the workpiece, of abrasive grains among the innumerable number thereof that participate in the grinding or polishing is made less than a critical depth of cut d.sub.c, which is a minimum depth of cut at which brittle fracture is produced in the workpiece.

Abstract: A CCD imager has an array of rows and columns of picture elements on a semiconductor substrate. A vertical charge transfer gate section extends in a first direction on the substrate to be associated with the columns. The transfer gate section includes CCD channels in the substrate, and insulated transfer gate electrodes overlying these CCD channels. A plurality of buffer electrodes are formed at a first level over the substrate surface to overlie the transfer gate electrodes. A plurality of shunt wires are formed at a second level over the substrate surface to overlie the buffer electrodes. The charge transfer gate electrodes and the buffer electrodes are connected with each other by first contact holes. The buffer electrodes and the shunt wires are coupled together by second contact holes.

Abstract: A charge-transfer device contains a high-resistance p-well layer formed in the surface of an n-type semiconductor substrate. In the surface of the well layer, a charge-transfer n-channel layer, a charge storage n-channel layer, a charge release n-channel layer, and a charge release n-type drain are formed continuously. An output gate electrode is provided above the junction of the transfer channel layer and the storage channel layer, with an insulating film interposed therebetween. Provided above the release channel layer is a reset gate electrode with an insulating film interposed therebetween. In the surface of the storage channel layer, a charge-sensing p-channel layer of a charge-sensing transistor is formed. The charge-sensing channel layer is arranged so as to be in contact with neither the transfer channel layer nor the release channel layer.

Abstract: A dynamic random access memory, which comprises a substrate, a dynamic memory cell located on the substrate, a pair of bit lines to read out data from the cell and/or write data to the cell, a plurality of word lines, connected to the bit lines, to select a desired memory cell, a differential sense amplifier having an output line, the differential sense amplifier amplifying data from the pair of bit lines and transferring the amplified data to the output lines; means for precharging a first bit line of the pair of bit lines to a reference voltage and a second bit line of the pair of bit lines to a second voltage exceeding the reference voltage by the amount of an input offset voltage of the sense amplifier.