Patents by Inventor Nobuo Owada
Nobuo Owada has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20030003733Abstract: In a semiconductor integrated circuit wherein an interlayer insulating film is formed over a semiconductor substrate having a semiconductor device formed thereover; and an interconnection embedded in an interconnection groove in the interlayer insulating film is formed by the deposition of a metal film such as copper and polishing by the CMP method, another interlayer insulating film over the interconnection and interlayer insulating film is formed to have a blocking film, a planarizing film and an insulating film. As the planarizing film, a film having fluidity such as SOG is employed.Type: ApplicationFiled: May 8, 2002Publication date: January 2, 2003Inventors: Naofumi Ohashi, Hizuru Yamaguchi, Junji Noguchi, Nobuo Owada
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Publication number: 20030001183Abstract: After formation of Cu interconnections 46a to 46e each to be embedded in an interconnection groove 40 of a silicon oxide film 39 by CMP and then washing, the surface of each of the silicon oxide film 39 and Cu interconnections 46a to 46e is treated with a reducing plasma (ammonia plasma). Then, without vacuum break, a cap film (silicon nitride film) is formed continuously. This process makes it possible to improve the dielectric breakdown resistance (reliability) of a copper interconnection formed by the damascene method.Type: ApplicationFiled: September 4, 2002Publication date: January 2, 2003Applicant: Hitachi, Ltd.Inventors: Junji Noguchi, Naofumi Ohashi, Kenichi Takeda, Tatsuyuki Saito, Hizuru Yamaguchi, Nobuo Owada
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Publication number: 20020192967Abstract: In order to provide an anticorrosive technique for metal wirings formed by a chemical mechanical polishing (CMP) method, a process for manufacturing a semiconductor integrated circuit device according to the invention comprises the steps of: forming a metal layer of Cu (or a Cu alloy containing Cu as a main component) over the major face of a wafer and then planarizing the metal layer by a chemical mechanical polishing (CMP) method to form metal wirings; anticorroding the planarized major face of the wafer to form a hydrophobic protective film over the surfaces of the metal wirings; immersing the anticorroded major face of the wafer or keeping the same in a wet state so that it may not become dry; and post-cleaning the major face, kept in the wet state, of the wafer.Type: ApplicationFiled: August 19, 2002Publication date: December 19, 2002Inventors: Naofumi Ohashi, Junji Noguchi, Toshinori Imai, Hizuru Yamaguchi, Nobuo Owada, Kenji Hinode, Yoshio Homma, Seiichi Kondo
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Publication number: 20020142576Abstract: After formation of Cu interconnections 46a to 46e each to be embedded in an interconnection groove 40 of a silicon oxide film 39 by CMP and then washing, the surface of each of the silicon oxide film 39 and Cu interconnections 46a to 46e is treated with a reducing plasma (ammonia plasma). Then, without vacuum break, a cap film (silicon nitride film) is formed continuously. This process makes it possible to improve the dielectric breakdown resistance (reliability) of a copper interconnection formed by the damascene method.Type: ApplicationFiled: May 8, 2002Publication date: October 3, 2002Applicant: Hitachi, Ltd.Inventors: Junji Noguchi, Naofumi Ohashi, Kenichi Takeda, Tatsuyuki Saito, Hizuru Yamaguchi, Nobuo Owada
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Patent number: 6458674Abstract: In order to provide an anticorrosive technique for metal wirings formed by a chemical mechanical polishing (CMP) method, a process for manufacturing a semiconductor integrated circuit device according to the invention comprises the steps of: forming a metal layer of Cu (or a Cu alloy containing Cu as a main component) over the major face of a wafer and then planarizing the metal layer by a chemical mechanical polishing (CMP) method to form metal wirings; anticorroding the planarized major face of the wafer to form a hydrophobic protective film over the resurfaces of the metal wirings; immersing the anticorroded major face of the wafer or keeping the same in a wet state so that it may not become dry; and post-cleaning the major face, kept in the wet state, of the wafer.Type: GrantFiled: January 18, 2002Date of Patent: October 1, 2002Assignee: Hitachi, Ltd.Inventors: Naofumi Ohashi, Junji Noguchi, Toshinori Imai, Hizuru Yamaguchi, Nobuo Owada, Kenji Hinode, Yoshio Homma, Seiichi Kondo
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Publication number: 20020127842Abstract: After formation of Cu interconnections 46a to 46e each to be embedded in an interconnection groove 40 of a silicon oxide film 39 by CMP and then washing, the surface of each of the silicon oxide film 39 and Cu interconnections 46a to 46e is treated with a reducing plasma (ammonia plasma). Then, without vacuum break, a cap film (silicon nitride film) is formed continuously. This process makes it possible to improve the dielectric breakdown resistance (reliability) of a copper interconnection formed by the damascene method.Type: ApplicationFiled: May 8, 2002Publication date: September 12, 2002Applicant: Hitachi, Ltd.Inventors: Junji Noguchi, Naofumi Ohashi, Kenichi Takeda, Tatsuyuki Saito, Hizuru Yamaguchi, Nobuo Owada
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Publication number: 20020127843Abstract: After formation of Cu interconnections 46a to 46e each to be embedded in an interconnection groove 40 of a silicon oxide film 39 by CMP and then washing, the surface of each of the silicon oxide film 39 and Cu interconnections 46a to 46e is treated with a reducing plasma (ammonia plasma). Then, without vacuum break, a cap film (silicon nitride film) is formed continuously. This process makes it possible to improve the dielectric breakdown resistance (reliability) of a copper interconnection formed by the damascene method.Type: ApplicationFiled: May 8, 2002Publication date: September 12, 2002Applicant: Hitachi, LtdInventors: Junji Noguchi, Naofumi Ohashi, Kenichi Takeda, Tatsuyuki Saito, Hizuru Yamaguchii, Nobuo Owada
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Publication number: 20020119651Abstract: After formation of Cu interconnections 46a to 46e each to be embedded in an interconnection groove 40 of a silicon oxide film 39 by CMP and then washing, the surface of each of the silicon oxide film 39 and Cu interconnections 46a to 46e is treated with a reducing plasma (ammonia plasma). Then, without vacuum break, a cap film (silicon nitride film) is formed continuously. This process makes it possible to improve the dielectric breakdown resistance (reliability) of a copper interconnection formed by the damascene method.Type: ApplicationFiled: April 24, 2002Publication date: August 29, 2002Applicant: Hitachi, Ltd.Inventors: Junji Noguchi, Naofumi Ohashi, Kenichi Takeda, Tatsuyuki Saito, Hizuru Yamaguchii, Nobuo Owada
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Publication number: 20020113271Abstract: A semiconductor device comprises a semiconductor substrate; a first insulating film overlying a surface of the semiconductor substrate, an upper surface of the first insulating film being nitrided; a first copper-embedded interconnection embedded in the first insulating film, and which first copper-embedded interconnection contains copper as a main component; a copper nitride film overlying an upper surface of the first copper-embedded interconnection; a cap insulating film overlying an upper surface of the first insulating film and an upper surface of the copper nitride film; and a second insulting film overlying the cap insulating film.Type: ApplicationFiled: April 24, 2002Publication date: August 22, 2002Applicant: Hitachi, Ltd.Inventors: Junji Noguchi, Naofumi Ohashi, Kenichi Takeda, Tatsuyuki Saito, Hizuru Yamaguchii, Nobuo Owada
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Patent number: 6403459Abstract: In a semiconductor integrated circuit wherein an interlayer insulating film is formed over a semiconductor substrate having a semiconductor device formed thereover; and an interconnection embedded in an interconnection groove in the interlayer insulating film is formed by the deposition of a metal film such as copper and polishing by the CMP method, another interlayer insulating film over the interconnection and interlayer insulating film is formed to have a blocking film, a planarizing film and an insulating film. As the planarizing film, a film having fluidity such as SOG is employed.Type: GrantFiled: September 26, 2000Date of Patent: June 11, 2002Assignee: Hitachi, Ltd.Inventors: Naofumi Ohashi, Hizuru Yamaguchi, Junji Noguchi, Nobuo Owada
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Publication number: 20020058363Abstract: In order to provide an anticorrosive technique for metal wirings formed by a chemical mechanical polishing (CMP) method, a process for manufacturing a semiconductor integrated circuit device according to the invention comprises the steps of: forming a metal layer of Cu (or a Cu alloy containing Cu as a main component) over the major face of a wafer and then planarizing the metal layer by a chemical mechanical polishing (CMP) method to form metal wirings; anticorroding the planarized major face of the wafer to form a hydrophobic protective film over the surfaces of the metal wirings; immersing the anticorroded major face of the wafer or keeping the same in a wet state so that it may not become dry; and post-cleaning the major face, kept in the wet state, of the wafer.Type: ApplicationFiled: January 18, 2002Publication date: May 16, 2002Inventors: Naofumi Ohashi, Junji Noguchi, Toshinori Imai, Hizuru Yamaguchi, Nobuo Owada, Kenji Hinode, Yoshio Homma, Seiichi Kondo
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Patent number: 6376345Abstract: In order to provide an anticorrosive technique for metal wirings formed by a chemical mechanical polishing (CMP) method, a process for manufacturing a semiconductor integrated circuit device according to the invention comprises the steps of: forming a metal layer of Cu (or a Cu alloy containing Cu as a main component) over the major face of a wafer and then planarizing the metal layer by a chemical mechanical polishing (CMP) method to form metal wirings; anticorroding the planarized major face of the wafer to form a hydrophobic protective film over the surfaces of the metal wirings; immersing the anticorroded major face of the wafer or keeping the same in a wet state so that it may not become dry; and post-cleaning the major face, kept in the wet state, of the wafer.Type: GrantFiled: July 20, 1999Date of Patent: April 23, 2002Assignee: Hitachi Ltd.Inventors: Naofumi Ohashi, Junji Noguchi, Toshinori Imai, Hizuru Yamaguchi, Nobuo Owada, Kenji Hinode, Yoshio Homma, Seiichi Kondo
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Publication number: 20020025605Abstract: In order to suppress an increase of depressions, etc. to occur on a copper based alloy layer during polishing when a copper based alloy inlaid wiring is formed with the damascene method in grooves formed in an insulating film, the polishing rate for the lower metallic layer is set not less than five times faster than the etching rate for the same and the polishing rate for the insulating film is set lower than the polishing rate for the lower metallic layer when the upper metallic layer 13 to become a wiring and the lower metallic layer 12 to become a barrier are polished respectively. Thus, the object damascene wiring can be formed with less erosion on each of insulating layers and dishing on each of metallic layers respectively.Type: ApplicationFiled: October 17, 2001Publication date: February 28, 2002Applicant: Hitachi, Ltd.Inventors: Yoshio Homma, Seiichi Kondo, Noriyuki Sakuma, Naofumi Ohashi, Toshinori Imai, Hizuru Yamaguchi, Nobuo Owada
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Publication number: 20020017669Abstract: Herein disclosed is a semiconductor integrated circuit device fabricating process for forming MISFETs over the principal surface in those active regions of a substrate, which are surrounded by inactive regions formed of an element separating insulating film and channel stopper regions, comprising: the step of for forming a first mask by a non-oxidizable mask and an etching mask sequentially over the principal surface of the active regions of the substrate; the step of forming a second mask on and in self-alignment with the side walls of the first mask by a non-oxidizable mask thinner than the non-oxidizable mask of the first mask and an etching mask respectively; the step of etching the principal surface of the inactive regions of the substrate by using the first mask and the second mask; the step of forming the element separating insulating film over the principal surface of the inactive regions of the substrate by an oxidization using the first mask and the second mask; and the step of forming the channel sType: ApplicationFiled: July 9, 2001Publication date: February 14, 2002Inventors: Jun Sugiura, Osamu Tsuchiya, Makoto Ogasawara, Fumio Ootsuka, Kazuyoshi Torii, Isamu Asano, Nobuo Owada, Mitsuaki Horiuchi, Tsuyoshi Tamaru, Hideo Aoki, Nobuhiro Otsuka, Seiichirou Shirai, Masakazu Sagawa, Yoshihiro Ikeda, Masatoshi Tsuneoka, Toru Kaga, Tomotsugu Shimmyo, Hidetsugu Ogishi, Osamu Kasahara, Hiromichi Enami, Atsushi Wakahara, Hiroyuki Akimori, Sinichi Suzuki, Keisuke Funatsu, Yoshinao Kawasaki, Tunehiko Tubone, Takayoshi Kogano, Ken Tsugane
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Patent number: 6342412Abstract: Herein disclosed is a semiconductor integrated circuit device fabricating process for forming MISFETs over the principal surface in those active regions of a substrate, which are surrounded by inactive regions formed of an element separating insulating film and channel stopper regions, comprising: the step of for forming a first mask by a non-oxidizable mask and an etching mask sequentially over the principal surface of the active regions of the substrate; the step of forming a second mask on and in self-alignment with the side walls of the first mask by a non-oxidizable mask thinner than the non-oxidizable mask of the first mask and an etching mask respectively; the step of etching the principal surface of the inactive regions of the substrate by using the first mask and the second mask; the step of forming the element separating insulating film over the principal surface of the inactive regions of the substrate by an oxidization using the first mask and the second mask; and the step of forming the channel sType: GrantFiled: December 14, 1999Date of Patent: January 29, 2002Assignees: Hitachi, Ltd., Hitachi VLSI Engineering Corp.Inventors: Jun Sugiura, Osamu Tsuchiya, Makoto Ogasawara, Fumio Ootsuka, Kazuyoshi Torii, Isamu Asano, Nobuo Owada, Mitsuaki Horiuchi, Tsuyoshi Tamaru, Hideo Aoki, Nobuhiro Otsuka, Seiichirou Shirai, Masakazu Sagawa, Yoshihiro Ikeda, Masatoshi Tsuneoka, Toru Kaga, Tomotsugu Shimmyo, Hidetsugu Ogishi, Osamu Kasahara, Hiromichi Enami, Atsushi Wakahara, Hiroyuki Akimori, Sinichi Suzuki, Keisuke Funatsu, Yoshinao Kawasaki, Tunehiko Tubone, Takayoshi Kogano, Ken Tsugane
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Patent number: 6326299Abstract: In order to suppress an increase of depressions, etc. to occur on a copper based alloy layer during polishing when a copper based alloy inlaid wiring is formed with the damascene method in grooves formed in an insulating film, the polishing rate for the lower metallic layer is set not less than five times faster than the etching rate for the same and the polishing rate for the insulating film is set lower than the polishing rate for the lower metallic layer when the upper metallic layer 13 to become a wiring and the lower metallic layer 12 to become a barrier are polished respectively. Thus, the object damascene wiring can be formed with less erosion on each of insulating layers and dishing on each of metallic layers respectively.Type: GrantFiled: July 28, 1999Date of Patent: December 4, 2001Assignee: Hitachi, Ltd.Inventors: Yoshio Homma, Seiichi Kondo, Noriyuki Sakuma, Naofumi Ohashi, Toshinori Imai, Hizuru Yamaguchi, Nobuo Owada
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Patent number: 6184143Abstract: In a semiconductor integrated circuit wherein an interlayer insulating film is formed over a semiconductor substrate having a semiconductor device formed thereover; and an interconnection embedded in an interconnection groove in the interlayer insulating film is formed by the deposition of a metal film such as copper and polishing by the CMP method, another interlayer insulating film over the interconnection and interlayer insulating film is formed to have a blocking film, a planarizing film and an insulating film. As the planarizing film, a film having fluidity such as SOG is employed.Type: GrantFiled: July 28, 1998Date of Patent: February 6, 2001Assignee: Hitachi, Ltd.Inventors: Naofumi Ohashi, Hizuru Yamaguchi, Junji Noguchi, Nobuo Owada
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Patent number: 6169324Abstract: Herein disclosed is a semiconductor integrated circuit device fabricating process for forming MISFETs over the principal surface in those active regions of a substrate, which are surrounded by inactive regions formed of an element separating insulating film and channel stopper regions, comprising: the step of for forming a first mask by a non-oxidizable mask and an etching mask sequentially over the principal surface of the active regions of the substrate; the step of forming a second mask on and in self-alignment with the side walls of the first mask by a non-oxidizable mask thinner than the non-oxidizable mask of the first mask and an etching mask respectively; the step of etching the principal surface of the inactive regions of the substrate by using the first mask and the second mask; the step of forming the element separating insulating film over the principal surface of the inactive regions of the substrate by an oxidization using the first mask and the second mask; and the step of forming the channel sType: GrantFiled: October 6, 1999Date of Patent: January 2, 2001Assignees: Hitachi, Ltd., Hitachi VLSI Engineering Corp.Inventors: Jun Sugiura, Osamu Tsuchiya, Makoto Ogasawara, Fumio Ootsuka, Kazuyoshi Torii, Isamu Asano, Nobuo Owada, Mitsuaki Horiuchi, Tsuyoshi Tamaru, Hideo Aoki, Nobuhiro Otsuka, Seiichirou Shirai, Masakazu Sagawa, Yoshihiro Ikeda, Masatoshi Tsuneoka, Toru Kaga, Tomotsugu Shimmyo, Hidetsugu Ogishi, Osamu Kasahara, Hiromichi Enami, Atsushi Wakahara, Hiroyuki Akimori, Sinichi Suzuki, Keisuke Funatsu, Yoshinao Kawasaki, Tunehiko Tubone, Takayoshi Kogano, Ken Tsugane
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Patent number: 6127255Abstract: Herein disclosed is a semiconductor integrated circuit device fabricating process for forming MISFETs over the principal surface in active regions of a substrate, which are surrounded by inactive regions formed of an element separating insulating film and channel stopper regions. The disclosed process includes forming insulating films over wiring lines including uppermost wiring lines, the uppermost wiring lines having gaps between adjacent uppermost wiring lines. The insulating films include forming a silicon oxide film over the wiring lines and in the gaps between adjacent uppermost wiring lines, and forming a silicon nitride film over the silicon oxide film, the silicon nitride film being formed by plasma chemical vapor deposition. The silicon oxide film is formed to have a thickness of at least one-half of the gap between adjacent uppermost wiring lines, with the silicon nitride film being thicker than the silicon oxide film.Type: GrantFiled: October 3, 1997Date of Patent: October 3, 2000Assignees: Hitachi, Ltd., Hitachi VLSI Engineering Corp.Inventors: Jun Sugiura, Osamu Tsuchiya, Makoto Ogasawara, Fumio Ootsuka, Kazuyoshi Torii, Isamu Asano, Nobuo Owada, Mitsuaki Horiuchi, Tsuyoshi Tamaru, Hideo Aoki, Nobuhiro Otsuka, Seiichirou Shirai, Masakazu Sagawa, Yoshihiro Ikeda, Masatoshi Tsuneoka, Toru Kaga, Tomotsugu Shimmyo, Hidetsugu Ogishi, Osamu Kasahara, Hiromichi Enami, Atsushi Wakahara, Hiroyuki Akimori, Sinichi Suzuki, Keisuke Funatsu, Yoshinao Kawasaki, Tunehiko Tubone, Takayoshi Kogano, Ken Tsugane
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Patent number: 5811316Abstract: Herein disclosed is a semiconductor integrated circuit device fabricating process for forming MISFETs over the principal surface in those active regions of a substrate, which are surrounded by inactive regions formed of an element separating insulating film and channel stopper regions, comprising: the step of for forming a first mask by a non-oxidizable mask and an etching mask sequentially over the principal surface of the active regions of the substrate; the step of forming a second mask on and in self-alignment with the side walls of the first mask by a non-oxidizable mask thinner than the non-oxidizable mask of the first mask and an etching mask respectively; the step of etching the principal surface of the inactive regions of the substrate by using the first mask and the second mask; the step of forming the element separating insulating film over the principal surface of the inactive regions of the substrate by an oxidization using the first mask and the second mask; and the step of forming the channel sType: GrantFiled: June 5, 1995Date of Patent: September 22, 1998Assignees: Hitachi. Ltd., Hitachi VLSI Engineering CorporationInventors: Jun Sugiura, Osamu Tsuchiya, Makoto Ogasawara, Fumio Ootsuka, Kazuyoshi Torii, Isamu Asano, Nobuo Owada, Mitsuaki Horiuchi, Tsuyoshi Tamaru, Hideo Aoki, Nobuhiro Otsuka, Seiichirou Shirai, Masakazu Sagawa, Yoshihiro Ikeda, Masatoshi Tsuneoka, Toru Kaga, Tomotsugu Shimmyo, Hidetsugu Ogishi, Osamu Kasahara, Hiromichi Enami, Atsushi Wakahara, Hiroyuki Akimori, Sinichi Suzuki, Keisuke Funatsu, Yoshinao Kawasaki, Tunehiko Tubone, Takayoshi Kogano, Ken Tsugane