Abstract: Herein disclosed is a semiconductor integrated circuit device fabricating process for forming MISFETs over the principal surface in those active regions of a substrate, which are surrounded by inactive regions formed of an element separating insulating film and channel stopper regions, comprising: the step of for forming a first mask by a non-oxidizable mask and an etching mask sequentially over the principal surface of the active regions of the substrate; the step of forming a second mask on and in self-alignment with the side walls of the first mask by a non-oxidizable mask thinner than the non-oxidizable mask of the first mask and an etching mask respectively; the step of etching the principal surface of the inactive regions of the substrate by using the first mask and the second mask; the step of forming the element separating insulating film over the principal surface of the inactive regions of the substrate by an oxidization using the first mask and the second mask; and the step of forming the channel s

Abstract: Herein disclosed is a semiconductor integrated circuit device fabricating process for forming MISFETs over the principal surface in those active regions of a substrate, which are surrounded by inactive regions formed of an element separating insulating film and channel stopper regions, comprising: the step of for forming a first mask by a non-oxidizable mask and an etching mask sequentially over the principal surface of the active regions of the substrate; the step of forming a second mask on and in self-alignment with the side walls of the first mask by a non-oxidizable mask thinner than the non-oxidizable mask of the first mask and an etching mask respectively; the step of etching the principal surface of the inactive regions of the substrate by using the first mask and the second mask; the step of forming the element separating insulating film over the principal surface of the inactive regions of the substrate by an oxidization using the first mask and the second mask; and the step of forming the channel s

Abstract: In a method of fabricating a semiconductor device having a MISFET and/or bipolar transistor and/or a resistor formed with different surface portions of a single silicon semiconductor substrate in which a silicide layer is formed on each of source/drain regions of the MISFET and/or collector contact region and extrinsic base region of the bipolar transistor and/or contact regions of the resistor, the bipolar transistor has its emitter region formed by diffusing an impurity contained in doped polysilicon film serving as an emitter electrode of the bipolar transistor into a part of its base region. The resistor may have a resistive region formed in a surface portion of the substrate and may be covered with an insulating film and a doped polysilicon film thereon or may have a doped polysilicon film formed over a surface portion of the substrate as a resistor element.

Abstract: Herein disclosed is a semiconductor integrated circuit device fabricating process for forming MISFETs over the principal surface in those active regions of a substrate, which are surrounded by inactive regions formed of an element separating insulating film and channel stopper regions, comprising: the step of for forming a first mask by a non-oxidizable mask and an etching mask sequentially over the principal surface of the active regions of the substrate; the step of forming a second mask on and in self-alignment with the side walls of the first mask by a non-oxidizable mask thinner than the non-oxidizable mask of the first mask and an etching mask respectively; the step of etching the principal surface of the inactive regions of the substrate by using the first mask and the second mask; the step of forming the element separating insulating film over the principal surface of the inactive regions of the substrate by an oxidization using the first mask and the second mask; and the step of forming the channel s

Abstract: Herein disclosed is a semiconductor integrated circuit device fabricating process for forming MISFETs over the principal surface in those active regions of a substrate, which are surrounded by inactive regions formed of an element separating insulating film and channel stopper regions, comprising: the step of for forming a first mask by a non-oxidizable mask and an etching mask sequentially over the principal surface of the active regions of the substrate; the step of forming a second mask on and in self-alignment with the side walls of the first mask by a non-oxidizable mask thinner than the non-oxidizable mask of the first mask and an etching mask respectively; the step of etching the principal surface of the inactive regions of the substrate by using the first mask and the second mask; the step of forming the element separating insulating film over the principal surface of the inactive regions of the substrate by an oxidization using the first mask and the second mask; and the step of forming the channel s

Abstract: The present invention relates to an ion implantation process in a wafer process for a semiconductor integrated circuit device. Particularly, according to the present invention, a shallow junction can be formed by performing the implantation of ion while holding a wafer to be processed at a low temperature.

Abstract: Herein disclosed is an improved bipolar transistor manufacturing method which adopts an EBT (Epitaxial Base Transistor) structure using an SPESG (Selective Poly-and-Epitaxial-Silicon Growth) technique. Specifically, the method of manufacturing a bipolar transistor according to the present invention comprises the steps of: forming an isolation oxide layer to enclose an active region of a single crystal semiconductor substrate and to have a lower surface than that of the substrate of said active region; simultaneously forming a single crystal silicon layer over the substrate surface of said active region and a polycrystal silicon layer to become integral with said single crystal silicon layer over the surface of said isolation oxide layer by simultaneously growing silicon films over the substrate surface of said active region and the surface of said isolation oxide layer; and forming an active region of a semiconductor element in said single crystal silicon layer.

Abstract: The heat transfer path (the heat radiating portion) from a position very near the semiconductor device as the heat source to the surface of the semiconductor apparatus is made of a material having a large heat conductivity thereby to more rapidly transfer the heat generated in the p-n junction to the surface of the semiconductor apparatus or the outside. This arrangement can cope with that the calorific power is increased as the integration is increased. The formation of the good heat conductive material from the surface of the apparatus to the heat source through the multilayer structure film can be attained by means of the CVD technique.

Abstract: A method of manufacturing a bipolar transistor having a base lead-out electrode provided so as to surround an emitter region to be formed on a main surface of a semiconductor substrate and also having an emitter lead-out electrode provided along a stepped shape of the base lead-out electrode and connected to said emitter region is characterized by forming a first silicon film selectively only in an area surrounded by the base lead-out electrode. Impurity is introduced into the first silicon film and then diffused into the main surface of the semiconductor substrate to form the emitter region. Finally, a second silicon film is formed on the first silicon film to serve as the emitter lead-out electrode.

Abstract: A multi-layered structure of wirings on a semiconductor substrate has been employed in conjunction with the increase in the integration density of semiconductor integrated circuit devices. In the invention, dummy patterns made of the same material as an Al wiring layer for compensating for any step or level gradation are disposed in the regions below bump electrodes and in the proximity thereof in order to reduce any defects inherent to a multi-layered structure that occur in CCB bump electrodes formed on the multi-layered wirings and at pads as the base layer of the former.

Abstract: Herein disclosed is a semiconductor integrated circuit device fabricating process for forming MISFETs over the principal surface in those active regions of a substrate, which are surrounded by inactive regions formed of an element separating insulating film and channel stopper regions, comprising: the step of for forming a first mask by a non-oxidizable mask and an etching mask sequentially over the principal surface of the active regions of the substrate; the step of forming a second mask on and in self-alignment with the side walls of the first mask by a non-oxidizable mask thinner than the non-oxidizable mask of the first mask and an etching mask respectively; the step of etching the principal surface of the inactive regions of the substrate by using the first mask and the second mask; the step of forming the element separating insulating film over the principal surface of the inactive regions of the substrate by an oxidization using the first mask and the second mask; and the step of forming the channel s

Abstract: A method of manufacturing a bipolar transistor having a base lead-out electrode provided so as to surround an emitter region to be formed on a main surface of a semiconductor substrate and also having an emitter lead-out electrode provided along a stepped shape of the base lead-out electrode and connected to said emitter region is characterized by forming a first silicon film selectively only in an area surrounded by the base lead-out electrode. Impurity is introduced into the first silicon film and then diffused into the main surface of the semiconductor substrate to form the emitter region. Finally, a second silicon film is formed on the first silicon film to serve as the emitter lead-out electrode.

Abstract: A semiconductor integrated circuit device having at least one bipolar transistor comprises a semiconductor substrate of monocrystalline silicon having a main surface; an isolation oxide layer selectively formed on the main surface so as to surround an active region of the main surface; a first silicon layer formed on the active region and extending on the isolation oxide layer and a second silicon layer stacked on the first silicon layer, wherein a collector region of a bipolar transistor is formed on the active region of the first silicon layer, the intrinsic base region is formed on the active region of the second silicon layer, and a base-lead out region which is electrically connected with the intrinsic base region is formed of the first and second silicon layers over the isolation oxide layer.

Abstract: On a semiconductor film to function as a lead-out electrode of a semiconductor element, a metal silicide film and a metal nitride film are successively provided, whereby alloying and inferior contact resistances attributed to heat during wiring with aluminum can be effectively suppressed, so that the reliability of a semiconductor device can be enhanced.

Abstract: Disclosed is a semiconductor integrated circuit device adopting a gate array scheme, having a plurality of layers of wiring formed by a Design Automation system. The device according to the present invention includes a semiconductor substrate having basic cell forming regions, the basic cell forming regions being spaced from each other with wiring channel regions between adjacent basic cell forming regions. The wiring includes at least first-layer wiring lines arranged overlying the wiring channel regions; second-layer wiring lines overlying both the basic cell forming regions and the wiring channel regions; and third-layer wiring lines overlying both the basic cell forming regions and the wiring channel regions. The first-, second- and third-layer wiring lines respectively extend in first, second and third directions, the second direction being different from the first direction.

Abstract: A multi-layered structure of wirings on a semiconductor substrate has been employed in conjuction with the increase in the integration density of semiconductor integrated circuit devices. In the invention, dummy patterns made of the same material as an Al wiring layer for compensating for any step or level gradation are disposed in the regions below bump electrodes and in the proximity thereof in order to reduce any defects inherent to a multi-layered structure that occur in CCB bump electrodes formed on the multi-layered wirings and at pads as the base layer of the former.