Patents by Inventor Nobutaka Nakamura

Nobutaka Nakamura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6146012
    Abstract: The DSC (DTA) signal waveform measured under an experimental heating rate condition is separated into a base line and individual basic peak elements, and the respective activation energies are calculated corresponding to each of basic peak elements separated. A DSC (DTA) signal that should be obtained at an another heating rate is estimated from the data obtained from the experimental heating rate and it is outputted. In this process, the temperature shift caused by heating rate difference is corrected using the values of activation energies obtained.
    Type: Grant
    Filed: January 15, 1999
    Date of Patent: November 14, 2000
    Assignee: Seiko Instruments Inc.
    Inventors: Nobutaka Nakamura, Rintaro Nakatani, Ryoichi Kinoshita
  • Patent number: 6016548
    Abstract: A computer system capable of entering a sleep mode is disclosed. The rate at which the computer switches between a normal state and a stop grant state while in the sleep mode is controllable by a timer. The stop grant state is an intermediate power consumption state between the sleep mode and the normal state. The timer may include a software system management interrupt timer. The system may also include processing to determine the cause of the switch from the stop grant state to the normal state.
    Type: Grant
    Filed: July 15, 1997
    Date of Patent: January 18, 2000
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Nobutaka Nakamura, Masayo Yamaki
  • Patent number: 5937206
    Abstract: A DS-PCI/ISA bridge device for controlling I/O devices on an external PCI bus and an external ISA bus has the two operation states of proceed and freeze. When the DS-PCI/ISA bridge device receives a serial GNT# from a DMAC core, the operation state is switched from proceed to freeze. In the freeze state, a serial REQ# cycle is only executed when a change has occurred in the state of a DMA request of the I/O device which the DACK# has notified. Execution of serial REQ# cycles for reporting state changes in DMA requests relating to other I/O devices is frozen. Further, the DMAC core is notified whether or not an initiated serial transfer cycle is a cycle for notifying that the DMA request from an I/O device for which notification of DMA cycle execution has been given is inactive, according to the length of the inactive time period of a serial REQ# from the I/O devices.
    Type: Grant
    Filed: August 9, 1996
    Date of Patent: August 10, 1999
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Nobutaka Nakamura
  • Patent number: 5901292
    Abstract: An analog switch is provided to be connected to the signal lines of a bus of a computer body to be led to an expansion unit. When the signal lines of the bus of the expansion unit are pulled up, a high value is sent to the signal lines of the bus of the computer body. When the signal lines of the bus of the expansion unit are pulled down, a low value is sent to the signal lines of the bus of the computer body. After the potential levels of the signal lines of one bus equal to those of the signal lines of the other bus by the high value or the low value sent, a connection control gate array sets the analog switch on. This can allow the signal lines of both buses to be connected together without causing a transient phenomenon even while the bus cycle is being executed.
    Type: Grant
    Filed: February 28, 1997
    Date of Patent: May 4, 1999
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Nobutaka Nishigaki, Nobutaka Nakamura
  • Patent number: 5892977
    Abstract: A computer system has an I/O address space with an ISA bus, and a configuration address space with a PCI bus, further the system including an ISA DMA (Direct Memory Access) controller with two or more DMA channels on the ISA bus, an I/O register implemented in the DMA controller for storing information for DMA transfer on each of the DMA channels, and a register control logic device for controlling read/write-access to the I/O register. The I/O registers are allocated to the I/O address space, and further write-only registers in the I/O registers are allocated to the configuration address space. When a HOST-PCI bridge device generates a configuration read cycle through the configuration address space on the PCI bus, the register control logic device read-accesses the write-only registers, in response to the generated configuration read cycle.
    Type: Grant
    Filed: August 9, 1996
    Date of Patent: April 6, 1999
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Nobutaka Nakamura
  • Patent number: 5850529
    Abstract: A computer system for detecting a resource lock state on a PCI bus includes a DMA controller that transmits a bus access request signal from an I/O expansion device through a bridge device to a bus arbiter, and receives a granted bus access enable signal from the bus arbiter. The computer system further has a circuit for determining whether the PCI bus is in a resource lock state by using a lock signal at a granted bus access enable signal, and a circuit for prohibiting the DMA controller from executing a transaction for DMA transfer, when the PCI bus is in a resource lock state.
    Type: Grant
    Filed: August 9, 1996
    Date of Patent: December 15, 1998
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Nobutaka Nakamura
  • Patent number: 5826983
    Abstract: A thermomechanical analyzer capable of performing, in addition to thermomechanical measurement, thermogravimetry of a sample of several grams or more only by switching parts of the analyzer. A thermomechanical analyzer has a heating furnace, a temperature detector for detecting temperature of the sample that is placed within the heating furnace, an attachable/detachable detecting rod and a sample holding member, wherein the sample is held between the detecting rod and the sample holding member. A load applying instrument applies an external force to the sample via the detecting rod. A displacement detector detects displacement of the detecting rod relative to the sample holding member. The thermomechanical analyzer is provided with a control computing apparatus for adjusting an output from the load applying instrument to bring an output from the displacement detector closer to a fixed value.
    Type: Grant
    Filed: July 10, 1996
    Date of Patent: October 27, 1998
    Assignee: Seiko Instruments Inc.
    Inventors: Nobutaka Nakamura, Yoshiharu Sugano
  • Patent number: 5742849
    Abstract: A computer system including a high speed CPU, a low speed main memory, and a system controller which has a write buffer coupled to the processor data bus in parallel to the main memory for latching CPU write data. The system controller includes a gate array LSI, and an address buffer which is coupled to the CPU through a processor address bus and to the main memory through a memory address bus. When the write buffer latches the write data from the CPU, the system controller suspends the transfer of the write data to the main memory before completion of the memory write cycle. The memory write cycle is completed by transferring the latched data in the write buffer to the main memory before the CPU begins the next read/write cycle.
    Type: Grant
    Filed: February 7, 1997
    Date of Patent: April 21, 1998
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Nobutaka Nakamura
  • Patent number: 5734914
    Abstract: There is provided a computer system including a system memory operable with a first voltage level, a processor operable with a second voltage level different from the first voltage level, and capable of accessing the system memory to perform burst read, a data bus connected to the processor, and a level shifter connected between the system memory and the data bus for shifting the voltage level of a data signal supplied from the system memory and transferring the level-shifted data signal to the data bus, the level shifter including a latch circuit for sequentially latching, at predetermined interval, a plurality of n-bit data which constitute the level-shifted data signal, to thereby minimize the interval between each adjacent pair of the n-bit data.
    Type: Grant
    Filed: March 1, 1996
    Date of Patent: March 31, 1998
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Nobutaka Nakamura, Koichi Senuma
  • Patent number: 5711604
    Abstract: A method for measuring the coefficient of thermal conductivity of a solid sample material by: heating a meltable calibration sample having good thermal conductivity to its melting temperature by raising the temperature of an analyzer at a controlled rate and causing heat to flow through a path having a thermal resistance to the calibration sample, the heating being performed one time with the solid sample material interposed in the path so that heat flows through the path and through the solid sample material, and one time with the solid sample material removed so that heat flows only through the path; deriving thermal analysis curves each representing a relation between heat flow to the calibration sample and the controlled rate at which the analyzer temperature is raised, during melting of the calibration sample in respective performances of the heating step; and determining the coefficient of thermal conductivity of the solid sample material based on the solid sample material thickness and a characteristic
    Type: Grant
    Filed: November 3, 1995
    Date of Patent: January 27, 1998
    Assignee: Seiko Instruments Inc.
    Inventor: Nobutaka Nakamura
  • Patent number: 5706407
    Abstract: A global standby System Management Interrupt ("SMI) is supplied to a CPU when all hardware interrupt requests (except a timer interrupt) are not generated for four seconds. The SMI routine sets the CPU to a stop grant state whereby the CPU goes to a sleep mode. Thus, the same sleep mode function is provided regardless of the operating system environment. Memory banks are reallocated in the DRAM logical address space in memory-size order such that a smaller address range is allocated to a bank with a larger memory size. For any address range allocated to any DRAM bank, there is a sequence of bits having a common value associated with all the memory address values belonging to the address range. Each sequence of bits is used as a decoding condition for the associated address strobe line. The memory address space of the CPU is separated into a plurality of memory address areas.
    Type: Grant
    Filed: December 27, 1994
    Date of Patent: January 6, 1998
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Nobutaka Nakamura, Koichi Senuma
  • Patent number: 5669554
    Abstract: The humidity of the atmosphere contacting a sample and the water vapor partial pressure are program controlled and measured in a device having: a sample chamber which is provided with an inlet and an outlet for water vapor and which is capable of controlling a feedback temperature along with the sample stored therein; a warm water chamber for generating saturated water vapor pressure which has a gas inlet and an outlet connected to a pipe and which is capable of controlling the feedback temperature; a humidity program function generator for outputting a target humidity value for the sample chamber for each input time interval; a memory for storing a temperature-saturated water vapor pressure curve; and a calculator for calculating a control target temperature for the warm water chamber for generating the saturated water vapor pressure on the basis of the sample chamber target temperature output from a temperature program function generator, sample chamber target humidity of the sample chamber output from the
    Type: Grant
    Filed: November 21, 1995
    Date of Patent: September 23, 1997
    Assignee: Seiko Instruments, Inc.
    Inventors: Nobutaka Nakamura, Ryoichi Kinoshita
  • Patent number: 5599104
    Abstract: The temperature of a heat reservoir is varied according to a linear function which is AC modulated. At this time, the temperature difference between two points located in a heat flow path going from the heat reservoir to an unknown sample is measured. Also, the temperature difference between two points located in a heat flow path going from the heat reservoir to a reference sample is measured. These two pairs of points are arranged symmetrically. Then, the resulting signals are demodulated, and each signal is divided into an AC component and a low-frequency component. Using these signals, the DSC signal is separated into a heat capacity component and a latent heat component.
    Type: Grant
    Filed: September 23, 1994
    Date of Patent: February 4, 1997
    Assignee: Seiko Instruments Inc.
    Inventors: Nobutaka Nakamura, Yoshihiko Teramoto
  • Patent number: 5588746
    Abstract: In order to carry out thermal analysis under various kinds of atmospheres, there is provided an apparatus for thermal analysis containing a sample chamber having a portion for a sample and a signal detection chamber provided with a signal detection member, the signal detection chamber having an inlet port for a purging gas, the sample chamber and the signal detection chamber being connected through a purging gas passage, and the sample chamber being provided with an inlet port for an atmosphere gas and also with an outlet port for the atmosphere gas and the purging gas.
    Type: Grant
    Filed: July 19, 1994
    Date of Patent: December 31, 1996
    Assignees: Sumitomo Chemical Company, Limited, Seiko Instruments, Inc.
    Inventors: Masao Minobe, Noboru Shiraga, Nobutaka Nakamura
  • Patent number: 5546567
    Abstract: A computer system includes a program executing section for executing a program, an instruction generating section for generating a frequency change instruction in response to the execution of the program, and a changing section for changing the frequency of an operation clock of a system bus in reponse to the frequency change instruction. The frequency of the operation clock of the system bus is changed when an interface having a low operation rate is accessed. Therefore, an average speed of the system can remain high.
    Type: Grant
    Filed: May 13, 1994
    Date of Patent: August 13, 1996
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Nobutaka Nakamura
  • Patent number: 5515080
    Abstract: An apparatus that saves power consumption by reading out display data from a memory and writing data to a display device such that the read operation is set in a sleep state when a same screen display content continues for a predetermined period of time.
    Type: Grant
    Filed: August 19, 1993
    Date of Patent: May 7, 1996
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Nobutaka Nakamura, Hiroki Zenda
  • Patent number: 5452614
    Abstract: Phase delay, amplitude and the like of sinusoidal strain (stress) are detected with high precision, and also adverse influences caused by expansion, shrinkage, stress relaxation, and creep of a sample are removed by a simple correction term by way of a mathematical method, utilizing Fourier transformation processing. A digital-to-analog converter is used for converting a signal of a detector for detecting sample strain, or displacement of the sample, a memory is connected for storing a digital output signal from the analog-to-digital converter, and a calculator is used for performing a Fourier transformation calculation on the signal values stored in the memory. Complex elastic modulus M* and loss tangent tan .delta. corresponding to the basic physical amount in dynamic viscoelasticity can be obtained with high precision by processing a response signal derived from the sample by Fourier transformation processing. Also, the measuring range of the elastic modulus can be expanded.
    Type: Grant
    Filed: October 13, 1993
    Date of Patent: September 26, 1995
    Assignee: Seiko Instruments Inc.
    Inventors: Hidetaka Kato, Nobutaka Nakamura
  • Patent number: 5440121
    Abstract: A scanning probe microscope uses a conductive material as a probe of AFM. The probe scans a sample while the probe is forcibly oscillated by applying alternating current voltage from an oscillator between the probe and the sample. Signals .omega. and 2.omega. from the probe are extracted with an analog processor using a discrete Fourier transformation, so that distribution of surface potential of the sample is obtained using the signals .omega. and 2.omega..
    Type: Grant
    Filed: December 28, 1993
    Date of Patent: August 8, 1995
    Assignee: Seiko Instruments Inc.
    Inventors: Masatoshi Yasutake, Nobutaka Nakamura
  • Patent number: 5434589
    Abstract: An electronic apparatus having a TFT LCD includes a detector for detecting whether or not display data in a video RAM is rewritten. When the rewrite operation of display data is detected, a display controller reads out display data from the video RAM, and supplies the readout display data to the TFT LCD. When data on a memory plane for storing display data, which is being displayed on the TFT LCD, is rewritten, the display controller reads out display data from the video RAM, and supplies the readout display data to the TFT LCD. When display data to be written in the Video RAM is the same as the already stored display data, the display controller does not supply the display data from the video RAM to the TFT LCD.
    Type: Grant
    Filed: February 1, 1994
    Date of Patent: July 18, 1995
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Nobutaka Nakamura, Hiroki Zenda
  • Patent number: 5389884
    Abstract: In order to measure a complex dielectric constant, a sample 8 enveloped by a ring 9 and two laminas 10 is inserted between parallel plate electrodes constituted by an exciting electrode 2 and a response electrode 3. Measuring data is obtained as a measuring value of the sample 8 itself because an operational circuit 21 removes parasitic effects of the ring 9 and the lamina 10. Dielectric characteristics of a fluid sample can be obtained readily and accurately without contaminating the electrodes.
    Type: Grant
    Filed: May 7, 1993
    Date of Patent: February 14, 1995
    Assignee: Seiko Instruments Inc.
    Inventors: Nobutaka Nakamura, Masafumi Take, Nobuo Iizuka