Patents by Inventor Nobutaka Nakamura

Nobutaka Nakamura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5306087
    Abstract: Apparatus for conducting thermogravimetric analysis continuously when sample weights are measured automatically in the case of measurement of a plurality of samples. A plurality of empty sample containers are transferred individually in succession from a tray to a thermobalance, where each container is weighed and a representation of the weight of each empty container is stored in a first memory. Then, a sample is loaded into each container in the tray and the loaded sample containers are transferred individually in succession from the tray to the thermobalance where each loaded container is weighed and a representation of the weight of each container is stored in a second memory. The weight of each sample is then determined based on the difference between the representations stored in the first and second memories.
    Type: Grant
    Filed: August 25, 1992
    Date of Patent: April 26, 1994
    Assignee: Seiko Instruments Inc.
    Inventors: Nobutaka Nakamura, Haruo Takeda, Yoshiharu Sugano
  • Patent number: 5287749
    Abstract: A thermomechanical analyzer for efficiently measuring the dynamic viscoelasticity of a sample piece. The analyzer is provided with a function generator, a stress applier, a strain detector, an analog-to-digital converter, a memory and a Fourier transform processor. The function generator generates a sine wave signal to induce a sine wave stress-strain response in the sample piece. This response is Fourier-transformed by the processor to calculate the dynamic viscoelasticity of the sample piece.
    Type: Grant
    Filed: October 11, 1991
    Date of Patent: February 22, 1994
    Assignee: Seiko Instruments, Inc.
    Inventor: Nobutaka Nakamura
  • Patent number: 5280589
    Abstract: A memory access control system is disclosed. In this system, a CPU, a low speed memory, a high speed memory and direct memory access controller (DMAC) are connected to a system bus. A high speed memory is connected through a local bus to the CPU. A control circuit is connected to the local bus, the system bus and the high speed memory. A bidirectional buffer is connected to the local and system buses. When the CPU accesses the high speed memory, the control circuit addresses the high speed memory and disables the buffer. As a result, data can directly be transferred between the CPU and the high speed memory. When the CPU accesses the low speed memory, the control circuit drives the system bus according to a protocol of the system bus, thereby to address the low speed memory and enables the buffer. As a result, data can be transferred between the CPU and the low speed memory, via a route of the local bus, the buffer and the system bus.
    Type: Grant
    Filed: April 22, 1991
    Date of Patent: January 18, 1994
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Nobutaka Nakamura
  • Patent number: 5163135
    Abstract: In a computer system, a CPU bus cycle control section receives a bus cycle request (BC-REQ) to generate a system bus cycle request (SBC-REQ) and feeds back a ready notice (READY-a) to the CPU. A system bus cycle control section performs the bus cycle control in response to the system bus cycle request (SBC-REQ) from the control section and generates a ready notice (READY-b) to the CPU bus cycle control section. The computer system includes a timer for delaying the ready notice (READY-b), a selector for selecting one of the ready notice (D'READY) delayed by the timer and the ready notice (READy-b) from the system bus cycle control section and supplies the selected ready notice to the CPU bus cycle control section and a register for holding access control information including a recovery state bit FRDY and recovery time data (RDY3-RDY0) of the timer.
    Type: Grant
    Filed: April 7, 1992
    Date of Patent: November 10, 1992
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Nobutaka Nakamura
  • Patent number: 5013159
    Abstract: Apparatus for controlling the temperature of a sample in a thermal analysis system according to a temperature-control program in order to facilitate the production of rising and falling temperatures. The apparatus includes a first heater, a thermally insulating container having an opening and containing a mass of liquified coolant, a coolant vapor flow pipe, a sample chamber for containing the sample, a second heater, a sample chamber temperature detector, a temperature-control program setting circuit, a first power supply regulator and a second power supply regulator.
    Type: Grant
    Filed: October 12, 1989
    Date of Patent: May 7, 1991
    Assignee: Seiko Instruments, Inc.
    Inventors: Nobutaka Nakamura, Haruo Takeda, Masafumi Take
  • Patent number: 4984469
    Abstract: An apparatus for providing an indication of the amplitude of a length signal having a top peak, a bottom peak and an intrinsic offset and being indicative of viscoelasticity of a sample. A peak measurement circuit is provided for measuring values of top and bottom peaks of the length signal to determine the amplitude thereof and an offset circuit is connected for providing a compensative offset. An adder circuit is provided for adding the compensative offset to the length signal. An offset calculation circuit receptive of the values of the top and bottom peaks from the peak measurement circuit is provided for outputting to the offset circuit, according to the received values, a control signal effective to control the offset circuit to provide an update compensative offset effective to cancel the intrinsic offset of the length signal.
    Type: Grant
    Filed: November 16, 1989
    Date of Patent: January 15, 1991
    Assignee: Seiko Instruments, Inc.
    Inventors: Masafumi Take, Haruo Takeda, Nobutaka Nakamura
  • Patent number: 4943910
    Abstract: A plurality of memory blocks, which includes a plurality of memory areas, each having a page number. Each of the memory blocks has a set number. A page controlling register stores mapping information and a page number of the memory areas. A mapping register stores mapping information including set information that indicates the set number of a memory block in which data supplied from a CPU is stored. A memory controller accesses the memory section in accordance with the mapping information.
    Type: Grant
    Filed: April 14, 1988
    Date of Patent: July 24, 1990
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Nobutaka Nakamura
  • Patent number: 4725833
    Abstract: In a tone control device in a monochromatic tone display apparatus, when an intensity signal and at least one of the R, G and B signals is active, an AND gate generates a maximum tone level signal. A selector/adder having OR gates and resistors receives the maximum tone level signal and the R, G and B signals. When the maximum tone level signal is inactive, the selector/adder generates a tone level signal in response to the active state of the R, G and B signals. When the maximum tone level signal is active and all the R, G and B signals are inactive, the selector/adder generates a minimum tone level voltage. However, when the maximum tone level signal and at least one of the R, G and B signals is active, the selector/adder generates a maximum tone level voltage.
    Type: Grant
    Filed: October 1, 1985
    Date of Patent: February 16, 1988
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Nobutaka Nakamura
  • Patent number: 4724493
    Abstract: A floppy disk drive interface circuit of the invention has a counter/selector for counting the pulse width of a window signal supplied from a voltage frequency oscillator. When a window pulse having a pulse width longer or shorter than a preset pulse width is input, counter/selector supplies a disable signal to AND gate 22. AND gate 22blocks window signal 12 from VFO2 being supplied to FDC 3.
    Type: Grant
    Filed: July 11, 1986
    Date of Patent: February 9, 1988
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Nobutaka Nakamura
  • Patent number: 4166166
    Abstract: Phenolic novolak resins are produced from acetophenone, particularly by-product acetophenone obtained from the cumene process for manufacturing phenol, by the process of (1) reacting acetophenone with an aldehyde under alkaline conditions, and (2) reacting the product of step (1) with a phenol under acidic conditions. Phenolic resole resins are produced by reacting the product of step (2) with an aldehyde under alkaline conditions. The acetophenone modified phenolic resins are useful as a molding material, a felting or batting binder, a grinding stone binder, a foundry sand binder and an adhesive for timbers.
    Type: Grant
    Filed: October 2, 1978
    Date of Patent: August 28, 1979
    Assignee: Sumitomo Durez Company, Ltd.
    Inventors: Nobutaka Nakamura, Yukio Saeki
  • Patent number: 4125502
    Abstract: Adhesive compositions comprising a mixture of polyvinyl acetate and an alcohol soluble resol phenolic resin and about 2 to 20 parts by weight of lower polyhydric alcohol per 100 parts by weight of the resin solids have enhanced binding strengths on curing even after a prolonged open assembly time.
    Type: Grant
    Filed: December 29, 1975
    Date of Patent: November 14, 1978
    Assignee: Sumitomo Durez Company, Ltd.
    Inventors: Nobutaka Nakamura, Yukio Saeki
  • Patent number: 4109057
    Abstract: A method for accelerated curing of phenolic resin adhesives comprises adding powdered green tea to a thermosetting phenolic resin at about ambient temperature.
    Type: Grant
    Filed: May 23, 1977
    Date of Patent: August 22, 1978
    Assignee: Sumitomo Durez Company, Ltd.
    Inventors: Nobutaka Nakamura, Yukio Saeki, Shigeru Nemoto
  • Patent number: 4104698
    Abstract: A ceramic capacitor is provided having a flame retardant electrical insulation coating characterized by blending 10 - 15 percent by weight of an uniformly melt-blendable non-heat-reactive type synthetic resin, with melting points between 70.degree. and 150.degree. C. into a flame-retardant wax, which contains a halogenated flame retardent.
    Type: Grant
    Filed: February 7, 1977
    Date of Patent: August 1, 1978
    Assignee: Sumitomo Durez Company, Ltd.
    Inventors: Takao Murata, Nobutaka Nakamura, Tateo Goto
  • Patent number: 4032490
    Abstract: Wax compositions for flame retardant electrical insulation coating characterized by blending 10 - 15 percent by weight of an uniformly melt-blendable non-heat-reactive type synthetic resin, with melting points between 70.degree. and 150.degree. C. into a flame-retardant wax, which contains a halogenated flame retardant.
    Type: Grant
    Filed: October 10, 1975
    Date of Patent: June 28, 1977
    Assignee: Sumitomo Durez Company, Ltd.
    Inventors: Takao Murata, Nobutaka Nakamura, Tateo Goto
  • Patent number: 4031276
    Abstract: Improved preparation of densified wood reinforced with a resole phenolic resin is accomplished by impregnating wood with a solution of the resin in the presence of about 0.6 to 4 parts of methanol, acetone, or mixture thereof per part by weight of the solids content of the resin under a pressure of about 10-50 Kgs/cm.sup.2 and thereafter drying and curing the resin-impregnated wood. The resultant product has an enhanced content of cured resin and greater bending strength than densified wood prepared by conventional resin impregnating techniques.
    Type: Grant
    Filed: July 21, 1975
    Date of Patent: June 21, 1977
    Assignee: Sumitomo Durez Company, Ltd.
    Inventors: Nobutaka Nakamura, Yukio Saeki
  • Patent number: 4006081
    Abstract: A method for preventing the gelation of thermosetting resin glues or varnishes in waste wash water characterized by mixing urea in to the waste water which principally contains resorcinol resin obtained by reacting resorcinol with formaldehyde or phenol modified resorcinol resin obtained by reacting phenol, resorcinol and formaldehyde.
    Type: Grant
    Filed: December 31, 1974
    Date of Patent: February 1, 1977
    Assignee: Sumitomo Durez Company, Ltd.
    Inventors: Nobutaka Nakamura, Yukio Saeki