Patents by Inventor Nobutoshi Fujii

Nobutoshi Fujii has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12150322
    Abstract: An imaging device according to an embodiment of the present disclosure includes: a first semiconductor substrate (100) provided with pixels including a photoelectric conversion element (PD) and floating diffusion (FD) that temporarily holds a charge output from the photoelectric conversion element (PD); and a semiconductor layer (200Y) provided on the first semiconductor substrate (100) via an insulating film (123), the semiconductor layer (200Y) including a readout circuit unit (539) that reads out the charge held in the floating diffusion (FD) and outputs a pixel signal, in which the semiconductor layer (200Y) is formed of an organic semiconductor material.
    Type: Grant
    Filed: June 17, 2020
    Date of Patent: November 19, 2024
    Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventors: Kenya Nishio, Suguru Saito, Nobutoshi Fujii, Hirotaka Yoshioka
  • Patent number: 12136640
    Abstract: There is provided a solid-state imaging device including: a first semiconductor layer including a photoelectric converter and an electric charge accumulation section for each pixel, the electric charge accumulation section in which a signal electric charge generated in the photoelectric converter is accumulated; a pixel separation section that is provided in the first semiconductor layer, and partitions a plurality of the pixels from each other; a second semiconductor layer that is provided with a pixel transistor and is stacked on the first semiconductor layer, the pixel transistor that reads the signal electric charge of the electric charge accumulation section; and a first shared coupling section that is provided between the second semiconductor layer and the first semiconductor layer, and is provided to straddle the pixel separation section and is electrically coupled to a plurality of the electric charge accumulation sections.
    Type: Grant
    Filed: June 26, 2020
    Date of Patent: November 5, 2024
    Assignee: Sony Semiconductor Solutions Corporation
    Inventors: Keiichi Nakazawa, Koichiro Zaitsu, Nobutoshi Fujii, Yohei Hiura, Shigetaka Mori, Shintaro Okamoto, Keiji Ohshima, Shuji Manda, Junpei Yamamoto, Yui Yuga, Shinichi Miyake, Tomoki Kambe, Ryo Ogata, Tatsuki Miyaji, Shinji Nakagawa, Hirofumi Yamashita, Yasushi Hamamoto, Naohiko Kimizuka
  • Publication number: 20240290813
    Abstract: An optical detection device including a through electrode is provided. The optical detection device includes a first semiconductor layer having a photoelectric conversion region, a first surface, and a second surface that is a light entrance surface, a second semiconductor layer with a third surface and a fourth surface, a second wiring layer overlapped with the third surface, a third wiring layer overlapped with the fourth surface, a first wiring layer with one surface overlapped with the first surface and another surface overlapped with one of the second wiring layer and the third wiring layer, a first conductor that has a first width, includes a first material, and penetrates the second semiconductor layer in a thickness direction, and a second conductor that has a second width smaller than the first width, includes a second material different from the first material, and penetrates the second semiconductor layer in the thickness direction.
    Type: Application
    Filed: June 16, 2022
    Publication date: August 29, 2024
    Applicant: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventors: Masaki HANEDA, Kengo KOTOO, Yoshiki SHIRASU, Kazuki SHIMOMURA, Nobutoshi FUJII, Takaaki HIRANO, Yosuke FUJII, Takashi OINOUE, Suguru SAITO, Toshiyuki ISHIMARU, Keiji OHSHIMA, Shinichi IMAI, Takuya KUROTORI, Tomohiro SUGIYAMA, Ikue MITSUHASHI, Kenichi TOKUOKA
  • Publication number: 20240222410
    Abstract: The present disclosure relates to a solid-state imaging apparatus, a manufacturing method thereof, and electronic equipment that are able to suppress nonuniform reflection of incident light. The solid-state imaging apparatus includes an imaging element chip and a device chip. The imaging element chip has a semiconductor substrate. The device chip is bonded to a wiring layer opposite the light incident surface of the semiconductor substrate. The device chip is disposed in a pixel region of the imaging element chip. The wiring layer of the imaging element chip includes a dummy metal wiring in a region where the device chip of the pixel region is not disposed. The technology according to the present disclosure is applicable, for example, to the solid-state imaging apparatus that is formed by bonding the imaging element chip to the device chip.
    Type: Application
    Filed: February 2, 2022
    Publication date: July 4, 2024
    Inventors: HIROKI OOMORI, NOBUTOSHI FUJII
  • Patent number: 11990366
    Abstract: Provided are a semiconductor device in which an air gap structure can be formed in any desired region regardless of the layout of metallic wiring lines, a method for manufacturing the semiconductor device, and an electronic apparatus. A first wiring layer and a second wiring layer including a metallic film are stacked via a diffusion preventing film that prevents diffusion of the metallic film. The diffusion preventing film is formed by burying a second film in a large number of holes formed in a first film. At least the first wiring layer includes the metallic film, an air gap, and a protective film formed with the second film on the inner peripheral surface of the air gap, and the opening width of the air gap is equal to the opening width of the holes formed in the first film or is greater than the opening width of the holes.
    Type: Grant
    Filed: February 1, 2022
    Date of Patent: May 21, 2024
    Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventors: Suguru Saito, Nobutoshi Fujii, Masaki Haneda, Kazunori Nagahata
  • Publication number: 20240162268
    Abstract: In an imaging element obtained by stacking a plurality of semiconductor substrates, connection between semiconductor substrates is facilitated. The imaging element includes a first semiconductor substrate, a second semiconductor substrate, an insulating layer, connection sections, and a recess. The first semiconductor substrate includes photoelectric conversion sections that perform photoelectric conversion of incident light. The second semiconductor substrate includes pixel circuits that generate an image signal corresponding to a charge generated by the photoelectric conversion, and the first semiconductor substrate is stacked on the back side of the second semiconductor substrate. The insulating layer is disposed between the first semiconductor substrate and the second semiconductor substrate. A connection section penetrates through the insulating layer and connects the first semiconductor substrate and the back side of the second semiconductor substrate.
    Type: Application
    Filed: February 28, 2022
    Publication date: May 16, 2024
    Inventors: YUTA NAKAMURA, NOBUTOSHI FUJII
  • Patent number: 11923279
    Abstract: A first semiconductor device includes: a first wiring layer including a first interlayer insulating film, a first electrode pad, and a first dummy electrode, the first electrode pad being embedded in the first interlayer insulating film and having one surface located on same plane as one surface of the first interlayer insulating film, and the first dummy electrode being embedded in the first interlayer insulating film, having one surface located on same plane as the one surface of the first interlayer insulating film, and being disposed around the first electrode pad; and a second wiring layer including a second interlayer insulating film, a second electrode pad, and a second dummy electrode, the second electrode pad being embedded in the second interlayer insulating film, having one surface located on same surface as one surface of the second interlayer insulating film, and being bonded to the first electrode pad, and the second dummy electrode having one surface located on same plane as the surface located
    Type: Grant
    Filed: December 7, 2022
    Date of Patent: March 5, 2024
    Assignee: SONY GROUP CORPORATION
    Inventors: Nobutoshi Fujii, Yoshihisa Kagawa
  • Publication number: 20240047503
    Abstract: Provided are a semiconductor device capable of lowering the temperature of the entire joining process to room temperature, a method for manufacturing a semiconductor device, and an electronic device. The semiconductor device includes: a first insulating film; a plurality of first joining electrodes formed on a surface of the first insulating film; a second insulating film; a plurality of second joining electrodes formed on a surface of the second insulating film; and a metal film covering an entire surface of a joining surface including the first insulating film and the plurality of first joining electrodes and an entire surface of a joining surface including the second insulating film and the plurality of second joining electrodes. The first insulating film includes a first dug portion that is formed between at least some joining electrodes of the plurality of first joining electrodes and separating the metal film between the joining electrodes.
    Type: Application
    Filed: October 29, 2021
    Publication date: February 8, 2024
    Inventors: SUGURU SAITO, NOBUTOSHI FUJII
  • Publication number: 20240006437
    Abstract: While improving the bonding strength between a plurality of semiconductor substrates, the passage of noise from one of the plurality of semiconductor substrates to another is suppressed.
    Type: Application
    Filed: November 8, 2021
    Publication date: January 4, 2024
    Inventors: YOSUKE NITTA, NOBUTOSHI FUJII, SUGURU SAITO
  • Publication number: 20240006448
    Abstract: Provided is an imaging device including: a first semiconductor substrate provided with a photoelectric conversion element, a second semiconductor substrate stacked on the first semiconductor substrate with an interlayer insulating film interposed therebetween and provided with a pixel circuit that reads out charges generated in the photoelectric conversion element as a pixel signal, and a via that penetrates the interlayer insulating film and electrically connects a first surface of the first semiconductor substrate facing the second semiconductor substrate and at least a part of a second surface of the second semiconductor substrate facing the first surface.
    Type: Application
    Filed: October 11, 2021
    Publication date: January 4, 2024
    Applicant: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventors: Takeya MOCHIZUKI, Keiichi NAKAZAWA, Shinichi YOSHIDA, Kenya NISHIO, Nobutoshi FUJII, Suguru SAITO, Masaki OKAMOTO, Ryosuke KAMATANI, Yuichi YAMAMOTO, Kazutaka IZUKASHI, Yuki MIYANAMI, Hirotaka YOSHIOKA, Hiroshi HORIKOSHI, Takuya KUROTORI, Shunsuke FURUSE, Takayoshi HONDA
  • Patent number: 11862662
    Abstract: Provided is an imaging device (1) including: an imaging element (10); and a semiconductor element (20, 30) provided to be opposed to the imaging element and electrically coupled to the imaging element. The semiconductor element includes: a wiring region (20A, 30A) provided in a middle portion and a peripheral region (20B, 30B) outside the wiring region; a wiring layer (22, 32) having a wiring line in the wiring region; a semiconductor substrate (21, 31) opposed to the imaging element with the wiring layer interposed therebetween and having a first surface (Sa, Sc) and a second surface (Sb, Sd) in order from a side of the wiring layer; and a polishing adjustment section (23, 33) including a material that is lower in polishing rate than a constituent material of the semiconductor substrate, the polishing adjustment section being disposed in at least a portion of the peripheral region and provided in a thickness direction of the semiconductor substrate from the second surface.
    Type: Grant
    Filed: October 9, 2019
    Date of Patent: January 2, 2024
    Assignee: Sony Semiconductor Solutions Corporation
    Inventors: Sotetsu Saito, Suguru Saito, Nobutoshi Fujii
  • Publication number: 20230361145
    Abstract: To provide a semiconductor device having a structure suitable for higher integration. This semiconductor device includes: a first semiconductor substrate; and a second semiconductor substrate. The first semiconductor substrate is provided with a first electrode including a first protruding portion and a first base portion. The first protruding portion includes a first abutting surface. The first base portion is linked to the first protruding portion and has volume greater than volume of the first protruding portion. The second semiconductor substrate is provided with a second electrode including a second protruding portion and a second base portion. The second protruding portion includes a second abutting surface that abuts the first abutting surface. The second base portion is linked to the second protruding portion and has volume greater than volume of the second protruding portion. The second semiconductor substrate is stacked on the first semiconductor substrate.
    Type: Application
    Filed: July 19, 2023
    Publication date: November 9, 2023
    Inventors: YOSHIYA HAGIMOTO, NOBUTOSHI FUJII
  • Patent number: 11769784
    Abstract: The present technology relates to an imaging device, an electronic apparatus, and a method of manufacturing an imaging device capable of thinning a semiconductor on a terminal extraction surface while maintaining a strength of a semiconductor chip. There is provided an imaging device including: a first substrate having a pixel region in which pixels are two-dimensionally arranged, the pixels performing photoelectric conversion of light; and a second substrate in which a through silicon via is formed, in which a dug portion is formed in a back surface of the second substrate opposite to an incident side of light of the second substrate, and a redistribution layer (RDL) connected to a back surface of the first substrate is formed in the dug portion. The present technology can be applied to, for example, a semiconductor package including a semiconductor chip.
    Type: Grant
    Filed: April 8, 2022
    Date of Patent: September 26, 2023
    Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventors: Suguru Saito, Nobutoshi Fujii
  • Publication number: 20230282661
    Abstract: A contact of a glass substrate with an on-chip lens is suppressed while suppressing occurrence of flare. A package includes a flattening film covering an on-chip lens formed on a light incidence side of a substrate having an element formed thereon, a transparent substrate formed on the light incidence side of the flattening film, a hollow portion formed in a region overlapping the on-chip lens when seen in a plan view with respect to at least one of between the flattening film and the transparent substrate and inside the transparent substrate, and a through-hole making the hollow portion communicate with the outside.
    Type: Application
    Filed: August 13, 2021
    Publication date: September 7, 2023
    Inventors: YOSUKE NITTA, NOBUTOSHI FUJII, SUGURU SAITO, YOICHI OOTSUKA
  • Patent number: 11742374
    Abstract: To provide a semiconductor device having a structure suitable for higher integration. This semiconductor device includes: a first semiconductor substrate; and a second semiconductor substrate. The first semiconductor substrate is provided with a first electrode including a first protruding portion and a first base portion. The first protruding portion includes a first abutting surface. The first base portion is linked to the first protruding portion and has volume greater than volume of the first protruding portion. The second semiconductor substrate is provided with a second electrode including a second protruding portion and a second base portion. The second protruding portion includes a second abutting surface that abuts the first abutting surface. The second base portion is linked to the second protruding portion and has volume greater than volume of the second protruding portion. The second semiconductor substrate is stacked on the first semiconductor substrate.
    Type: Grant
    Filed: September 17, 2019
    Date of Patent: August 29, 2023
    Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventors: Yoshiya Hagimoto, Nobutoshi Fujii
  • Publication number: 20230268369
    Abstract: Provided is a semiconductor device with a wiring layer including a plurality of wiring lines extending in a first direction; a first insulating film stacked on the wiring layer that has a gap region between the plurality of wiring lines adjacent to each other in a second direction; and a second insulating film between the plurality of wiring lines and the first insulating film. Each wiring line includes a metal film and a barrier metal layer. The metal film includes an electrically conductive material including a first metal. The barrier metal layer partially covers surroundings of the metal film in a cross section orthogonal to the first direction and includes a material including a second metal. The second metal prevents diffusion of the first metal. The second insulating film includes an insulating material and covers a portion of the metal film. The insulating material prevents diffusion of the first metal.
    Type: Application
    Filed: July 6, 2021
    Publication date: August 24, 2023
    Applicant: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventors: Koichi SEJIMA, Takashi FUKATANI, Kenya NISHIO, Masaki HANEDA, Nobutoshi FUJII, Suguru SAITO
  • Publication number: 20230261016
    Abstract: The present feature relates to a solid-state imaging device that allows generation of flare to be reduced and a manufacturing method therefor. A solid-state imaging device according to the present feature includes a semiconductor substrate having a pixel area having a plurality of pixels provided therein, and a transparent structure joined to a light incident surface side of the semiconductor substrate with resin and having a hollow structure. In the solid-state imaging device according to the present feature, the transparent structure includes a glass substrate and a transparent film, and the hollow structure is formed between the glass substrate and the transparent film. The present feature can be applied for example to imaging devices.
    Type: Application
    Filed: June 25, 2021
    Publication date: August 17, 2023
    Applicant: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventors: Nobutoshi FUJII, Suguru SAITO, Takashi FUKATANI
  • Patent number: 11626356
    Abstract: A first semiconductor device includes a first substrate including a first electrode and a second electrode at a first surface side of the first substrate opposite to a light incident surface side of the first substrate; and a second substrate including a photodiode, a transfer transistor, and a third electrode and a fourth electrode at a first surface side of the second substrate facing the first surface of the first substrate, and a plurality of transistors.
    Type: Grant
    Filed: February 18, 2022
    Date of Patent: April 11, 2023
    Assignee: SONY GROUP CORPORATION
    Inventors: Nobutoshi Fujii, Yoshihisa Kagawa
  • Publication number: 20230098931
    Abstract: A first semiconductor device includes: a first wiring layer including a first interlayer insulating film, a first electrode pad, and a first dummy electrode, the first electrode pad being embedded in the first interlayer insulating film and having one surface located on same plane as one surface of the first interlayer insulating film, and the first dummy electrode being embedded in the first interlayer insulating film, having one surface located on same plane as the one surface of the first interlayer insulating film, and being disposed around the first electrode pad; and a second wiring layer including a second interlayer insulating film, a second electrode pad, and a second dummy electrode, the second electrode pad being embedded in the second interlayer insulating film, having one surface located on same surface as one surface of the second interlayer insulating film, and being bonded to the first electrode pad, and the second dummy electrode having one surface located on same plane as the surface located
    Type: Application
    Filed: December 7, 2022
    Publication date: March 30, 2023
    Applicant: Sony Group Corporation
    Inventors: Nobutoshi Fujii, Yoshihisa Kagawa
  • Publication number: 20230067340
    Abstract: There are provided a light emitting device capable of forming a light emitting element on a suitable substrate and a method of manufacturing the same. A light emitting device according to the present disclosure includes: a first substrate; a plurality of light emitting elements that are provided on a first surface of the first substrate; and a second substrate that is provided on a second surface of the first substrate opposite to the first surface.
    Type: Application
    Filed: January 6, 2021
    Publication date: March 2, 2023
    Applicant: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventors: Suguru SAITO, Yuichi YAMAMOTO, Nobutoshi FUJII, Taizo TAKACHI