Patents by Inventor Nobutoshi Fujii

Nobutoshi Fujii has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11525984
    Abstract: The present technology relates to, for example, a lens attached substrate including a substrate which has a through-hole formed therein and a light shielding film formed on a side wall of the through-hole and a lens resin portion which is formed inside the through-hole of the substrate. The present technology can be applied to, for example, a lens attached substrate, a layered lens structure, a camera module, a manufacturing apparatus, a manufacturing method, an electronic device, a computer, a program, a storage medium, a system, and the like.
    Type: Grant
    Filed: October 26, 2021
    Date of Patent: December 13, 2022
    Assignee: Sony Semiconductor Solutions Corporation
    Inventors: Yusuke Moriya, Masanori Iwasaki, Takashi Oinoue, Yoshiya Hagimoto, Hiroyasu Matsugai, Hiroyuki Itou, Suguru Saito, Keiji Ohshima, Nobutoshi Fujii, Hiroshi Tazawa, Toshiaki Shiraiwa, Minoru Ishida
  • Publication number: 20220375984
    Abstract: The present technology relates to an imaging device, an electronic apparatus, and a method of manufacturing an imaging device capable of thinning a semiconductor on a terminal extraction surface while maintaining a strength of a semiconductor chip. There is provided an imaging device including: a first substrate having a pixel region in which pixels are two-dimensionally arranged, the pixels performing photoelectric conversion of light; and a second substrate in which a through silicon via is formed, in which a dug portion is formed in a back surface of the second substrate opposite to an incident side of light of the second substrate, and a redistribution layer (RDL) connected to a back surface of the first substrate is formed in the dug portion. The present technology can be applied to, for example, a semiconductor package including a semiconductor chip.
    Type: Application
    Filed: April 8, 2022
    Publication date: November 24, 2022
    Inventors: SUGURU SAITO, NOBUTOSHI FUJII
  • Publication number: 20220367558
    Abstract: An apparatus and method enabling a reduction in a resistance of a conductive path electrically connecting an upper substrate and a lower substrate. The apparatus includes a first semiconductor layer with element formation regions disposed adjacent to one another via element isolation regions, each of the element formation regions having a first active element, contact regions on an element isolation region side of a front layer portion of the element formation regions, conductive pads connected to the contact regions and extending across the element isolation region, a first insulating layer, a second semiconductor layer on the first insulating layer and having a second active element, a second insulating layer covering the second semiconductor layer, and conductive plugs extending from the second insulating layer to the conductive pad, the conductive plugs including a material identical to a material of the conductive pad and formed integrally with the conductive pad.
    Type: Application
    Filed: June 26, 2020
    Publication date: November 17, 2022
    Applicant: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventors: Nobutoshi FUJII, Koichi SEJIMA, Koichiro SAGA, Shinichi MIYAKE
  • Publication number: 20220359620
    Abstract: An imaging device according to an embodiment of the present disclosure includes: a first semiconductor substrate (100) provided with pixels including a photoelectric conversion element (PD) and floating diffusion (FD) that temporarily holds a charge output from the photoelectric conversion element (PD); and a semiconductor layer (200Y) provided on the first semiconductor substrate (100) via an insulating film (123), the semiconductor layer (200Y) including a readout circuit unit (539) that reads out the charge held in the floating diffusion (FD) and outputs a pixel signal, in which the semiconductor layer (200Y) is formed of an organic semiconductor material.
    Type: Application
    Filed: June 17, 2020
    Publication date: November 10, 2022
    Inventors: KENYA NISHIO, SUGURU SAITO, NOBUTOSHI FUJII, HIROTAKA YOSHIOKA
  • Publication number: 20220328549
    Abstract: The present disclosure relates to an imaging device, an electronic device, and a manufacturing method enabling to reduce a manufacturing cost. There are provided: a first semiconductor element including an imaging element configured to generate a pixel signal; and a second semiconductor element in which a first signal processing circuit and a second signal processing circuit that are configured to process the pixel signal are embedded by an embedded member. The first signal processing circuit has a structure including at least one more layer than the second signal processing circuit. There are further provided: a first wiring line that connects the first semiconductor element and the first signal processing circuit; and a second wiring line that connects the first signal processing circuit and the second signal processing circuit. The present disclosure can be applied to an imaging device.
    Type: Application
    Filed: August 27, 2020
    Publication date: October 13, 2022
    Applicant: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventors: Yosuke NITTA, Yoshiya HAGIMOTO, Nobutoshi FUJII, Yuichi YAMAMOTO
  • Publication number: 20220271070
    Abstract: There is provided a solid-state imaging device including: a first semiconductor layer including a photoelectric converter and an electric charge accumulation section for each pixel, the electric charge accumulation section in which a signal electric charge generated in the photoelectric converter is accumulated; a pixel separation section that is provided in the first semiconductor layer, and partitions a plurality of the pixels from each other; a second semiconductor layer that is provided with a pixel transistor and is stacked on the first semiconductor layer, the pixel transistor that reads the signal electric charge of the electric charge accumulation section; and a first shared coupling section that is provided between the second semiconductor layer and the first semiconductor layer, and is provided to straddle the pixel separation section and is electrically coupled to a plurality of the electric charge accumulation sections.
    Type: Application
    Filed: June 26, 2020
    Publication date: August 25, 2022
    Applicant: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventors: Keiichi NAKAZAWA, Koichiro ZAITSU, Nobutoshi FUJII, Yohei HIURA, Shigetaka MORI, Shintaro OKAMOTO, Keiji OHSHIMA, Shuji MANDA, Junpei YAMAMOTO, Yui YUGA, Shinichi MIYAKE, Tomoki KAMBE, Ryo OGATA, Tatsuki MIYAJI, Shinji NAKAGAWA, Hirofumi YAMASHITA, Yasushi HAMAMOTO, Naohiko KIMIZUKA
  • Publication number: 20220246498
    Abstract: A first semiconductor device includes: a first wiring layer including a first interlayer insulating film, a first electrode pad, and a first dummy electrode, the first electrode pad being embedded in the first interlayer insulating film and having one surface located on same plane as one surface of the first interlayer insulating film, and the first dummy electrode being embedded in the first interlayer insulating film, having one surface located on same plane as the one surface of the first interlayer insulating film, and being disposed around the first electrode pad; and a second wiring layer including a second interlayer insulating film, a second electrode pad, and a second dummy electrode, the second electrode pad being embedded in the second interlayer insulating film, having one surface located on same surface as one surface of the second interlayer insulating film, and being bonded to the first electrode pad, and the second dummy electrode having one surface located on same plane as the surface located
    Type: Application
    Filed: February 18, 2022
    Publication date: August 4, 2022
    Applicant: Sony Group Corporation
    Inventors: Nobutoshi Fujii, Yoshihisa Kagawa
  • Publication number: 20220230907
    Abstract: Provided are a semiconductor device in which an air gap structure can be formed in any desired region regardless of the layout of metallic wiring lines, a method for manufacturing the semiconductor device, and an electronic apparatus. A first wiring layer and a second wiring layer including a metallic film are stacked via a diffusion preventing film that prevents diffusion of the metallic film. The diffusion preventing film is formed by burying a second film in a large number of holes formed in a first film. At least the first wiring layer includes the metallic film, an air gap, and a protective film formed with the second film on the inner peripheral surface of the air gap, and the opening width of the air gap is equal to the opening width of the holes formed in the first film or is greater than the opening width of the holes.
    Type: Application
    Filed: February 1, 2022
    Publication date: July 21, 2022
    Inventors: SUGURU SAITO, NOBUTOSHI FUJII, MASAKI HANEDA, KAZUNORI NAGAHATA
  • Publication number: 20220165767
    Abstract: An imaging device according to an embodiment of the present disclosure includes: a first substrate including, in a first semiconductor substrate, a sensor pixel that performs photoelectric conversion; a second substrate including, in a second semiconductor substrate, a readout circuit that outputs a pixel signal based on electric charges outputted from the sensor pixel, the second substrate being stacked on the first substrate; a first insulating layer provided between the first semiconductor substrate and the second semiconductor substrate; and a second insulating layer provided between the first semiconductor substrate and the second semiconductor substrate, and having lower film density than the first insulating layer.
    Type: Application
    Filed: February 13, 2020
    Publication date: May 26, 2022
    Inventors: NOBUTOSHI FUJII, KATSUNORI HIRAMATSU, KEIICHI NAKAZAWA
  • Patent number: 11342371
    Abstract: A deformation of a stacked lens is suppressed. A stacked lens structure has a configuration in which substrates with lenses having a lens disposed on an inner side of a through-hole formed in the substrate are bonded and stacked by direct bonding. The present technique can be applied to a camera module or the like in which a stacked lens structure in which at least three substrates with lenses including first to third substrates with lenses which are substrates with lenses in which a through-hole is formed in the substrate and a lens is formed on an inner side of the through-hole is integrated with a light receiving element, for example.
    Type: Grant
    Filed: July 31, 2020
    Date of Patent: May 24, 2022
    Assignee: SONY CORPORATION
    Inventors: Hiroyasu Matsugai, Hiroyuki Itou, Suguru Saito, Keiji Ohshima, Masanori Iwasaki, Toshihiko Hayashi, Shuzo Sato, Nobutoshi Fujii, Hiroshi Tazawa, Toshiaki Shiraiwa, Minoru Ishida
  • Patent number: 11322538
    Abstract: The present technology relates to an imaging device, an electronic apparatus, and a method of manufacturing an imaging device capable of thinning a semiconductor on a terminal extraction surface while maintaining a strength of a semiconductor chip. There is provided an imaging device including: a first substrate having a pixel region in which pixels are two-dimensionally arranged, the pixels performing photoelectric conversion of light; and a second substrate in which a through silicon via is formed, in which a dug portion is formed in a back surface of the second substrate opposite to an incident side of light of the second substrate, and a redistribution layer (RDL) connected to a back surface of the first substrate is formed in the dug portion. The present technology can be applied to, for example, a semiconductor package including a semiconductor chip.
    Type: Grant
    Filed: February 8, 2018
    Date of Patent: May 3, 2022
    Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventors: Suguru Saito, Nobutoshi Fujii
  • Patent number: 11264272
    Abstract: The present technology relates to Provided are a semiconductor device in which an air gap structure can be formed in any desired region regardless of the layout of metallic wiring lines, a method for manufacturing the semiconductor device, and an electronic apparatus. A first wiring layer and a second wiring layer including a metallic film are stacked via a diffusion preventing film that prevents diffusion of the metallic film. The diffusion preventing film is formed by burying a second film in a large number of holes formed in a first film. At least the first wiring layer includes the metallic film, an air gap, and a protective film formed with the second film on the inner peripheral surface of the air gap, and the opening width of the air gap is equal to the opening width of the holes formed in the first film or is greater than the opening width of the holes.
    Type: Grant
    Filed: December 28, 2018
    Date of Patent: March 1, 2022
    Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventors: Suguru Saito, Nobutoshi Fujii, Masaki Haneda, Kazunori Nagahata
  • Patent number: 11262485
    Abstract: There is provided imaging devices and methods of forming the same, the imaging devices, including: a photodetector layer; and a light-blocking member stacked above the photodetector layer, where the light-blocking member includes at least one light-transmitting portion and at least one lens portion.
    Type: Grant
    Filed: June 24, 2016
    Date of Patent: March 1, 2022
    Assignee: Sony Semiconductor Solutions Corporation
    Inventors: Nobutoshi Fujii, Hiroyuki Itou
  • Publication number: 20220043241
    Abstract: The present technology relates to, for example, a lens attached substrate including a substrate which has a through-hole formed therein and a light shielding film formed on a side wall of the through-hole and a lens resin portion which is formed inside the through-hole of the substrate. The present technology can be applied to, for example, a lens attached substrate, a layered lens structure, a camera module, a manufacturing apparatus, a manufacturing method, an electronic device, a computer, a program, a storage medium, a system, and the like.
    Type: Application
    Filed: October 26, 2021
    Publication date: February 10, 2022
    Applicant: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventors: Yusuke MORIYA, Masanori IWASAKI, Takashi OINOUE, Yoshiya HAGIMOTO, Hiroyasu MATSUGAI, Hiroyuki ITOU, Suguru SAITO, Keiji OHSHIMA, Nobutoshi FUJII, Hiroshi TAZAWA, Toshiaki SHIRAIWA, Minoru ISHIDA
  • Publication number: 20220013567
    Abstract: The present disclosure includes a first substrate including a first wiring layer having a first connection electrode projecting by a predetermined quantity from a first interlayer insulation film and a second wiring layer having a second connection electrode projecting by a predetermined quantity from a second interlayer insulation film. On a bonded surface between the first and second substrates, the first and second connection electrodes are joined with each other, and at the same time, at least a part of the first interlayer insulation film and a part of the second interlayer insulation film which face to each other in a lamination direction are joined with each other.
    Type: Application
    Filed: April 26, 2021
    Publication date: January 13, 2022
    Inventors: NOBUTOSHI FUJII, KENICHI AOYAGI
  • Publication number: 20210408092
    Abstract: Provided is an imaging device (1) including: an imaging element (10); and a semiconductor element (20, 30) provided to be opposed to the imaging element and electrically coupled to the imaging element. The semiconductor element includes: a wiring region (20A, 30A) provided in a middle portion and a peripheral region (20B, 30B) outside the wiring region; a wiring layer (22, 32) having a wiring line in the wiring region; a semiconductor substrate (21, 31) opposed to the imaging element with the wiring layer interposed therebetween and having a first surface (Sa, Sc) and a second surface (Sb, Sd) in order from a side of the wiring layer; and a polishing adjustment section (23, 33) including a material that is lower in polishing rate than a constituent material of the semiconductor substrate, the polishing adjustment section being disposed in at least a portion of the peripheral region and provided in a thickness direction of the semiconductor substrate from the second surface.
    Type: Application
    Filed: October 9, 2019
    Publication date: December 30, 2021
    Inventors: Sotetsu SAITO, Suguru SAITO, Nobutoshi FUJII
  • Publication number: 20210391369
    Abstract: To provide a semiconductor device having a structure suitable for higher integration. This semiconductor device includes: a first semiconductor substrate; and a second semiconductor substrate. The first semiconductor substrate is provided with a first electrode including a first protruding portion and a first base portion. The first protruding portion includes a first abutting surface. The first base portion is linked to the first protruding portion and has volume greater than volume of the first protruding portion. The second semiconductor substrate is provided with a second electrode including a second protruding portion and a second base portion. The second protruding portion includes a second abutting surface that abuts the first abutting surface. The second base portion is linked to the second protruding portion and has volume greater than volume of the second protruding portion. The second semiconductor substrate is stacked on the first semiconductor substrate.
    Type: Application
    Filed: September 17, 2019
    Publication date: December 16, 2021
    Inventors: YOSHIYA HAGIMOTO, NOBUTOSHI FUJII
  • Patent number: 11194135
    Abstract: The present technology relates to, for example, a lens attached substrate including a substrate which has a through-hole formed therein and a light shielding film formed on a side wall of the through-hole and a lens resin portion which is formed inside the through-hole of the substrate. The present technology can be applied to, for example, a lens attached substrate, a layered lens structure, a camera module, a manufacturing apparatus, a manufacturing method, an electronic device, a computer, a program, a storage medium, a system, and the like.
    Type: Grant
    Filed: July 10, 2019
    Date of Patent: December 7, 2021
    Assignee: Sony Semiconductor Solutions Corporation
    Inventors: Yusuke Moriya, Masanori Iwasaki, Takashi Oinoue, Yoshiya Hagimoto, Hiroyasu Matsugai, Hiroyuki Itou, Suguru Saito, Keiji Ohshima, Nobutoshi Fujii, Hiroshi Tazawa, Toshiaki Shiraiwa, Minoru Ishida
  • Publication number: 20210366958
    Abstract: A semiconductor device includes a first substrate having an attaching surface on which first electrodes and a first insulating film are exposed, an insulating thin film that covers the attaching surface of the first substrate, and a second substrate which has an attaching surface on which second electrodes and a second insulating film are exposed and is attached to the first substrate in a state in which the attaching surface of the second substrate and the attaching surface of the first substrate are attached together sandwiching the insulating thin film therebetween, and the first electrodes and the second electrodes deform and break a part of the insulating thin film so as to be directly electrically connected to each other.
    Type: Application
    Filed: August 3, 2021
    Publication date: November 25, 2021
    Applicant: Sony Group Corporation
    Inventors: Nobutoshi Fujii, Yoshiya Hagimoto, Kenichi Aoyagi, Yoshihisa Kagawa
  • Publication number: 20210305300
    Abstract: The present technology relates to techniques of preventing intrusion of moisture into a chip. Various illustrative embodiments include image sensors that include: a substrate; a plurality of layers stacked on the substrate; the plurality of layers including a photodiode layer having a plurality of photodiodes formed on a surface of the photodiode layer; the plurality of layers including at least one layer having a groove formed such that a portion of the at least one layer is excavated; and a transparent resin layer formed above the photodiode layer and formed in the groove. The present technology can be applied to, for example, an image sensor.
    Type: Application
    Filed: January 8, 2021
    Publication date: September 30, 2021
    Applicant: SONY CORPORATION
    Inventors: Atsushi YAMAMOTO, Shinji MIYAZAWA, Yutaka OOKA, Kensaku MAEDA, Yusuke MORIYA, Naoki OGAWA, Nobutoshi FUJII, Shunsuke FURUSE, Masaya NAGATA, Yuichi YAMAMOTO