Patents by Inventor Nobuyoshi Takahashi
Nobuyoshi Takahashi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10679948Abstract: A semiconductor device includes first and second inspection mark regions having the same pattern including a plurality of overlay inspection marks, a first element region having a portion overlapping with the first inspection mark region, and a second element region having a portion overlapping with the second inspection mark region. The first and second element regions are adjacent to each other and have different areas. The first element region includes a first pattern aligned with a plurality of first overlay inspection marks. The second element region includes a second pattern aligned with a plurality of second overlay inspection marks.Type: GrantFiled: November 19, 2018Date of Patent: June 9, 2020Assignee: TowerJazz Panasonic Semiconductor Co., Ltd.Inventors: Takahisa Ogawa, Mitsunori Fukura, Nobuyoshi Takahashi
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Patent number: 10483125Abstract: A semiconductor device includes a first interlayer film formed on an upper surface of a substrate, a first metal wiring line, a second interlayer film, a second metal wiring line, a first via electrically connecting the first metal wiring line and the second metal wiring line, a landing pad embedded in an upper portion of the first interlayer film and penetrating the second interlayer film, and a second via penetrating the substrate and the first interlayer film from a back side of the substrate and connected to the landing pad. The lower surface position of the landing pad is different from that of the first metal wiring line.Type: GrantFiled: August 28, 2018Date of Patent: November 19, 2019Assignee: TOWERJAZZ PANASONIC SEMICONDUCTOR CO., LTD.Inventors: Yuka Inoue, Mitsunori Fukura, Nobuyoshi Takahashi, Masahiro Oda, Hisashi Yano, Yutaka Ito, Yasunori Morinaga
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Publication number: 20190088602Abstract: A semiconductor device includes first and second inspection mark regions having the same pattern including a plurality of overlay inspection marks, a first element region having a portion overlapping with the first inspection mark region, and a second element region having a portion overlapping with the second inspection mark region. The first and second element regions are adjacent to each other and have different areas. The first element region includes a first pattern aligned with a plurality of first overlay inspection marks. The second element region includes a second pattern aligned with a plurality of second overlay inspection marks.Type: ApplicationFiled: November 19, 2018Publication date: March 21, 2019Inventors: Takahisa OGAWA, Mitsunori FUKURA, Nobuyoshi TAKAHASHI
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Publication number: 20180366342Abstract: A semiconductor device includes a first interlayer film formed on an upper surface of a substrate, a first metal wiring line, a second interlayer film, a second metal wiring line, a first via electrically connecting the first metal wiring line and the second metal wiring line, a landing pad embedded in an upper portion of the first interlayer film and penetrating the second interlayer film, and a second via penetrating the substrate and the first interlayer film from a back side of the substrate and connected to the landing pad. The lower surface position of the landing pad is different from that of the first metal wiring line.Type: ApplicationFiled: August 28, 2018Publication date: December 20, 2018Inventors: Yuka INOUE, Mitsunori FUKURA, Nobuyoshi TAKAHASHI, Masahiro ODA, Hisashi YANO, Yutaka ITO, Yasunori MORINAGA
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Patent number: 9828749Abstract: To provide a hybrid wheel loader capable of reliably detecting a short-circuited state of a synchronous generator driven by a drive source. The present invention is provided with an MG 4 being a synchronous generator driven as an electric generator by an engine and operated as a motor by the electric power supplied from an electrical storage device 9, an MG inverter 5 having a motor current sensor 5d for detecting motor current flowing through the MG 4 and semiconductor switches 5a, 5b, and an HCU 10 for detecting a short-circuited state of the MG 4, wherein the HCU 10 determines that the MG 4 is in a short-circuited state when the semiconductor switches 5a, 5b of the MG inverter 5 are in an OFF state at gates and when the motor current detected by the motor current sensor 5d is equal to or greater than a specified threshold value.Type: GrantFiled: February 27, 2015Date of Patent: November 28, 2017Assignee: Hitachi Construction Machinery Co., Ltd.Inventors: Tomonori Takada, Shigeyuki Yoshihara, Toshihiko Ishida, Nobuyoshi Takahashi, Naoya Kawakami
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Patent number: 9735204Abstract: Each imaging pixel provided in a solid-state imaging device includes a charge accumulation part which is a diffusion region formed in a substrate, a gate electrode formed lateral to the charge accumulation part on the substrate, an insulating film formed on the charge accumulation part, and a contact plug connected to the charge accumulation part so as to penetrate the insulating film and made of semiconductor. The contact plug is, at a lower part thereof, embedded in the insulating film, and is, at an upper part thereof, exposed through the insulating film. Silicide is formed on the upper part of the contact plug, and the charge accumulation part and the gate electrode are covered by the insulating film.Type: GrantFiled: November 25, 2014Date of Patent: August 15, 2017Assignee: Panasonic Intellectual Property Management Co., Ltd.Inventors: Ryota Sakaida, Nobuyoshi Takahashi, Kosaku Saeki
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Patent number: 9647038Abstract: A solid-state imaging device includes: a semiconductor substrate; a pixel unit formed on the semiconductor substrate; and a peripheral circuit unit formed on the semiconductor substrate, at a periphery of the pixel unit, in which the pixel unit includes: a photoelectric conversion film which converts incident light into charges; and a floating diffusion which holds the charges, the peripheral circuit unit includes a transistor including a gate electrode and two source and drain diffusion regions, and the two source and drain diffusion regions have a higher impurity concentration than an impurity concentration of the floating diffusion.Type: GrantFiled: June 28, 2016Date of Patent: May 9, 2017Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.Inventors: Yoshiya Moriyama, Hiromasa Fujimoto, Kosaku Saeki, Nobuyoshi Takahashi
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Publication number: 20160307967Abstract: A solid-state imaging device includes: a semiconductor substrate; a pixel unit formed on the semiconductor substrate; and a peripheral circuit unit formed on the semiconductor substrate, at a periphery of the pixel unit, in which the pixel unit includes: a photoelectric conversion film which converts incident light into charges; and a floating diffusion which holds the charges, the peripheral circuit unit includes a transistor including a gate electrode and two source and drain diffusion regions, and the two source and drain diffusion regions have a higher impurity concentration than an impurity concentration of the floating diffusion.Type: ApplicationFiled: June 28, 2016Publication date: October 20, 2016Inventors: Yoshiya MORIYAMA, Hiromasa FUJIMOTO, Kosaku SAEKI, Nobuyoshi TAKAHASHI
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Patent number: 9406722Abstract: A solid-state imaging device includes: a semiconductor substrate; a pixel unit formed on the semiconductor substrate; and a peripheral circuit unit formed on the semiconductor substrate, at a periphery of the pixel unit, in which the pixel unit includes: a photoelectric conversion film which converts incident light into charges; and a floating diffusion which holds the charges, the peripheral circuit unit includes a transistor including a gate electrode and two source and drain diffusion regions, and the two source and drain diffusion regions have a higher impurity concentration than an impurity concentration of the floating diffusion.Type: GrantFiled: November 25, 2014Date of Patent: August 2, 2016Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.Inventors: Yoshiya Moriyama, Hiromasa Fujimoto, Kosaku Saeki, Nobuyoshi Takahashi
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Publication number: 20160194855Abstract: To provide a hybrid wheel loader capable of reliably detecting a short-circuited state of a synchronous generator driven by a drive source. The present invention is provided with an MG 4 being a synchronous generator driven as an electric generator by an engine and operated as a motor by the electric power supplied from an electrical storage device 9, an MG inverter 5 having a motor current sensor 5d for detecting motor current flowing through the MG 4 and semiconductor switches 5a, 5b, and an HCU 10 for detecting a short-circuited state of the MG 4, wherein the HCU 10 determines that the MG 4 is in a short-circuited state when the semiconductor switches 5a, 5b of the MG inverter 5 are in an OFF state at gates and when the motor current detected by the motor current sensor 5d is equal to or greater than a specified threshold value.Type: ApplicationFiled: February 27, 2015Publication date: July 7, 2016Inventors: Tomonori TAKADA, Shigeyuki YOSHIHARA, Toshihiko ISHIDA, Nobuyoshi TAKAHASHI, Naoya KAWAKAMI
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Publication number: 20150076500Abstract: Each imaging pixel provided in a solid-state imaging device includes a charge accumulation part which is a diffusion region formed in a substrate, a gate electrode formed lateral to the charge accumulation part on the substrate, an insulating film formed on the charge accumulation part, and a contact plug connected to the charge accumulation part so as to penetrate the insulating film and made of semiconductor. The contact plug is, at a lower part thereof, embedded in the insulating film, and is, at an upper part thereof, exposed through the insulating film. Silicide is formed on the upper part of the contact plug, and the charge accumulation part and the gate electrode are covered by the insulating film.Type: ApplicationFiled: November 25, 2014Publication date: March 19, 2015Inventors: Ryota SAKAIDA, Nobuyoshi TAKAHASHI, Kosaku SAEKI
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Publication number: 20150076484Abstract: A solid-state imaging device includes: a semiconductor substrate; a pixel unit formed on the semiconductor substrate; and a peripheral circuit unit formed on the semiconductor substrate, at a periphery of the pixel unit, in which the pixel unit includes: a photoelectric conversion film which converts incident light into charges; and a floating diffusion which holds the charges, the peripheral circuit unit includes a transistor including a gate electrode and two source and drain diffusion regions, and the two source and drain diffusion regions have a higher impurity concentration than an impurity concentration of the floating diffusion.Type: ApplicationFiled: November 25, 2014Publication date: March 19, 2015Inventors: Yoshiya MORIYAMA, Hiromasa FUJIMOTO, Kosaku SAEKI, Nobuyoshi TAKAHASHI
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Patent number: 8628740Abstract: A method of processing waste iron chloride solution including ferrous chloride, ferric chloride or mixtures thereof and optionally free hydrochloric acid, includes concentrating waste iron chloride solution into concentrated liquid having iron chloride concentration of at least 30%-40% by weight; optionally oxidizing ferrous chloride in the concentrated liquid from the concentration step to ferric chloride providing liquid containing ferric chloride; hydrolyzing the liquid containing ferric chloride from the oxidation step at 155-350° C.Type: GrantFiled: June 18, 2009Date of Patent: January 14, 2014Assignee: SMS Siemag AktiengesellschaftInventors: Nobuyoshi Takahashi, Osama Taki, Herbert Weissenbaeck, Dieter Vogl
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Patent number: 8569824Abstract: The semiconductor device includes: a plurality of bit lines formed in stripes in a semiconductor substrate of a first conductivity type, each of the bit lines being a diffusion layer of an impurity of a second conductivity type; a plurality of gate insulation films formed on regions of the semiconductor substrate between the bit lines; a plurality of word lines formed on the semiconductor substrate via the gate insulating films, the word lines extending in a direction intersecting with the bit lines; and a plurality of bit line isolation diffusion layers formed in regions of the semiconductor substrate between the word lines, each of the bit line isolation diffusion layers being a diffusion layer of an impurity of the first conductivity type. The bit line isolation diffusion layer includes a diffusion suppressor for suppressing diffusion of an impurity.Type: GrantFiled: January 27, 2009Date of Patent: October 29, 2013Assignee: Panasonic CorporationInventors: Nobuyoshi Takahashi, Ichirou Matsuo
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Patent number: 8076196Abstract: The semiconductor device includes: memory cells each having a first multilayer electrode including a first lower electrode made of a first conductive film and a first upper electrode made of a second conductive film formed one on the other with a first interface film therebetween; and a diode having a diode electrode made of the second conductive film and a second interface film as a silicon oxide film formed at the interface between the diode electrode and a substrate. The first interface film has a thickness with which electrical connection between the lower electrode and the upper electrode is maintained, and the second interface film has a thickness with which epitaxial growth between the substrate and the diode electrode is inhibited.Type: GrantFiled: October 6, 2010Date of Patent: December 13, 2011Assignee: Panasonic CorporationInventor: Nobuyoshi Takahashi
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Publication number: 20110158869Abstract: A method of processing waste iron chloride solution including ferrous chloride, ferric chloride or mixtures thereof and optionally free hydrochloric acid, includes concentrating waste iron chloride solution into concentrated liquid having iron chloride concentration of at least 30%-40% by weight; optionally oxidizing ferrous chloride in the concentrated liquid from the concentration step to ferric chloride providing liquid containing ferric chloride; hydrolyzing the liquid containing ferric chloride from the oxidation step at 155-350° C.Type: ApplicationFiled: June 18, 2009Publication date: June 30, 2011Applicant: SMS SIEMAG AKTIENGESELLSCHAFTInventors: Nobuyoshi Takahashi, Osama Taki, Herbert Weissenbaeck, Dieter Vogl
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Patent number: 7951679Abstract: First, on a semiconductor region of a first conductivity type, a trapping film is formed which stores information by accumulating charges. Then, the trapping film is formed with a plurality of openings, and impurity ions of a second conductivity type are implanted into the semiconductor region from the formed openings, thereby forming a plurality of diffused layers of the second conductivity type in portions of the semiconductor region located below the openings, respectively. An insulating film is formed to cover edges of the trapping film located toward the openings, and then the semiconductor region is subjected to a thermal process in an atmosphere containing oxygen to oxidize upper portions of the diffused layers. Thereby, insulating oxide films are formed in the upper portions of the diffused layers, respectively. Subsequently, a conductive film is formed over the trapping film including the edges thereof to form an electrode.Type: GrantFiled: July 25, 2005Date of Patent: May 31, 2011Assignee: Panasonic CorporationInventors: Koji Yoshida, Keita Takahashi, Fumihiko Noro, Masatoshi Arai, Nobuyoshi Takahashi
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Publication number: 20110084277Abstract: A semiconductor memory device has a plurality of word line provided on a semiconductor region, extending in a row direction, a plurality of bit lines provided in the semiconductor region, extending in a column direction, and a plurality of memory elements provided at intersections between the plurality of word lines and the plurality of bit lines. Each word line provides a first gate electrode in the corresponding memory element. A lower portion of a side surface of each word line in a direction parallel to an extending direction of the word line is perpendicular to a main surface of the semiconductor region. An upper portion of the side surface is inclined so that a width thereof becomes smaller toward a top thereof.Type: ApplicationFiled: December 20, 2010Publication date: April 14, 2011Applicant: PANASONIC CORPORATIONInventors: Koichi Kawashima, Nobuyoshi Takahashi, Yuichiro Higuchi
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Publication number: 20110021013Abstract: The semiconductor device includes: memory cells each having a first multilayer electrode including a first lower electrode made of a first conductive film and a first upper electrode made of a second conductive film formed one on the other with a first interface film therebetween; and a diode having a diode electrode made of the second conductive film and a second interface film as a silicon oxide film formed at the interface between the diode electrode and a substrate. The first interface film has a thickness with which electrical connection between the lower electrode and the upper electrode is maintained, and the second interface film has a thickness with which epitaxial growth between the substrate and the diode electrode is inhibited.Type: ApplicationFiled: October 6, 2010Publication date: January 27, 2011Applicant: PANASONIC CORPORATIONInventor: Nobuyoshi TAKAHASHI
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Patent number: 7834401Abstract: The semiconductor device includes: memory cells each having a first multilayer electrode including a first lower electrode made of a first conductive film and a first upper electrode made of a second conductive film formed one on the other with a first interface film therebetween; and a diode having a diode electrode made of the second conductive film and a second interface film as a silicon oxide film formed at the interface between the diode electrode and a substrate. The first interface film has a thickness with which electrical connection between the lower electrode and the upper electrode is maintained, and the second interface film has a thickness with which epitaxial growth between the substrate and the diode electrode is inhibited.Type: GrantFiled: February 11, 2009Date of Patent: November 16, 2010Assignee: Panasonic CorporationInventor: Nobuyoshi Takahashi