Patents by Inventor Nobuyoshi Takahashi
Nobuyoshi Takahashi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7807557Abstract: A semiconductor device includes: source/drain regions formed in a semiconductor substrate; a trapping film for storing information by accumulating charges, the trapping film being formed in a region on the semiconductor substrate which includes a region on a channel region between the source/drain regions; and gate electrodes formed on the trapping film. A silicon nitride film containing carbon is formed by low pressure CVD using an organic material so as to cover the gate electrodes and a part of the trapping film which is located between adjacent gate electrodes.Type: GrantFiled: June 5, 2007Date of Patent: October 5, 2010Assignee: Panasonic CorporationInventors: Koji Yoshida, Masataka Kusumi, Hiroaki Kuriyama, Fumihiko Noro, Nobuyoshi Takahashi
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Publication number: 20100213987Abstract: A semiconductor device includes an element to be protected formed on a semiconductor substrate, a first protection transistor, and a second protection transistor. The first protection transistor is formed on a first well of a first conductivity type formed in an upper portion of a deep well of a second conductivity type. The second protection transistor is formed on a second well of the second conductivity type. A second source/drain diffusion layer is electrically connected with a third source/drain diffusion layer and at the same potential as the first well. A fourth source/drain diffusion layer is electrically connected with a second diffusion layer and at the same potential as the second well and the second diffusion layer.Type: ApplicationFiled: December 7, 2009Publication date: August 26, 2010Inventors: Keita TAKAHASHI, Nobuyoshi Takahashi
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Patent number: 7781291Abstract: A semiconductor device includes a memory section formed at a semiconductor substrate and including a first transistor having an ONO film that can store charges between the semiconductor substrate and a memory electrode and a first STI region for isolating the first transistor, and a CMOS section formed at the semiconductor substrate and including a second transistor having a CMOS electrode and a gate dielectric and a second STI region for isolating the second transistor. The height of the top surface of the first STI region is set equal to or smaller than the height of the top surface of the second STI region.Type: GrantFiled: September 1, 2009Date of Patent: August 24, 2010Assignee: Panasonic CorporationInventors: Nobuyoshi Takahashi, Satoshi Iwamoto, Fumihiko Noro, Masatoshi Arai
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Patent number: 7704803Abstract: A semiconductor device includes: a semiconductor region; a plurality of bit line diffusion layers formed in an upper portion of the semiconductor region and each extending in a row direction; a plurality of bit line insulating films formed on the bit line diffusion layers; a plurality of gate insulting films formed between the respective adjacent bit line diffusion layers on the semiconductor region; and a plurality of word lines each formed on the semiconductor region in a column direction and each intersecting with the bit line insulating films and the gate insulating films. Memory cells are formed at intersections of the gate insulating films and the word lines. A plurality of connection diffusion layers including connection parts electrically connected to the bit line diffusion layers are formed in the upper portion of the semiconductor region, and a level of upper faces of the connection parts is lower than a level of upper faces of the connection diffusion layers in the semiconductor region.Type: GrantFiled: December 17, 2008Date of Patent: April 27, 2010Assignee: Panasonic CorporationInventors: Nobuyoshi Takahashi, Fumihiko Noro, Kenji Sato
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Publication number: 20090321814Abstract: A semiconductor memory device includes, in a memory region, a plurality of bit line diffusion layers, a plurality of word lines, and a plurality of memory elements composed of a bit line diffusion layer pair, a gate insulating film, and a gate electrode. The plurality of bit line diffusion layers are divided into plural in respective columns, and are connected electrically to each other through bit line contact diffusion layers. The width of sidewall insulating films on the sides of the bit line contact diffusion layers formed at the word lines arranged adjacent to the bit line contact diffusion layers is smaller than that of the sidewall insulating films formed on the opposite sides of the bit line contact diffusion layers.Type: ApplicationFiled: April 30, 2009Publication date: December 31, 2009Inventors: Koichi KAWASHIMA, Nobuyoshi Takahashi
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Publication number: 20090317955Abstract: A semiconductor device includes a memory section formed at a semiconductor substrate and including a first transistor having an ONO film that can store charges between the semiconductor substrate and a memory electrode and a first STI region for isolating the first transistor, and a CMOS section formed at the semiconductor substrate and including a second transistor having a CMOS electrode and a gate dielectric and a second STI region for isolating the second transistor. The height of the top surface of the first STI region is set equal to or smaller than the height of the top surface of the second STI region.Type: ApplicationFiled: September 1, 2009Publication date: December 24, 2009Applicant: PANASONIC CORPORATIONInventors: Nobuyoshi TAKAHASHI, Satoshi Iwamoto, Fumihiko Noro, Masatoshi Arai
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Publication number: 20090256232Abstract: The semiconductor device includes: memory cells each having a first multilayer electrode including a first lower electrode made of a first conductive film and a first upper electrode made of a second conductive film formed one on the other with a first interface film therebetween; and a diode having a diode electrode made of the second conductive film and a second interface film as a silicon oxide film formed at the interface between the diode electrode and a substrate. The first interface film has a thickness with which electrical connection between the lower electrode and the upper electrode is maintained, and the second interface film has a thickness with which epitaxial growth between the substrate and the diode electrode is inhibited.Type: ApplicationFiled: February 11, 2009Publication date: October 15, 2009Inventor: Nobuyoshi TAKAHASHI
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Patent number: 7598589Abstract: A semiconductor device includes a memory section formed at a semiconductor substrate and including a first transistor having an ONO film that can store charges between the semiconductor substrate and a memory electrode and a first STI region for isolating the first transistor, and a CMOS section formed at the semiconductor substrate and including a second transistor having a CMOS electrode and a gate dielectric and a second STI region for isolating the second transistor. The height of the top surface of the first STI region is set equal to or smaller than the height of the top surface of the second STI region.Type: GrantFiled: June 15, 2005Date of Patent: October 6, 2009Assignee: Panasonic CorporationInventors: Nobuyoshi Takahashi, Satoshi Iwamoto, Fumihiko Noro, Masatoshi Arai
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Publication number: 20090189214Abstract: The semiconductor device includes: a plurality of bit lines formed in stripes in a semiconductor substrate of a first conductivity type, each of the bit lines being a diffusion layer of an impurity of a second conductivity type; a plurality of gate insulation films s formed on regions of the semiconductor substrate between the bit lines; a plurality of word lines formed on the semiconductor substrate via the gate insulating films, the word lines extending in a direction intersecting with the bit lines; and a plurality of bit line isolation diffusion layers formed in regions of the semiconductor substrate between the word lines, each of the bit line isolation diffusion layers being a diffusion layer of an impurity of the first conductivity type. The bit line isolation diffusion layer includes a diffusion suppressor for suppressing diffusion of an impurity.Type: ApplicationFiled: January 27, 2009Publication date: July 30, 2009Inventors: Nobuyoshi Takahashi, Ichirou Matsuo
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Publication number: 20090104765Abstract: A semiconductor device includes: a semiconductor region; a plurality of bit line diffusion layers formed in an upper portion of the semiconductor region and each extending in a row direction; a plurality of bit line insulating films formed on the bit line diffusion layers; a plurality of gate insulting films formed between the respective adjacent bit line diffusion layers on the semiconductor region; and a plurality of word lines each formed on the semiconductor region in a column direction and each intersecting with the bit line insulating films and the gate insulating films. Memory cells are formed at intersections of the gate insulating films and the word lines. A plurality of connection diffusion layers including connection parts electrically connected to the bit line diffusion layers are formed in the upper portion of the semiconductor region, and a level of upper faces of the connection parts is lower than a level of upper faces of the connection diffusion layers in the semiconductor region.Type: ApplicationFiled: December 17, 2008Publication date: April 23, 2009Applicant: Matsushita Electric Industrial Co., Ltd. (PANASONIC CORPORATION)Inventors: Nobuyoshi TAKAHASHI, Fumihiko Noro, Kenji Sato
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Publication number: 20090057767Abstract: A semiconductor device includes a protected device formed on a semiconductor substrate, a first protection transistor formed in a second well of a second conductivity type, and a second protection transistor formed in a first well of a first conductivity type. A fourth source/drain diffusion layer of the second protection transistor is in contact with a second diffusion layer, and a third source/drain diffusion layer is in contact with a second source/drain diffusion layer of the first protection transistor in the second well. A first source/drain diffusion layer of the first protection transistor is in contact with a first diffusion layer, which is in contact with a protected device electrode.Type: ApplicationFiled: August 25, 2008Publication date: March 5, 2009Inventors: Nobuyoshi Takahashi, Keita Takahashi
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Publication number: 20090052250Abstract: A semiconductor memory device has a plurality of word line provided on a semiconductor region, extending in a row direction, a plurality of bit lines provided in the semiconductor region, extending in a column direction, and a plurality of memory elements provided at intersections between the plurality of word lines and the plurality of bit lines. Each word line provides a first gate electrode in the corresponding memory element. A lower portion of a side surface of each word line in a direction parallel to an extending direction of the word line is perpendicular to a main surface of the semiconductor region. An upper portion of the side surface is inclined so that a width thereof becomes smaller toward a top thereof.Type: ApplicationFiled: July 23, 2008Publication date: February 26, 2009Inventors: Koichi KAWASHIMA, Nobuyoshi TAKAHASHI, Yuichiro HIGUCHI
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Patent number: 7476943Abstract: A semiconductor device includes: a semiconductor region; a plurality of bit line diffusion layers formed in an upper portion of the semiconductor region and each extending in a row direction; a plurality of bit line insulating films formed on the bit line diffusion layers; a plurality of gate insulting films formed between the respective adjacent bit line diffusion layers on the semiconductor region; and a plurality of word lines each formed on the semiconductor region in a column direction and each intersecting with the bit line insulating films and the gate insulating films. Memory cells are formed at intersections of the gate insulating films and the word lines. A plurality of connection diffusion layers including connection parts electrically connected to the bit line diffusion layers are formed in the upper portion of the semiconductor region, and a level of upper faces of the connection parts is lower than a level of upper faces of the connection diffusion layers in the semiconductor region.Type: GrantFiled: April 18, 2006Date of Patent: January 13, 2009Assignee: Panasonic CorporationInventors: Nobuyoshi Takahashi, Fumihiko Noro, Kenji Sato
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Patent number: 7446381Abstract: A semiconductor memory device has a memory region which is formed on a semiconductor substrate and in which a plurality of memory cells each including a memory transistor are arranged as a matrix using a plurality of impurity diffusion layers (bit lines) and a plurality of gate electrodes (word lines) intersecting each other. The gate electrode of each of the memory transistors has an upper surface thereof formed into a protruding portion which is higher in level at the middle portion than at the edge portions. A silicide layer is formed on the upper surface of the protruding portion of the gate electrode of each of the memory transistors.Type: GrantFiled: June 14, 2005Date of Patent: November 4, 2008Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Takahiko Hashidzume, Fumihiko Noro, Nobuyoshi Takahashi
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Patent number: 7439577Abstract: A semiconductor memory is provided with memory cells including bit lines made of a diffusion layer formed in a semiconductor substrate, charge-trapping gate insulating films formed between the bit lines and word lines formed on the gate insulating films. An interlayer insulating film is formed over the memory cells and bit line contact plugs are formed in the interlayer insulating film to be connected to the bit lines. Further, a light blocking film is formed on at least part of the interlayer insulating film covering the memory cells and part of the light blocking film formed on the interlayer insulating film extends from the surface to the inside of the interlayer insulating film in the neighborhood of the bit line contact plugs.Type: GrantFiled: July 31, 2006Date of Patent: October 21, 2008Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Takahiko Hashidzume, Nobuyoshi Takahashi, Koji Yoshida, Keita Takahashi, Kiyoshi Kurihara, Yoshiya Moriyama
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Publication number: 20080048247Abstract: A semiconductor device includes: source/drain regions formed in a semiconductor substrate; a trapping film for storing information by accumulating charges, the trapping film being formed in a region on the semiconductor substrate which includes a region on a channel region between the source/drain regions; and gate electrodes formed on the trapping film. A silicon nitride film containing carbon is formed by low pressure CVD using an organic material so as to cover the gate electrodes and a part of the trapping film which is located between adjacent gate electrodes.Type: ApplicationFiled: June 5, 2007Publication date: February 28, 2008Inventors: Koji Yoshida, Masataka Kusumi, Hiroaki Kuriyama, Fumihiko Noro, Nobuyoshi Takahashi
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Patent number: 7309629Abstract: In a method for fabricating a semiconductor device in which a semiconductor memory element having an ONO film and a CMOS part are formed on a single semiconductor substrate, a CMOS gate-oxidation step is performed several times. Thereafter, a bit line diffusion layer and a bit line oxide film are formed in the semiconductor memory element.Type: GrantFiled: September 27, 2006Date of Patent: December 18, 2007Assignee: Matsushita Electric Industrial Co., Ltd.Inventor: Nobuyoshi Takahashi
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Publication number: 20070108509Abstract: A semiconductor memory is provided with memory cells including bit lines made of a diffusion layer formed in a semiconductor substrate, charge-trapping gate insulating films formed between the bit lines and word lines formed on the gate insulating films. An interlayer insulating film is formed over the memory cells and bit line contact plugs are formed in the interlayer insulating film to be connected to the bit lines. Further, a light blocking film is formed on at least part of the interlayer insulating film covering the memory cells and part of the light blocking film formed on the interlayer insulating film extends from the surface to the inside of the interlayer insulating film in the neighborhood of the bit line contact plugs.Type: ApplicationFiled: July 31, 2006Publication date: May 17, 2007Inventors: Takahiko Hashidzume, Nobuyoshi Takahashi, Koji Yoshida, Keita Takahashi, Kiyoshi Kurihara, Yoshiya Moriyama
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Patent number: 7214578Abstract: In a method for fabricating a semiconductor device in which a semiconductor memory element having an ONO film and a CMOS part are formed on a single semiconductor substrate, a CMOS gate-oxidation step is performed several times. Thereafter, a bit line diffusion layer and a bit line oxide film are formed in the semiconductor memory element.Type: GrantFiled: January 13, 2005Date of Patent: May 8, 2007Assignee: Matsushita Electric Industrial Co., Ltd.Inventor: Nobuyoshi Takahashi
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Publication number: 20070020848Abstract: In a method for fabricating a semiconductor device in which a semiconductor memory element having an ONO film and a CMOS part are formed on a single semiconductor substrate, a CMOS gate-oxidation step is performed several times. Thereafter, a bit line diffusion layer and a bit line oxide film are formed in the semiconductor memory element.Type: ApplicationFiled: September 27, 2006Publication date: January 25, 2007Applicant: Matsushita Electric Industrial Co., Ltd.Inventor: Nobuyoshi Takahashi