Patents by Inventor Nobuyuki Okuzawa

Nobuyuki Okuzawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11380482
    Abstract: A dielectric composition including a complex oxide containing bismuth, zinc, and niobium, includes a crystal phase formed of the complex oxide and having a pyrochlore type crystal structure, and an amorphous phase. When the complex oxide is represented by a composition formula BixZnyNbzO1.75+?, in which x, y, and z satisfy relations of x+y+z=1.00, 0.20?y?0.50, and 2/3?x/z?3/2.
    Type: Grant
    Filed: March 15, 2019
    Date of Patent: July 5, 2022
    Assignee: TDK CORPORATION
    Inventors: Shota Suzuki, Nobuyuki Okuzawa, Daisuke Hirose, Shirou Ootsuki, Wakiko Sato
  • Publication number: 20220130595
    Abstract: Disclosed herein is a coil component that includes a coil pattern embedded in an element body and helically wound in a plurality of turns. The element body includes a support body having a cavity formed therein and a first insulating layer stacked on the support body so as to cover the cavity, thereby forming a hollow space inside the element body. The coil pattern includes a plurality of first sections formed along an inner wall of the cavity and a plurality of second sections formed on the first insulating layer. One ends of the plurality of first sections are connected respectively to their corresponding one ends of the plurality of second sections. The other ends of the plurality of first sections are connected respectively to their corresponding other ends of the plurality of second sections.
    Type: Application
    Filed: October 18, 2021
    Publication date: April 28, 2022
    Inventors: Nobuyuki OKUZAWA, Kazuhiko ITO, Munehiro TAKAKU, Junichiro URABE
  • Publication number: 20220130596
    Abstract: Disclosed herein is a coil component that includes a coil pattern embedded in a resin body. The resin body includes a winding core area surrounded by the coil pattern and having a first surface and a substantially flat second surface different in the circumferential direction position from the first surface, and a first surrounding area covering the first surface of the winding core area. The coil pattern includes first sections extending along the first surface of the winding core area and second sections extending along the second surface of the winding core area. One ends of the first sections are connected respectively to their corresponding one ends of the second sections. The other ends of the first sections are connected respectively to their corresponding other ends of the second sections.
    Type: Application
    Filed: October 18, 2021
    Publication date: April 28, 2022
    Inventors: Nobuyuki OKUZAWA, Kazuhiko ITO, Munehiro TAKAKU, Junichiro URABE
  • Publication number: 20220130601
    Abstract: Disclosed herein is a coil component that includes a resin body having a first resin-based insulating material and a second resin-based insulating material lower in relative permittivity than the first resin-based insulating material, a coil pattern embedded in the resin body and helically wound in a plurality of turns, and first and second terminal electrodes formed on a surface of the resin body and connected respectively to one and other ends of the coil pattern. The coil pattern has a part covered with the first resin-based insulating material and another part covered with the second resin-based insulating material.
    Type: Application
    Filed: October 18, 2021
    Publication date: April 28, 2022
    Inventors: Nobuyuki OKUZAWA, Kazuhiko ITO, Munehiro TAKAKU, Junichiro URABE
  • Publication number: 20210012961
    Abstract: A dielectric composition including a complex oxide containing bismuth, zinc, and niobium, includes a crystal phase formed of the complex oxide and having a pyrochlore type crystal structure, and an amorphous phase. When the complex oxide is represented by a composition formula BixZnyNbzO1.75+?, in which x, y, and z satisfy relations of x+y+z=1.00, 0.20?y?0.50, and 2/3?x/z?3/2.
    Type: Application
    Filed: March 15, 2019
    Publication date: January 14, 2021
    Applicant: TDK CORPORATION
    Inventors: Shota SUZUKI, Nobuyuki OKUZAWA, Daisuke HIROSE, Shirou OOTSUKI, Wakiko SATO
  • Publication number: 20200294687
    Abstract: A dielectric composition contains a complex oxide represented by a composition formula of BixZnyNbzO1.75+?. x+y+z=1.00. x<0.20. 0.20?y?0.50. 0.25?x/z. A dielectric composition contains a complex oxide represented by a composition formula of BixZnyNbzO1.75+?. x+y+z=1.00. 0.20?y?0.50. 1.5<x/z?3.0. z<0.25.
    Type: Application
    Filed: March 13, 2020
    Publication date: September 17, 2020
    Applicant: TDK Corporation
    Inventors: Shota SUZUKI, Nobuyuki OKUZAWA
  • Patent number: 8513034
    Abstract: A method of manufacturing a layered chip package that includes a main body, and wiring disposed on a side surface of the main body. The main body includes a plurality of layer portions. The method includes fabricating a plurality of substructures, and completing the layered chip package by fabricating the main body using the plurality of substructures and by forming the wiring on the main body.
    Type: Grant
    Filed: April 22, 2011
    Date of Patent: August 20, 2013
    Assignees: Headway Technologies, Inc., TDK Corporation, SAE Magnetics (H.K.) Ltd.
    Inventors: Yoshitaka Sasaki, Hiroyuki Ito, Tatsuya Harada, Nobuyuki Okuzawa, Satoru Sueki, Hiroshi Ikejima
  • Patent number: 8324741
    Abstract: A layered chip package has a main body including pairs of layer portions, and wiring disposed on a side surface of the main body. Each layer portion includes a semiconductor chip. The pairs of layer portions include specific pairs of layer portions. Each of the specific pairs of layer portions includes a first-type layer portion and a second-type layer portion. The first-type layer portion includes electrodes each connected to the semiconductor chip and each having an end face located at the side surface of the main body on which the wiring is disposed, whereas the second-type layer portion does not include such electrodes. The specific pairs of layer portions are provided in an even number.
    Type: Grant
    Filed: May 16, 2011
    Date of Patent: December 4, 2012
    Assignees: Headway Technologies, Inc., TDK Corporation, SAE Magnetics (H.K.) Ltd.
    Inventors: Yoshitaka Sasaki, Hiroyuki Ito, Tatsuya Harada, Nobuyuki Okuzawa, Satoru Sueki, Hiroshi Ikejima
  • Patent number: 8154116
    Abstract: A layered chip package includes: a plurality of layer portions stacked, each of the layer portions including a semiconductor chip; and a heat sink. Each of the plurality of layer portions has a top surface, a bottom surface, and four side surfaces. The heat sink has at least one first portion, and a second portion coupled to the at least one first portion. The at least one first portion is adjacent to the top surface or the bottom surface of at least one of the layer portions. The second portion is adjacent to one of the side surfaces of each of at least two of the plurality of layer portions.
    Type: Grant
    Filed: November 3, 2008
    Date of Patent: April 10, 2012
    Assignees: HeadwayTechnologies, Inc., TDK Corporation, SAE Magnetics (H.K.) Ltd.
    Inventors: Yoshitaka Sasaki, Hiroyuki Ito, Tatsuya Harada, Nobuyuki Okuzawa, Satoru Sueki, Hiroshi Ikejima
  • Patent number: 8134229
    Abstract: A layered chip package includes a main body including a plurality of layer portions, and wiring disposed on a side surface of the main body. Each layer portion includes a semiconductor chip, an insulating portion covering at least one side surface of the semiconductor chip, and a plurality of electrodes connected to the semiconductor chip. The insulating portion has an end face located at the side surface of the main body on which the wiring is disposed. Each electrode has an end face surrounded by the insulating portion and located at the side surface of the main body on which the wiring is disposed.
    Type: Grant
    Filed: September 2, 2010
    Date of Patent: March 13, 2012
    Assignees: Headway Technologies, Inc., TDK Corporation
    Inventors: Yoshitaka Sasaki, Hiroyuki Ito, Tatsuya Harada, Nobuyuki Okuzawa, Satoru Sueki
  • Patent number: 8050045
    Abstract: The invention relates to a surface mount type electronic component mounted on a printed circuit board or hybrid IC (HIC) and a method of manufacturing the same and provides an electronic component which can be formed with a small size and a low height at a low cost and a method of manufacturing the same. A common mode choke coil as the electronic component has an overall shape in the form of rectangular parallelepiped that is provided by forming an insulation layer, a coil layer (not shown) formed with a coil conductor, and external electrodes electrically connected to the coil conductor in the order listed on a silicon substrate using thin film forming techniques. The external electrodes are formed to spread on a top surface (mounting surface) of the insulation layer.
    Type: Grant
    Filed: August 7, 2006
    Date of Patent: November 1, 2011
    Assignee: TDK Corporation
    Inventors: Nobuyuki Okuzawa, Makoto Yoshida
  • Publication number: 20110221073
    Abstract: A layered chip package has a main body including pairs of layer portions, and wiring disposed on a side surface of the main body. Each layer portion includes a semiconductor chip. The pairs of layer portions include specific pairs of layer portions. Each of the specific pairs of layer portions includes a first-type layer portion and a second-type layer portion. The first-type layer portion includes electrodes each connected to the semiconductor chip and each having an end face located at the side surface of the main body on which the wiring is disposed, whereas the second-type layer portion does not include such electrodes. The specific pairs of layer portions are provided in an even number.
    Type: Application
    Filed: May 16, 2011
    Publication date: September 15, 2011
    Applicants: HEADWAY TECHNOLOGIES, INC., SAE MAGNETICS (H.K.) LTD., TDK CORPORATION
    Inventors: Yoshitaka Sasaki, Hiroyuki Ito, Tatsuya Harada, Nobuyuki Okuzawa, Satoru Sueki, Hiroshi Ikejima
  • Publication number: 20110201137
    Abstract: A method of manufacturing a layered chip package that includes a main body, and wiring disposed on a side surface of the main body. The main body includes a plurality of layer portions. The method includes fabricating a plurality of substructures, and completing the layered chip package by fabricating the main body using the plurality of substructures and by forming the wiring on the main body.
    Type: Application
    Filed: April 22, 2011
    Publication date: August 18, 2011
    Applicants: HEADWAY TECHNOLOGIES, INC., TDK CORPORATION, SAE MAGNETICS (H.K.) LTD.
    Inventors: Yoshitaka Sasaki, Hiroyuki Ito, Tatsuya Harada, Nobuyuki Okuzawa, Satoru Sueki, Hiroshi Ikejima
  • Patent number: 7968374
    Abstract: A layered chip package has a main body including pairs of layer portions, and wiring disposed on a side surface of the main body. Each layer portion includes a semiconductor chip. The pairs of layer portions include at least one specific pair of layer portions including a first-type layer portion and a second-type layer portion. The first-type layer portion includes electrodes each connected to the semiconductor chip and each having an end face located at the side surface of the main body on which the wiring is disposed, whereas the second-type layer portion does not include such electrodes.
    Type: Grant
    Filed: February 6, 2009
    Date of Patent: June 28, 2011
    Assignees: Headway Technologies, Inc., TDK Corporation, SAE Magnetics (H.K.) Ltd.
    Inventors: Yoshitaka Sasaki, Hiroyuki Ito, Tatsuya Harada, Nobuyuki Okuzawa, Satoru Sueki, Hiroshi Ikejima
  • Patent number: 7964976
    Abstract: A layered chip package includes a main body including a plurality of layer portions, and wiring disposed on a side surface of the main body. The plurality of layer portions include at least one layer portion of a first type and at least one layer portion of a second type. The layer portions of the first and second types each include a semiconductor chip. The layer portion of the first type further includes a plurality of electrodes each connected to the semiconductor chip and each having an end face located at the side surface of the main body on which the wiring is disposed, whereas the layer portion of the second type does not include any electrode connected to the semiconductor chip and having an end face located at the side surface of the main body on which the wiring is disposed. The wiring is connected to the end face of each of the plurality of electrodes.
    Type: Grant
    Filed: August 20, 2008
    Date of Patent: June 21, 2011
    Assignees: Headway Technologies, Inc., TDK Corporation, SAE Magnetics (H.K.) Ltd.
    Inventors: Yoshitaka Sasaki, Hiroyuki Ito, Tatsuya Harada, Nobuyuki Okuzawa, Satoru Sueki, Hiroshi Ikejima
  • Patent number: 7905008
    Abstract: There is provided a method of manufacturing a coil component, where a first insulation layer is formed on a first magnetic substrate, an insulation film is formed on the first insulation layer, a coil conductor is formed on the insulation film, another insulation film is formed on the coil conductor, and an open region is formed on the inner circumference side and on the outer circumference side of the coil conductor. A magnetic later is embedded, at least partially, in the open region, and a second magnetic substrate is secured on the magnetic layer. Also, a plurality of electrode terminals are formed, where one of the electrode terminals is connected to a terminal portion of the coil conductor, and the electrode terminals are provided across sides of the first and second magnetic substrates. Therefore, the first insulation layer can suitably prevent shorting failures between the electrode terminals.
    Type: Grant
    Filed: October 24, 2006
    Date of Patent: March 15, 2011
    Assignee: TDK Corporation
    Inventors: Makoto Yoshida, Nobuyuki Okuzawa, Tomokazu Ito, Takashi Kudo, Makoto Otomo, Akira Sato
  • Patent number: 7868442
    Abstract: A layered chip package includes a plurality of layer portions stacked, each layer portion including a semiconductor chip having a first surface with a device formed thereon and a second surface opposite thereto. The plurality of layer portions include at least a pair of layer portions disposed such that the first surfaces of the respective semiconductor chips face toward each other. A manufacturing method for the layered chip package includes the steps of: fabricating a layered substructure by stacking a plurality of substructures each including a plurality of layer portions corresponding to the plurality of layer portions of the layered chip package; and fabricating a plurality of layered chip packages by using the layered substructure.
    Type: Grant
    Filed: June 30, 2008
    Date of Patent: January 11, 2011
    Assignees: Headway Technologies, Inc., TDK Corporation
    Inventors: Yoshitaka Sasaki, Hiroyuki Ito, Tatsuya Harada, Nobuyuki Okuzawa, Satoru Sueki
  • Patent number: 7863095
    Abstract: A layered chip package includes a plurality of layer portions stacked, each layer portion including a semiconductor chip having a first surface with a device formed thereon and a second surface opposite thereto. The plurality of layer portions include at least a pair of layer portions disposed such that the first surfaces of the respective semiconductor chips face toward each other. A manufacturing method for the layered chip package includes the steps of: fabricating a layered substructure by stacking a plurality of substructures each including a plurality of layer portions corresponding to the plurality of layer portions of the layered chip package; and fabricating a plurality of layered chip packages by using the layered substructure.
    Type: Grant
    Filed: July 30, 2010
    Date of Patent: January 4, 2011
    Assignees: Headway Technologies, Inc., TDK Corporation
    Inventors: Yoshitaka Sasaki, Hiroyuki Ito, Tatsuya Harada, Nobuyuki Okuzawa, Satoru Sueki
  • Publication number: 20100327464
    Abstract: A layered chip package includes a main body including a plurality of layer portions, and wiring disposed on a side surface of the main body. Each layer portion includes a semiconductor chip, an insulating portion covering at least one side surface of the semiconductor chip, and a plurality of electrodes connected to the semiconductor chip. The insulating portion has an end face located at the side surface of the main body on which the wiring is disposed. Each electrode has an end face surrounded by the insulating portion and located at the side surface of the main body on which the wiring is disposed.
    Type: Application
    Filed: September 2, 2010
    Publication date: December 30, 2010
    Applicants: HEADWAY TECHNOLOGIES, INC., TDK CORPORATION
    Inventors: Yoshitaka Sasaki, Hiroyuki Ito, Tatsuya Harada, Nobuyuki Okuzawa, Satoru Sueki
  • Patent number: 7846772
    Abstract: A layered chip package includes a main body including a plurality of layer portions, and wiring disposed on a side surface of the main body. Each layer portion includes a semiconductor chip, an insulating portion covering at least one side surface of the semiconductor chip, and a plurality of electrodes connected to the semiconductor chip. The insulating portion has an end face located at the side surface of the main body on which the wiring is disposed. Each electrode has an end face surrounded by the insulating portion and located at the side surface of the main body on which the wiring is disposed. To manufacture the layered chip package, a layered chip package substructure is fabricated by: processing a semiconductor wafer to form a plurality of pre-semiconductor-chip portions aligned; forming at least one groove extending to be adjacent to at least one of the pre-semiconductor-chip portions; forming an insulating layer to fill the groove; and forming the electrodes.
    Type: Grant
    Filed: June 23, 2008
    Date of Patent: December 7, 2010
    Assignees: Headway Technologies, Inc., TDK Corporation
    Inventors: Yoshitaka Sasaki, Hiroyuki Ito, Tatsuya Harada, Nobuyuki Okuzawa, Satoru Sueki