Patents by Inventor Nobuyuki Okuzawa

Nobuyuki Okuzawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7846772
    Abstract: A layered chip package includes a main body including a plurality of layer portions, and wiring disposed on a side surface of the main body. Each layer portion includes a semiconductor chip, an insulating portion covering at least one side surface of the semiconductor chip, and a plurality of electrodes connected to the semiconductor chip. The insulating portion has an end face located at the side surface of the main body on which the wiring is disposed. Each electrode has an end face surrounded by the insulating portion and located at the side surface of the main body on which the wiring is disposed. To manufacture the layered chip package, a layered chip package substructure is fabricated by: processing a semiconductor wafer to form a plurality of pre-semiconductor-chip portions aligned; forming at least one groove extending to be adjacent to at least one of the pre-semiconductor-chip portions; forming an insulating layer to fill the groove; and forming the electrodes.
    Type: Grant
    Filed: June 23, 2008
    Date of Patent: December 7, 2010
    Assignees: Headway Technologies, Inc., TDK Corporation
    Inventors: Yoshitaka Sasaki, Hiroyuki Ito, Tatsuya Harada, Nobuyuki Okuzawa, Satoru Sueki
  • Publication number: 20100304531
    Abstract: A layered chip package includes a plurality of layer portions stacked, each layer portion including a semiconductor chip having a first surface with a device formed thereon and a second surface opposite thereto. The plurality of layer portions include at least a pair of layer portions disposed such that the first surfaces of the respective semiconductor chips face toward each other. A manufacturing method for the layered chip package includes the steps of: fabricating a layered substructure by stacking a plurality of substructures each including a plurality of layer portions corresponding to the plurality of layer portions of the layered chip package; and fabricating a plurality of layered chip packages by using the layered substructure.
    Type: Application
    Filed: July 30, 2010
    Publication date: December 2, 2010
    Applicants: HEADWAY TECHNOLOGIES, INC., TDK CORPORATION
    Inventors: Yoshitaka Sasaki, Hiroyuki Ito, Tatsuya Harada, Nobuyuki Okuzawa, Satoru Sueki
  • Publication number: 20100200977
    Abstract: A layered chip package has a main body including a plurality of pairs of layer portions, and wiring disposed on a side surface of the main body. Each layer portion includes a semiconductor chip. The plurality of pairs of layer portions include at least one specific pair of layer portions consisting of a first-type layer portion and a second-type layer portion. The first-type layer portion includes a plurality of electrodes each connected to the semiconductor chip and each having an end face located at the side surface of the main body on which the wiring is disposed, whereas the second-type layer portion does not include such electrodes.
    Type: Application
    Filed: February 6, 2009
    Publication date: August 12, 2010
    Applicants: HEADWAY TECHNOLOGIES, INC., TDK CORPORATION, SAE MAGNETICS (H.K.) LTD.
    Inventors: Yoshitaka Sasaki, Hiroyuki Ito, Tatsuya Harada, Nobuyuki Okuzawa, Satoru Sueki, Hiroshi Ikejima
  • Patent number: 7767494
    Abstract: A manufacturing method for a layered chip package including a stack of a plurality of layer portions includes the steps of: fabricating a layered substructure by stacking a plurality of substructures each including a plurality of layer portions corresponding to the plurality of layer portions of the layered chip package; and fabricating a plurality of layered chip packages by using the layered substructure.
    Type: Grant
    Filed: June 30, 2008
    Date of Patent: August 3, 2010
    Assignees: Headway Technologies, Inc., TDK Corporation
    Inventors: Yoshitaka Sasaki, Hiroyuki Ito, Tatsuya Harada, Nobuyuki Okuzawa, Satoru Sueki
  • Patent number: 7745259
    Abstract: A layered chip package includes: a main body including a plurality of layer portions; wiring disposed on a side surface of the main body; a plurality of first terminals disposed on a top surface of the main body; and a plurality of second terminals disposed on a bottom surface of the main body. Each layer portion includes a semiconductor chip, an insulating portion covering at least one side surface of the semiconductor chip, and a plurality of electrodes connected to the semiconductor chip. Each electrode has an end face surrounded by the insulating portion and located at the side surface of the main body on which the wiring is disposed. The wiring is connected to the end faces of the plurality of electrodes of the plurality of layer portions, and to the plurality of first and second terminals.
    Type: Grant
    Filed: June 30, 2008
    Date of Patent: June 29, 2010
    Assignees: Headway Technologies, Inc., TDK Corporation
    Inventors: Yoshitaka Sasaki, Hiroyuki Ito, Tatsuya Harada, Nobuyuki Okuzawa, Satoru Sueki
  • Publication number: 20100109137
    Abstract: A layered chip package includes: a plurality of layer portions stacked, each of the layer portions including a semiconductor chip; and a heat sink. Each of the plurality of layer portions has a top surface, a bottom surface, and four side surfaces. The heat sink has at least one first portion, and a second portion coupled to the at least one first portion. The at least one first portion is adjacent to the top surface or the bottom surface of at least one of the layer portions. The second portion is adjacent to one of the side surfaces of each of at least two of the plurality of layer portions.
    Type: Application
    Filed: November 3, 2008
    Publication date: May 6, 2010
    Applicants: HEADWAY TECHNOLOGIES, INC., TDK CORPORATION, SAE MAGNETICS (H.K.) LTD.
    Inventors: Yoshitaka Sasaki, Hiroyuki Ito, Tatsuya Harada, Nobuyuki Okuzawa, Satoru Sueki, Hiroshi Ikejima
  • Patent number: 7683269
    Abstract: A terminal electrode body on a substrate is exposed relative to a resin layer, protruding out beyond the side of the resin layer. That is, the terminal electrode body is not covered by the resin layer. The electronic element is covered by an insulating layer and the terminal electrode body and the electronic element are electrically connected. Hence, an electric signal applied to the terminal electrode body can be transmitted to the electronic element. A cover layer covers the terminal electrode body and the boundary between the terminal electrode body and the resin layer.
    Type: Grant
    Filed: March 21, 2008
    Date of Patent: March 23, 2010
    Assignee: TDK Corporation
    Inventors: Toshiyuki Yoshizawa, Masaomi Ishikura, Masahiro Miyazaki, Akira Furuya, Nobuyuki Okuzawa
  • Publication number: 20100044879
    Abstract: A layered chip package includes a main body including a plurality of layer portions, and wiring disposed on a side surface of the main body. The plurality of layer portions include at least one layer portion of a first type and at least one layer portion of a second type. The layer portions of the first and second types each include a semiconductor chip. The layer portion of the first type further includes a plurality of electrodes each connected to the semiconductor chip and each having an end face located at the side surface of the main body on which the wiring is disposed, whereas the layer portion of the second type does not include any electrode connected to the semiconductor chip and having an end face located at the side surface of the main body on which the wiring is disposed. The wiring is connected to the end face of each of the plurality of electrodes.
    Type: Application
    Filed: August 20, 2008
    Publication date: February 25, 2010
    Applicants: HEADWAY TECHNOLOGIES, INC., TDK CORPORATION, SAE MAGNETICS (H.K.) LTD.
    Inventors: Yoshitaka Sasaki, Hiroyuki Ito, Tatsuya Harada, Nobuyuki Okuzawa, Satoru Sueki, Hiroshi Ikejima
  • Publication number: 20090325345
    Abstract: A manufacturing method for a layered chip package including a stack of a plurality of layer portions includes the steps of: fabricating a layered substructure by stacking a plurality of substructures each including a plurality of layer portions corresponding to the plurality of layer portions of the layered chip package; and fabricating a plurality of layered chip packages by using the layered substructure.
    Type: Application
    Filed: June 30, 2008
    Publication date: December 31, 2009
    Applicants: HEADWAY TECHNOLOGIES, INC., TDK CORPORATION
    Inventors: Yoshitaka Sasaki, Hiroyuki Ito, Tatsuya Harada, Nobuyuki Okuzawa, Satoru Sueki
  • Publication number: 20090321957
    Abstract: A layered chip package includes: a main body including a plurality of layer portions; wiring disposed on a side surface of the main body; a plurality of first terminals disposed on a top surface of the main body; and a plurality of second terminals disposed on a bottom surface of the main body. Each layer portion includes a semiconductor chip, an insulating portion covering at least one side surface of the semiconductor chip, and a plurality of electrodes connected to the semiconductor chip. Each electrode has an end face surrounded by the insulating portion and located at the side surface of the main body on which the wiring is disposed. The wiring is connected to the end faces of the plurality of electrodes of the plurality of layer portions, and to the plurality of first and second terminals.
    Type: Application
    Filed: June 30, 2008
    Publication date: December 31, 2009
    Applicants: HEADWAY TECHNOLOGIES, INC., TDK CORPORATION
    Inventors: Yoshitaka Sasaki, Hiroyuki Ito, Tatsuya Harada, Nobuyuki Okuzawa, Satoru Sueki
  • Publication number: 20090321956
    Abstract: A layered chip package includes a plurality of layer portions stacked, each layer portion including a semiconductor chip having a first surface with a device formed thereon and a second surface opposite thereto. The plurality of layer portions include at least a pair of layer portions disposed such that the first surfaces of the respective semiconductor chips face toward each other. A manufacturing method for the layered chip package includes the steps of: fabricating a layered substructure by stacking a plurality of substructures each including a plurality of layer portions corresponding to the plurality of layer portions of the layered chip package; and fabricating a plurality of layered chip packages by using the layered substructure.
    Type: Application
    Filed: June 30, 2008
    Publication date: December 31, 2009
    Applicants: TDK CORPORATION, HEADWAY TECHONOLOGIES, INC.
    Inventors: Yoshitaka Sasaki, Hiroyuki Ito, Tatsuya Harada, Nobuyuki Okuzawa, Satoru Sueki
  • Publication number: 20090315189
    Abstract: A layered chip package includes a main body including a plurality of layer portions, and wiring disposed on a side surface of the main body. Each layer portion includes a semiconductor chip, an insulating portion covering at least one side surface of the semiconductor chip, and a plurality of electrodes connected to the semiconductor chip. The insulating portion has an end face located at the side surface of the main body on which the wiring is disposed. Each electrode has an end face surrounded by the insulating portion and located at the side surface of the main body on which the wiring is disposed. To manufacture the layered chip package, a layered chip package substructure is fabricated by: processing a semiconductor wafer to form a plurality of pre-semiconductor-chip portions aligned; forming at least one groove extending to be adjacent to at least one of the pre-semiconductor-chip portions; forming an insulating layer to fill the groove; and forming the electrodes.
    Type: Application
    Filed: June 23, 2008
    Publication date: December 24, 2009
    Applicants: HEADWAY TECHNOLOGIES, INC., TDK CORPORATION
    Inventors: Yoshitaka Sasaki, Hiroyuki Ito, Tatsuya Harada, Nobuyuki Okuzawa, Satoru Sueki
  • Publication number: 20090244808
    Abstract: An object of the present invention is to restrain warpage in a thin-film trench capacitor. A thin-film capacitor includes a substrate, a dielectric film, and a pair of electrodes, and the dielectric film is provided along a concave-convex surface on which are formed a plurality of convex portions extending away from the substrate. The concave-convex surface forms a pattern having one or more divisions arranged in a plane parallel to the main plane of the substrate, and the convex portions are arranged in either parts of the divisions or other parts. At least some of the divisions have parts extending along the x axial direction, and two or more of the extending parts overlap each other and terminate at locations that are different from each other, as viewed from the y axial direction orthogonal to the x axial direction.
    Type: Application
    Filed: March 25, 2009
    Publication date: October 1, 2009
    Applicant: TDK CORPORATION
    Inventors: Takashi OHTSUKA, Nobuyuki OKUZAWA
  • Patent number: 7557439
    Abstract: A layered chip package includes a main body, and wiring disposed on a side surface of the main body. The main body includes a plurality of first-type layer portions each including a first-type semiconductor chip; and a second-type layer portion including a second-type semiconductor chip. The first-type semiconductor chip includes a plurality of memory cells. The second-type semiconductor chip includes a control circuit that controls writing and reading on and from the memory cells included in the plurality of first-type layer portions. Each layer portion includes an insulating portion covering at least one side surface of the semiconductor chip, and a plurality of electrodes connected to the semiconductor chip. Each of the electrodes has an end face that is located at the side surface of the main body and connected to the wiring.
    Type: Grant
    Filed: September 29, 2008
    Date of Patent: July 7, 2009
    Assignees: TDK Corporation, Headway Technologies, Inc.
    Inventors: Yoshitaka Sasaki, Hiroyuki Ito, Tatsuya Harada, Nobuyuki Okuzawa, Satoru Sueki, Ryuji Hashimoto
  • Publication number: 20080236885
    Abstract: A terminal electrode body on a substrate is exposed relative to a resin layer, protruding out beyond the side of the resin layer. That is, the terminal electrode body is not covered by the resin layer. The electronic element is covered by an insulating layer and the terminal electrode body and the electronic element are electrically connected. Hence, an electric signal applied to the terminal electrode body can be transmitted to the electronic element. A cover layer covers the terminal electrode body and the boundary between the terminal electrode body and the resin layer.
    Type: Application
    Filed: March 21, 2008
    Publication date: October 2, 2008
    Applicant: TDK CORPORATION
    Inventors: Toshiyuki YOSHIZAWA, Masaomi ISHIKURA, Masahiro MIYAZAKI, Akira FURUYA, Nobuyuki OKUZAWA
  • Patent number: 7414508
    Abstract: The invention relates to a common mode choke coil and a method of manufacturing the same and provides a compact, low-profile, and low-cost common mode choke coil and a method of manufacturing the same. A common mode choke coil has a general outline in the form of a rectangular parallelepiped provided by forming an insulation layer, a first helical coil unit, a second helical coil unit, and a closed magnetic path on a silicon substrate made of a single-crystal using thin film forming techniques. The first and second helical coil units are formed such that their axes of spiral extend substantially parallel to a substrate surface of the silicon substrate.
    Type: Grant
    Filed: September 28, 2006
    Date of Patent: August 19, 2008
    Assignee: TDK Corporation
    Inventors: Nobuyuki Okuzawa, Makoto Yoshida
  • Patent number: 7397334
    Abstract: The invention relates to a coil component used as a main component of a common mode choke coil or a transformer and a method of manufacturing the same, and the invention is aimed at providing a coil component with a small size and a low height having high differential transmission characteristics and a method of manufacturing the same. A common mode choke coil has a configuration in which an insulation film, a coil conductor, another insulation film, another coil conductor and another insulation film are stacked in the order listed between magnetic substrates provided opposite to each other. The coil conductors have a coil section which is in a trapezoidal general configuration. A top portion of the coil section is formed in a convex configuration such that it bulges in the form of a convex, and a bottom portion of the coil section is formed in a planar configuration.
    Type: Grant
    Filed: February 9, 2005
    Date of Patent: July 8, 2008
    Assignee: TDK Corporation
    Inventors: Makoto Yoshida, Nobuyuki Okuzawa, Tomokazu Ito, Yukari Hishimura, Yoshikazu Sato
  • Patent number: 7318269
    Abstract: The invention relates to a method of manufacturing a coil component uses as a major part of a common mode choke coil or a transformer, and there is provided a method of manufacturing a compact and low height coil component in which deterioration of impedance characteristics is low and reliability is high. An insulating film is formed on a magnetic substrate, and open regions are formed in the insulating film. A lead terminal portion is formed on the insulating film, and a planarizing film is formed on the open regions. An insulating film is formed and openings are formed in the insulating film at the open regions. A coil conductor is formed on the insulating film, and a planarizing film is further formed on the planarizing film. After a coil conductor is further formed on the coil conductor through the insulating film, the planarizing films are removed.
    Type: Grant
    Filed: August 13, 2004
    Date of Patent: January 15, 2008
    Assignee: TDK Corporation
    Inventors: Makoto Yoshida, Nobuyuki Okuzawa
  • Patent number: 7283028
    Abstract: Each of first and second coil conductors has a spiral form and is disposed between first and second magnetic substrates. The first and second coil conductors include first parts arranged so as to extend along each other with a predetermined gap therebetween on a first insulating layer, and second parts intersecting each other three-dimensionally. The first and second coil conductors intersect each other in their middle part as seen from a direction orthogonal to the principal face of the first magnetic substrate (second magnetic substrate).
    Type: Grant
    Filed: August 3, 2004
    Date of Patent: October 16, 2007
    Assignee: TDK Corporation
    Inventors: Makoto Yoshida, Tomokazu Ito, Tadashige Konno, Nobuyuki Okuzawa
  • Patent number: 7221250
    Abstract: The invention relates to a coil component used as a major component of a common mode choke coil or transformer and a method of manufacturing the same, and the invention is aimed at providing a compact and low-profile coil component having a high common mode filtering property and a method of manufacturing the same. A common mode choke coil has a configuration in which a first insulation film, a first coil conductor, a second insulation film, a second coil conductor and a third insulation film are stacked in the order listed between magnetic substrates provided opposite to each other. A top portion of the first coil conductor is formed in a convex shape. The second insulation film is formed so as to follow the shape of the top portion of the first coil conductor. A bottom portion of the second coil conductor is formed in a concave shape such that it follows the shape of a top portion of the second insulation film.
    Type: Grant
    Filed: February 23, 2005
    Date of Patent: May 22, 2007
    Assignee: TDK Corporation
    Inventors: Makoto Yoshida, Nobuyuki Okuzawa, Tomokazu Ito, Yukari Hishimura, Yoshikazu Sato