Abstract: Pipe regions PIPE0 to PIPEe (or endpoint regions) are allocated in a packet buffer, registers in which are set page sizes MPS0 to MPe (maximum packet size) and numbers of pages BP0 to BPe for the pipe regions are provided, and data is transferred between pipe regions and endpoints, region sizes RS0 to RSe of the pipe regions being set by the page sizes and numbers of pages. The page sizes and numbers of pages are set in registers that are used in common during both host operation and peripheral operation in accordance with the USB on-the-go standard. Transfer condition information such as transfer types TT0 to TTe is set in the registers, transactions with respect to the endpoints are automatically issued, and data is automatically transferred. Pipe regions are allocated in the packet buffer during host operation whereas endpoint regions are allocated during peripheral operation.

Abstract: A transaction is automatically issued with respect to one of end points and data is automatically transferred while the remaining data size of the transfer data is calculated based on the total size and the maximum packet size. When the remaining data size in the current transaction is less than the maximum packet size, the next transaction is issued automatically, and a short packet is transferred automatically to nest one of the end points. When the payload size of the packet to be transferred by the current transaction is the maximum packet size and the remaining data size of the transfer data is zero, a short packet of zero data length is transferred automatically to the next one of the end points. When DMA transfer is complete and the remaining data to be transferred is zero, a short packet of zero data length is transferred automatically in response to an IN token from a host. Data transfer according to USB On-The-Go is performed.

Abstract: A data transfer control device includes an OUT-transfer transmitter circuit which transmits OUT data by driving a serial signal line, a clock-transfer transmitter circuit which transmits a clock signal CLK by driving a serial signal line, a PLL circuit which generates the clock signal CLK, and a power-down setting circuit which sets a power-down mode. In a first power-down mode, the OUT-transfer transmitter circuit is set to the power-down mode, and the clock-transfer transmitter circuit is set to the power-down mode to stop a system clock signal of a target-side data transfer control device. In a second power-down mode, the OUT-transfer transmitter circuit is set to the power-down mode without setting the clock-transfer transmitter circuit to the power-down mode.

Abstract: A transmitter circuit including: a current driver which current-drives differential signal lines; and a voltage driver which is electrically disconnected from at least one of the differential signal lines in a normal transfer mode, and is electrically connected to the at least one of the differential signal lines and voltage-drives the at least one of the differential signal lines in a power-down mode. The voltage driver outputs a power-down voltage for setting a receiver circuit to the power-down mode or a wakeup voltage for canceling the power-down mode of the receiver circuit, to the at least one of the differential signal lines. The current driver transmits a power-down command to the receiver circuit by current-driving the differential signal lines in the normal transfer mode.

Abstract: A data transfer control device including: a buffer controller which allocates a plurality of pipe regions in a packet buffer and controls access to the packet buffer; and a transfer controller which controls data transfer between the pipe regions and corresponding endpoints. The transfer controller performs processing of pausing data transfer between the pipe regions and the endpoints, the buffer controller performs reconstruction processing which includes at least one of deletion, addition, and size change of the pipe regions after the completion of the pause processing, and then the transfer controller resumes the paused data transfer after the reconstruction processing of the pipe regions. Data in the pipe regions before the reconstruction processing is copied to the pipe regions after the reconstruction processing while preventing the data from being erased.

Abstract: A transmitter circuit including: a current driver which current-drives differential signal lines; and a voltage driver which is electrically disconnected from at least one of the differential signal lines in a normal transfer mode, and is electrically connected to the at least one of the differential signal lines and voltage-drives the at least one of the differential signal lines in a power-down mode. The voltage driver outputs a power-down voltage for setting a receiver circuit to the power-down mode or a wakeup voltage for canceling the power-down mode of the receiver circuit, to the at least one of the differential signal lines. The current driver transmits a power-down command to the receiver circuit by current-driving the differential signal lines in the normal transfer mode.

Abstract: An encryption/decryption device includes a storage section which stores input data and output data, a first encryption/decryption processing section which performs first encryption and decryption processing, and a second encryption/decryption processing section which performs second encryption and decryption processing. The encryption/decryption device stores decrypted data obtained by causing one of the first and second encryption/decryption processing sections to perform the first or second decryption processing for the input data in the storage section. The encryption/decryption device stores data obtained by causing the other of the first and second encryption/decryption processing sections to perform the first or second encryption processing for the decrypted data in the storage section as the output data. The storage area of the storage section for the decrypted data is configured to be inaccessible from the outside of the encryption/decryption device.

Abstract: A data transfer control device includes an OUT-transfer transmitter circuit which transmits OUT data by driving a serial signal line, a clock-transfer transmitter circuit which transmits a clock signal CLK by driving a serial signal line, a PLL circuit which generates the clock signal CLK, and a power-down setting circuit which sets a power-down mode. In a first power-down mode, the OUT-transfer transmitter circuit is set to the power-down mode, and the clock-transfer transmitter circuit is set to the power-down mode to stop a system clock signal of a target-side data transfer control device. In a second power-down mode, the OUT-transfer transmitter circuit is set to the power-down mode without setting the clock-transfer transmitter circuit to the power-down mode.

Abstract: Data to be transferred from a BUS1 (IEEE 1394 or USB) is encrypted by a second encryption process (DES) and the encrypted data is written to an external SDRAM through an external terminal of a data transfer control device. The encrypted data that has been written to the SDRAM is read through the external terminal, and the thus-read encrypted data is transferred to a BUS2 to which an HDD is connected. Encrypted data transferred from the BUS1 is decrypted by a first decryption process (DTCP), and is written to a small-capacity SRAM within the data transfer control device. The thus-written decrypted data is read from the SRAM and encrypted by the second encryption process. Paths that bypass the second encryption (or decryption) are also provided.

Abstract: A transmitter circuit including: a current driver which current-drives differential signal lines; and a voltage driver which is electrically disconnected from at least one of the differential signal lines in a normal transfer mode, and is electrically connected to the at least one of the differential signal lines and voltage-drives the at least one of the differential signal lines in a power-down mode. The voltage driver outputs a power-down voltage for setting a receiver circuit to the power-down mode or a wakeup voltage for canceling the power-down mode of the receiver circuit, to the at least one of the differential signal lines. The current driver transmits a power-down command to the receiver circuit by current-driving the differential signal lines in the normal transfer mode.

Abstract: An encryption/decryption device includes an encryption/decryption processing section which performs encryption or decryption processing for divided data of first and second content data in an operation mode of a block cipher method using data in a block other than a block under processing, and an intermediate value storage section which stores a processing result or an input value of the encryption/decryption processing section in content units. After the processing result or the input value of the encryption/decryption processing section for one of the divided data of the second content data has been stored in the intermediate value storage section, the processing result or the input value for the Kth divided data of the first content data is read from the intermediate value storage section, and the encryption/decryption processing section performs the encryption or decryption processing for the (K+1)th divided data of the first content data by using the processing result or the input value.

Abstract: An oscillation circuit generates a reference clock signal for a clock signal supplied to each section of a data transfer control device. In a clock output control circuit, a clock command is decoded by a clock command decoder and oscillation of the oscillation circuit is controlled. The data transfer control device including a clock control circuit transfers data as a host or a peripheral in a state being set to either a self-powered first device or a second device which can operate by using a power supply on a bus. The oscillation operation of the oscillation circuit is suspended in an idle state of the second device.

Abstract: A data transfer control device includes a DMAC1 that writes a packet transferred from a BUS1 (IEEE 1394 or USB), to a SRAM, a DMAC2 that reads the written isochronous data from the SRAM and writes it to a SDRAM, and a DMAC3 that reads the written isochronous data and transfers it to a BUS2 side. During transmission, isochronous data is read from the SDRAM and written to SRAM, and an isochronous packet including the written isochronous data is transferred to the BUS1 side. The SRAM includes an isochronous data area and an asynchronous data area. The SRAM is provided insides the data transfer control device and the SDRAM is provided on outside the data transfer control device.

Abstract: A processing section reserves a number of transfers for an isochronous packet which includes isochronous data in an transfer number reservation register TNREG. A DMAC1 reads that isochronous packet from SRAM, and the thus-read isochronous packet is transferred automatically to a BUS1 (IEEE 1394 or USB) side at each isochronous transfer cycle until the number of transfers reserved in TNREG reaches zero. An SRAM header area is divided into page K and page L areas, and registers TNREGK and TNREGL are provided for reserving a number of transfers for each of the page K and L areas. During a special reproduction, a data pointer is used to select a TS packet which includes an I picture, for automatic transfer to the BUS1 side.

Abstract: A transmitter circuit including: a current driver which current-drives differential signal lines; and a voltage driver which is electrically disconnected from at least one of the differential signal lines in a normal transfer mode, and is electrically connected to the at least one of the differential signal lines and voltage-drives the at least one of the differential signal lines in a power-down mode. The voltage driver outputs a power-down voltage for setting a receiver circuit to the power-down mode or a wakeup voltage for canceling the power-down mode of the receiver circuit, to the at least one of the differential signal lines. The current driver transmits a power-down command to the receiver circuit by current-driving the differential signal lines in the normal transfer mode.

Abstract: In a clock generating circuit, clocks generated therein are distributed by a clock distribution control circuit for every circuit block. In a clock output control circuit, a clock command is decoded by a clock command decoder and output of the clocks is controlled for every circuit block. A data transfer control device having a clock control circuit functions as a first device or a second device to transfer data as a host or a peripheral. When the data transfer control device function as a second device and in an idle state, it controls clock output to a state controller which controls switching between a host function and a peripheral function.

Abstract: A plurality of pipe regions PIPE0 to PIPEe in which data transferred to and from endpoints is stored are allocated in a packet buffer (FIFO). Transfer condition information on data transfer between the pipe regions and the endpoints is set in transfer condition registers TREG0 to TREGe in a register section. A host (transfer) controller automatically generates a transaction for each of the endpoints based on the transfer condition information (total size, maximum packet size, transfer direction, number of continuous execution times, token issue interval, and the like) set in the transfer condition registers, and automatically transfers data between each pipe region and the endpoint. An OTG (state) controller which controls a state of USB On-The-Go is provided. The pipe regions are allocated in the packet buffer during a host operation.

Abstract: A signal state detection circuit of a data transfer control device notifies a processing of results detected by a line state detection circuit or a power supply line detection circuit by using an interrupt signal. The processing sets a state command corresponding to a state of a transition destination judged based on the notified detection results in a control register of a state controller. A state command decoder decodes the state command set in the control register and generates a control signal. A signal line control circuit controls a signal state of at least one of signal lines formed of data signal lines (D+ and D?) and power supply lines (VBUS and GND) based on the control signal.

Abstract: A force sensor includes a shaft to which a magnet is fixed, and a case which can reciprocate with respect to the shaft and to which a Hall IC element is fixed. The Hall IC element outputs an output voltage which changes in accordance with relative displacement between the Hall IC element and the magnet. A main spring is interposed between the shaft and the case and elastically deforms in accordance with force produced between the shaft and the case in the reciprocating direction. A sub spring is provided in order to impart a preload such that when the amount of elastic deformation of the main spring is substantially zero, no axial clearance is formed between a flange portion of the shaft and one end portion of the main spring, and no axial clearance is formed between the case and the other end of the main spring.

Abstract: A state controller of a data transfer processing circuit switches an operation of an A-device or a B-device between a host operation and a peripheral operation by state transition. A power supply switch circuit connects a power supply circuit with a VBUS line based on transition of the state controller. A power supply switching circuit of a power supply control circuit connects the VBUS line or the power supply circuit with the data transfer processing circuit based on a switching signal. The switching signal is generated based on an output signal of a switch circuit or a control signal from the state controller.