Abstract: A receiver circuit includes: a current/voltage conversion circuit which performs a current/voltage conversion based on current which flows through the differential signal lines and outputs voltage signals; a comparator which compares the voltage signals and outputs an output signal; a power-down detection circuit which, when the transmitter circuit transmits a power-down command by current-driving the differential signal lines in a normal transfer mode, detects the transmitted power-down command based on a comparison result from the comparator; and a power-down setting circuit which sets at least one of the current/voltage conversion circuit and the comparator to a power-down mode when the power-down command is detected.

Abstract: A data transfer control device includes an OUT-transfer transmitter circuit which transmits OUT data by driving a serial signal line, a clock-transfer transmitter circuit which transmits a clock signal CLK by driving a serial signal line, a PLL circuit which generates the clock signal CLK, and a power-down setting circuit which sets a power-down mode. In a first power-down mode, the OUT-transfer transmitter circuit is set to the power-down mode, and the clock-transfer transmitter circuit is set to the power-down mode to stop a system clock signal of a target-side data transfer control device. In a second power-down mode, the OUT-transfer transmitter circuit is set to the power-down mode without setting the clock-transfer transmitter circuit to the power-down mode.

Abstract: A data transfer control device including: a buffer controller which allocates a plurality of pipe regions in a packet buffer and controls access to the packet buffer; and a transfer controller which controls data transfer between the pipe regions and corresponding endpoints. The transfer controller performs processing of pausing data transfer between the pipe regions and the endpoints, the buffer controller performs reconstruction processing which includes at least one of deletion, addition, and size change of the pipe regions after the completion of the pause processing, and then the transfer controller resumes the paused data transfer after the reconstruction processing of the pipe regions. Data in the pipe regions before the reconstruction processing is copied to the pipe regions after the reconstruction processing while preventing the data from being erased.

Abstract: A data transfer control device includes a buffer controller which allocates a plurality of pipe regions in a packet buffer and controls access to the packet buffer. The buffer controller includes an address translation table which stores a plurality of pipe region numbers each of which is assigned to one of a plurality of divided blocks in a memory region of the packet buffer and generates a physical access address of the packet buffer based on the stored pipe region numbers, one of the pipe region numbers to which access is requested, and a relative access address of the pipe regions, and a region allocator which performs reconstruction processing of the pipe regions (deletion, addition, or change in size of the pipe regions) by changing the pipe region numbers assigned to the divided blocks.

Abstract: A data transfer control device having: a hub dedicated data storage section which stores a packet transferred between the data transfer control device and a hub; a packet transmission section which cyclically issues a token packet to the hub for asking whether the state of the hub has changed or not; a packet reception section which receives a response packet sent from the hub in response to the token packet; and a transfer controller which writes the response packet received by the packet reception section into the hub dedicated data storage section, and generates an interrupt which indicates that the state of the hub has changed.

Abstract: When subcodes included in a CD format are reproduced, jitter is removed when the subcodes are synchronized with signal data. The data is connected together by using the subcode data to prevent interruptions of sound and pictures. An error correction unit performs error correction processing for signal data reproduced (read) from a CD. A memory stores the signal data whose error is corrected and a data output unit reads out the signal data stored in the memory according to a reference clock. A subcode detection/jitter removal unit detects subcode data reproduced from the CD and outputs the subcode data to the memory in synchronism with outputting of the signal data whose error is corrected by the error correction unit, to thereby remove jitter.

Abstract: In a clock generating circuit, clocks generated therein are distributed by a clock distribution control circuit for every circuit block. In a clock output control circuit, a clock command is decoded by a clock command decoder and output of the clocks is controlled for every circuit block. A data transfer control device having a clock control circuit functions as a first device or a second device to transfer data as a host or a peripheral. When the data transfer control device function as a second device and in an idle state, it controls clock output to a state controller which controls switching between a host function and a peripheral function.

Abstract: A transaction is automatically issued with respect to one of end points and data is automatically transferred while the remaining data size of the transfer data is calculated based on the total size and the maximum packet size. When the remaining data size in the current transaction is less than the maximum packet size, the next transaction is issued automatically, and a short packet is transferred automatically to nest one of the end points. When the payload size of the packet to be transferred by the current transaction is the maximum packet size and the remaining data size of the transfer data is zero, a short packet of zero data length is transferred automatically to the next one of the end points. When DMA transfer is complete and the remaining data to be transferred is zero, a short packet of zero data length is transferred automatically in response to an IN token from a host. Data transfer according to USB On-The-Go is performed.

Abstract: A state controller of a data transfer processing circuit switches an operation of an A-device or a B-device between a host operation and a peripheral operation by state transition. A power supply switch circuit connects a power supply circuit with a VBUS line based on transition of the state controller. A power supply switching circuit of a power supply control circuit connects the VBUS line or the power supply circuit with the data transfer processing circuit based on a switching signal. The switching signal is generated based on an output signal of a switch circuit or a control signal from the state controller.

Abstract: When transfer condition information is set and the start of automatic control transfer is instructed, a transfer controller (host controller) automatically issues a setup stage transaction and automatically transfers a setup stage packet, then, if there is data to be transferred, it automatically issues a data stage transaction and automatically transfers a data stage packet. It then automatically issues a status stage transaction and automatically transfers a status stage packet. Device request data, the total size of transfer data, data stage present/absent information, transfer direction in the data stage, and maximum packet size are set in transfer condition registers. A pipe region is allocated in the packet buffer during host operation of USB On-The-Go.

Abstract: Pipe regions PIPE0 to PIPEe (or endpoint regions) are allocated in a packet buffer, registers in which are set page sizes MPS0 to MPe (maximum packet size) and numbers of pages BP0 to BPe for the pipe regions are provided, and data is transferred between pipe regions and endpoints, region sizes RS0 to RSe of the pipe regions being set by the page sizes and numbers of pages. The page sizes and numbers of pages are set in registers that are used in common during both host operation and peripheral operation in accordance with the USB on-the-go standard. Transfer condition information such as transfer types TT0 to TTe is set in the registers, transactions with respect to the endpoints are automatically issued, and data is automatically transferred. Pipe regions are allocated in the packet buffer during host operation whereas endpoint regions are allocated during peripheral operation.

Abstract: An oscillation circuit generates a reference clock signal for a clock signal supplied to each section of a data transfer control device. In a clock output control circuit, a clock command is decoded by a clock command decoder and oscillation of the oscillation circuit is controlled. The data transfer control device including a clock control circuit transfers data as a host or a peripheral in a state being set to either a self-powered first device or a second device which can operate by using a power supply on a bus. The oscillation operation of the oscillation circuit is suspended in an idle state of the second device.

Abstract: Data to be transferred from a BUS1 (IEEE 1394 or USB) is encrypted by a second encryption process (DES) and the encrypted data is written to an external SDRAM through an external terminal of a data transfer control device. The encrypted data that has been written to the SDRAM is read through the external terminal, and the thus-read encrypted data is transferred to a BUS2 to which an HDD is connected. Encrypted data transferred from the BUS1 is decrypted by a first decryption process (DTCP), and is written to a small-capacity SRAM within the data transfer control device. The thus-written decrypted data is read from the SRAM and encrypted by the second encryption process. Paths that bypass the second encryption (or decryption) are also provided.

Abstract: When a first mode (with-SOF mode) has been set, data transfer is performed while SOF packets are transferred at frame periods, and when a second mode (non-SOF mode) has been set and also non-periodic (bulk) transfer is being performed, the periodic transfer of SOF packets is disabled and non-periodic data is transferred. If there is no non-periodic data to be transferred, a SOF packet is transferred in the frame period, even if the second mode has been set. During host operation with USB on-the-go (OTG), pipe regions are allocated to the packet buffer, and non-periodic data is transferred automatically to or from end points while the periodic transfer of SOF packets is disabled. When all of the automatic transfer instruction signals of the pipe regions are inactive, SOF packets are transferred periodically even if the second mode has been set.

Abstract: A plurality of pipe regions PIPE0 to PIPEe in which data transferred to and from endpoints is stored are allocated in a packet buffer (FIFO). Transfer condition information on data transfer between the pipe regions and the endpoints is set in transfer condition registers TREG0 to TREGe in a register section. A host (transfer) controller automatically generates a transaction for each of the endpoints based on the transfer condition information (total size, maximum packet size, transfer direction, number of continuous execution times, token issue interval, and the like) set in the transfer condition registers, and automatically transfers data between each pipe region and the endpoint. An OTG (state) controller which controls a state of USB On-The-Go is provided. The pipe regions are allocated in the packet buffer during a host operation.

Abstract: Messy and lots of questionable computer numbers in this, During reception, data to be transferred from a BUS1 (IEEE 1394 or USB) side is written into a reception data in SRAM, and, if the quantity of reception data exceeds a transfer unit ATU, data is read from the reception data area and transferred to a BUS2 side. During transmission, data transferred from the BUS2 side is written into a transmission data area in SRAM, and, when there is an instruction from a processing section (CPU) to start transmission (reservation of a number of transfers), the data that has been written into the transmission data area in SRAM is read and transferred to the BUS1 side. The size of the reception data area is smaller than that of the transmission data area. The transfer unit ATU is set to be equal to an encryption unit of a circuit (DES) that encrypts data read from the SRAM.

Abstract: A processing section reserves a number of transfers for an isochronous packet which includes isochronous data in an transfer number reservation register TNREG. A DMAC1 reads that isochronous packet from SRAM, and the thus-read isochronous packet is transferred automatically to a BUS1 (IEEE 1394 or USB) side at each isochronous transfer cycle until the number of transfers reserved in TNREG reaches zero. An SRAM header area is divided into page K and page L areas, and registers TNREGK and TNREGL are provided for reserving a number of transfers for each of the page K and L areas. During a special reproduction, a data pointer is used to select a TS packet which includes an I picture, for automatic transfer to the BUS1 side.

Abstract: A signal state detection circuit of a data transfer control device notifies a processing of results detected by a line state detection circuit or a power supply line detection circuit by using an interrupt signal. The processing sets a state command corresponding to a state of a transition destination judged based on the notified detection results in a control register of a state controller. A state command decoder decodes the state command set in the control register and generates a control signal. A signal line control circuit controls a signal state of at least one of signal lines formed of data signal lines (D+ and D−) and power supply lines (VBUS and GND) based on the control signal.

Abstract: A data transfer control device includes an OTG (state) controller which controls a plurality of states including a host operation state and a peripheral operation state, a host controller which is connected with a transceiver during the host operation, a peripheral controller which is connected with the transceiver during the peripheral operation, a register section including transfer condition registers which are used commonly during the host operation and the peripheral operation, and a buffer controller which controls access to a packet buffer used commonly by the host controller and the peripheral controller. Pipe regions PIPE0 to PIPEe are allocated in the packet buffer during the host operation, and endpoint regions EP0 to EPe are allocated in the packet buffer during the peripheral operation.

Abstract: A data transfer control device includes a DMAC1 that writes a packet transferred from a BUS1 (IEEE 1394 or USB), to a SRAM, a DMAC2 that reads the written isochronous data from the SRAM and writes it to a SDRAM, and a DMAC3 that reads the written isochronous data and transfers it to a BUS2 side. During transmission, isochronous data is read from the SDRAM and written to SRAM, and an isochronous packet including the written isochronous data is transferred to the BUS1 side. The SRAM includes an isochronous data area and an asynchronous data area. The SRAM is provided insides the data transfer control device and the SDRAM is provided on outside the data transfer control device.