Patents by Inventor Nobuyuki Shirai

Nobuyuki Shirai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200230137
    Abstract: The present invention provides a compound having a CaMKII inhibitory action, which is expected to be useful as an agent for the prophylaxis or treatment of cardiac diseases (particularly catecholaminergic polymorphic ventricular tachycardia, postoperative atrial fibrillation, heart failure, fatal arrhythmia) and the like. The present invention relates to a compound represented by the formula (I): wherein each symbol is as defined in the specification, or a salt thereof.
    Type: Application
    Filed: January 27, 2020
    Publication date: July 23, 2020
    Applicant: Cardurion Pharmaceuticals, LLC
    Inventors: Nobuyuki MATSUNAGA, Takashi NAKAHATA, Yuta TANAKA, Hiroki TAKAHAGI, Yasufumi MIYAMOTO, Rei OKAMOTO, Takeshi YOSHIKAWA, Yoshito TERAO, Takafumi YUKAWA, Keiko KAKEGAWA, Yoichi NISHIKAWA, Terufumi TAKAGI, Masashi TAKAHASHI, Mallareddy KOMANDLA, Lily KWOK, Joanne MIURA, Mark SABAT, Nicholas SCORAH, Paul TANIS, John TYHONAS, Phong H. VU, Haixia WANG, Xiaolun WANG, Junya SHIRAI, Tomohiro OKAWA, Zenyu SHIOKAWA, Akito SHIBUYA
  • Publication number: 20200095240
    Abstract: The present invention provides a compound having a CaMKII inhibitory action, which is expected to be useful as an agent for the prophylaxis or treatment of cardiac diseases (particularly catecholaminergic polymorphic ventricular tachycardia, postoperative atrial fibrillation, heart failure, fatal arrhythmia) and the like. The present invention relates to a compound represented by the formula (I): wherein each symbol is as defined in the specification, or a salt thereof.
    Type: Application
    Filed: September 24, 2019
    Publication date: March 26, 2020
    Inventors: Nobuyuki MATSUNAGA, Yasufumi MIYAMOTO, Junya SHIRAI, Takashi NAKAHATA, Zenyu SHIOKAWA, Tomohiro OKAWA, Akito SHIBUYA, Malcolm MacCoss
  • Patent number: 10543212
    Abstract: The present invention provides a compound having a CaMKII inhibitory action, which is expected to be useful as an agent for the prophylaxis or treatment of cardiac diseases (particularly catecholaminergic polymorphic ventricular tachycardia, postoperative atrial fibrillation, heart failure, fatal arrhythmia) and the like. The present invention relates to a compound represented by the formula (I): wherein each symbol is as defined in the specification, or a salt thereof.
    Type: Grant
    Filed: March 23, 2018
    Date of Patent: January 28, 2020
    Assignee: Cardurion Pharmaceuticals, LLC
    Inventors: Nobuyuki Matsunaga, Takashi Nakahata, Yuta Tanaka, Hiroki Takahagi, Yasufumi Miyamoto, Rei Okamoto, Takeshi Yoshikawa, Yoshito Terao, Takafumi Yukawa, Keiko Kakegawa, Yoichi Nishikawa, Terufumi Takagi, Masashi Takahashi, Mallareddy Komandla, Lily Kwok, Joanne Miura, Mark Sabat, Nicholas Scorah, Paul Tanis, John Tyhonas, Phong H. Vu, Haixia Wang, Xiaolun Wang, Junya Shirai, Tomohiro Okawa, Zenyu Shiokawa, Akito Shibuya
  • Publication number: 20190355846
    Abstract: Provided is a method of forming a trench gate MOSFET. A hard mask layer is formed on a substrate. The substrate is partially removed by using the hard mask layer as a mask, so as to form a trench in the substrate. A first insulating layer and a first conductive layer are formed in the lower portion of the trench. A sacrificial layer is formed on the side surface of the upper portion of the trench, and the sacrificial layer is connected to the hard mask layer. An interlayer insulating layer is formed on the first conductive layer by a thermal oxidation process when the sacrificial layer and the hard mask layer are present. A second insulating layer and a second conductive layer are formed in the upper portion of the trench. A trench gate MOSFET is further provided.
    Type: Application
    Filed: May 15, 2019
    Publication date: November 21, 2019
    Applicant: uPI Semiconductor Corp.
    Inventors: Nobuyuki Shirai, Chun-Hsu Chang, Ming-Hung Chou
  • Publication number: 20180366576
    Abstract: A semiconductor device is disclosed. The semiconductor device includes a semiconductor substrate, a gate electrode, a drain electrode and a source electrode. The gate electrode, the drain electrode and the source electrode are formed on the semiconductor substrate. An area of the source electrode is larger than an area of the gate electrode and the area of the drain electrode. A part of the source electrode has a convex shape and disposed between the gate electrode and the drain electrode. The semiconductor device of the invention can maintain various switching characteristics and enable high-speed switching.
    Type: Application
    Filed: June 1, 2018
    Publication date: December 20, 2018
    Inventors: Nobuyuki SHIRAI, Nobuyoshi MATSUURA
  • Patent number: 10074744
    Abstract: A control electrode GE1 is formed in a lower portion of a trench TR1 formed in a semiconductor substrate SUB, and a gate electrode GE2 is formed in an upper portion inside the trench TR1. An insulating film G1 is formed between the control electrode GE1 and a side wall and a bottom surface of the trench TR1, an insulating film G2 is formed between the side wall of the trench TR1 and the gate electrode GE2, and an insulating film G3 is formed between the control electrode GE1 and the gate electrode GE2. A region adjacent to the trench TR1 includes an n+-type semiconductor region NR for a source, a p-type semiconductor region PR for a channel formation, and a semiconductor region for a drain. A wiring connected to the control electrode GE1 is not connected to a wiring connected to the gate electrode GE2, and is not connected to a wiring connected to the n+-type semiconductor region NR for a source.
    Type: Grant
    Filed: June 16, 2017
    Date of Patent: September 11, 2018
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Hideo Numabe, Nobuyuki Shirai, Hirokazu Kato, Tomoaki Uno, Kazuyuki Umezu
  • Publication number: 20170288053
    Abstract: A control electrode GE1 is formed in a lower portion of a trench TR1 formed in a semiconductor substrate SUB, and a gate electrode GE2 is formed in an upper portion inside the trench TR1. An insulating film G1 is formed between the control electrode GE1 and a side wall and a bottom surface of the trench TR1, an insulating film G2 is formed between the side wall of the trench TR1 and the gate electrode GE2, and an insulating film G3 is formed between the control electrode GE1 and the gate electrode GE2. A region adjacent to the trench TR1 includes an n+-type semiconductor region NR for a source, a p-type semiconductor region PR for a channel formation, and a semiconductor region for a drain. A wiring connected to the control electrode GE1 is not connected to a wiring connected to the gate electrode GE2, and is not connected to a wiring connected to the n+-type semiconductor region NR for a source.
    Type: Application
    Filed: June 16, 2017
    Publication date: October 5, 2017
    Inventors: Hideo Numabe, Nobuyuki Shirai, Hirokazu Kato, Tomoaki Uno, Kazuyuki Umezu
  • Patent number: 9711637
    Abstract: A control electrode GE1 is formed in a lower portion of a trench TR1 formed in a semiconductor substrate SUB, and a gate electrode GE2 is formed in an upper portion inside the trench TR1. An insulating film G1 is formed between the control electrode GE1 and a side wall and a bottom surface of the trench TR1, an insulating film G2 is formed between the side wall of the trench TR1 and the gate electrode GE2, and an insulating film G3 is formed between the control electrode GE1 and the gate electrode GE2. A region adjacent to the trench TR1 includes an n+-type semiconductor region NR for a source, a p-type semiconductor region PR for a channel formation, and a semiconductor region for a drain. A wiring connected to the control electrode GE1 is not connected to a wiring connected to the gate electrode GE2, and is not connected to a wiring connected to the n+-type semiconductor region NR for a source.
    Type: Grant
    Filed: January 31, 2014
    Date of Patent: July 18, 2017
    Assignee: Renesas Electronics Corporation
    Inventors: Hideo Numabe, Nobuyuki Shirai, Hirokazu Kato, Tomoaki Uno, Kazuyuki Umezu
  • Publication number: 20160351702
    Abstract: A control electrode GE1 is formed in a lower portion of a trench TR1 formed in a semiconductor substrate SUB, and a gate electrode GE2 is formed in an upper portion inside the trench TR1. An insulating film G1 is formed between the control electrode GE1 and a side wall and a bottom surface of the trench TR1, an insulating film G2 is formed between the side wall of the trench TR1 and the gate electrode GE2, and an insulating film G3 is formed between the control electrode GE1 and the gate electrode GE2. A region adjacent to the trench TR1 includes an n+-type semiconductor region NR for a source, a p-type semiconductor region PR for a channel formation, and a semiconductor region for a drain. A wiring connected to the control electrode GE1 is not connected to a wiring connected to the gate electrode GE2, and is not connected to a wiring connected to the n+-type semiconductor region NR for a source.
    Type: Application
    Filed: January 31, 2014
    Publication date: December 1, 2016
    Inventors: Hideo Numabe, Nobuyuki Shirai, Hirokazu Kato, Tomoaki Uno, Kazuyuki Umezu
  • Patent number: 9449904
    Abstract: A semiconductor device includes a gate electrode GE electrically connected to a gate portion which is made of a polysilicon film provided in the inside of a plurality of grooves formed in a striped form along the direction of T of a chip region CA wherein the gate electrode GE is formed as a film at the same layer level as a source electrode SE electrically connected to a source region formed between adjacent stripe-shaped grooves and the gate electrode GE is constituted of a gate electrode portion G1 formed along a periphery of the chip region CA and a gate finger portion G2 arranged so that the chip region CA is divided into halves along the direction of X. The source electrode SE is constituted of an upper portion and a lower portion, both relative to the gate finger portion G2, and the gate electrode GE and the source electrode SE are connected to a lead frame via a bump electrode.
    Type: Grant
    Filed: October 14, 2014
    Date of Patent: September 20, 2016
    Assignee: Renesas Electronics Corporation
    Inventors: Nobuyuki Shirai, Nobuyoshi Matsuura
  • Patent number: 9099550
    Abstract: A semiconductor device has a MOSFET and a Schottky barrier diode. A source electrode of the MOSFET is disposed over a main surface of the semiconductor substrate and is coupled to a source region in a well region of the semiconductor substrate. The Schottky barrier diode is adjacent to the MOSFET and includes a part of the source electrode and a part of the main surface of the semiconductor substrate.
    Type: Grant
    Filed: October 30, 2014
    Date of Patent: August 4, 2015
    Assignee: Renesas Electronics Corporation
    Inventors: Nobuyuki Shirai, Nobuyoshi Matsuura, Yoshito Nakazawa
  • Publication number: 20150054069
    Abstract: A semiconductor device for use in a power supply circuit has first and second MOSFETS. The source-drain path of one of the MOSFETS are coupled to the source-drain path of the other, and a load element is coupled to a connection node of the source-drain paths. The second MOSFET is formed on a semiconductor substrate with a Schottky barrier diode. First gate electrodes of the second MOSFET are formed in trenches in a first region of the semiconductor substrate, while second gate electrodes of the second MOSFET are formed in trenches in a second region of the semiconductor substrate. The first and second gate electrodes are electrically connected together. Portions of the Schottky barrier diode are formed between adjacent ones of the second gate electrodes. A center-to-center spacing between adjacent first gate electrodes is smaller than a center-to-center spacing between adjacent second gate electrodes.
    Type: Application
    Filed: October 30, 2014
    Publication date: February 26, 2015
    Inventors: Nobuyuki SHIRAI, Nobuyoshi MATSUURA, Yoshito NAKAZAWA
  • Publication number: 20150028400
    Abstract: A semiconductor device includes a gate electrode GE electrically connected to a gate portion which is made of a polysilicon film provided in the inside of a plurality of grooves formed in a striped form along the direction of T of a chip region CA wherein the gate electrode GE is formed as a film at the same layer level as a source electrode SE electrically connected to a source region formed between adjacent stripe-shaped grooves and the gate electrode GE is constituted of a gate electrode portion G1 formed along a periphery of the chip region CA and a gate finger portion G2 arranged so that the chip region CA is divided into halves along the direction of X. The source electrode SE is constituted of an upper portion and a lower portion, both relative to the gate finger portion G2, and the gate electrode GE and the source electrode SE are connected to a lead frame via a bump electrode.
    Type: Application
    Filed: October 14, 2014
    Publication date: January 29, 2015
    Inventors: Nobuyuki Shirai, Nobuyoshi Matsuura
  • Patent number: 8928071
    Abstract: A semiconductor device has a semiconductor substrate with a plurality of transistor cell regions. Each transistor cell region includes a plurality of trenches disposed in the semiconductor substrate, a well region between the plurality of trenches, and a source region of a MOSFET in the well region. A source electrode of the MOSFET is in contact with a top surface of the source region in each of the plurality of transistor cell regions. The source electrode is in contact with a part of a main surface of the semiconductor substrate so as to form a Schottky junction in a Schottky cell region disposed between the plurality of transistor cell regions. The Schottky junction is lower than a portion of the main surface between the Schottky junction and one of the transistor cell regions.
    Type: Grant
    Filed: March 16, 2013
    Date of Patent: January 6, 2015
    Assignee: Renesas Electronics Corporation
    Inventors: Nobuyuki Shirai, Nobuyoshi Matsuura, Yoshito Nakazawa
  • Patent number: 8884361
    Abstract: A semiconductor device which includes a gate electrode electrically connected to a gate portion made of a polysilicon film provided inside of a plurality of grooves formed in a striped form along a direction of a chip region. The gate electrode is formed as a film at the same layer level as a source electrode electrically connected to a source region formed between adjacent stripe-shaped grooves. The gate electrode is constituted of a gate electrode portion formed along a periphery of the chip region and a gate finger portion arranged to divide the chip region into halves. The source electrode is constituted of an upper portion and a lower portion relative to the gate finger portion, and the gate electrode and the source electrode are connected to a lead frame via a bump electrode.
    Type: Grant
    Filed: January 13, 2012
    Date of Patent: November 11, 2014
    Assignee: Renesas Electronics Corporation
    Inventors: Nobuyuki Shirai, Nobuyoshi Matsuura
  • Patent number: 8546223
    Abstract: The characteristics of a semiconductor device including a trench-gate power MISFET are improved. The semiconductor device includes a substrate having an active region where the power MISFET is provided and an outer circumferential region which is located circumferentially outside the active region and where a breakdown resistant structure is provided, a pattern formed of a conductive film provided over the substrate in the outer circumferential region with an insulating film interposed therebetween, another pattern isolated from the pattern, and a gate electrode terminal electrically coupled to the gate electrodes of the power MISFET and provided in a layer over the conductive film. The conductive film of the pattern is electrically coupled to the gate electrode terminal, while the conductive film of another pattern is electrically decoupled from the gate electrode terminal.
    Type: Grant
    Filed: September 23, 2010
    Date of Patent: October 1, 2013
    Assignee: Renesas Electronics Corporation
    Inventors: Hiroki Arai, Nobuyuki Shirai, Tsuyoshi Kachi
  • Patent number: 8536643
    Abstract: A semiconductor device includes a gate electrode GE electrically connected to a gate portion which is made of a polysilicon film provided in the inside of a plurality of grooves formed in a striped form along the direction of T of a chip region CA wherein the gate electrode GE is formed as a film at the same layer level as a source electrode SE electrically connected to a source region formed between adjacent stripe-shaped grooves and the gate electrode GE is constituted of a gate electrode portion G1 formed along a periphery of the chip region CA and a gate finger portion G2 arranged so that the chip region CA is divided into halves along the direction of X. The source electrode SE is constituted of an upper portion and a lower portion, both relative to the gate finger portion G2, and the gate electrode GE and the source electrode SE are connected to a lead frame via a bump electrode.
    Type: Grant
    Filed: February 19, 2010
    Date of Patent: September 17, 2013
    Assignee: Renesas Electronics Corporation
    Inventors: Nobuyuki Shirai, Nobuyoshi Matsuura
  • Patent number: 8426910
    Abstract: A semiconductor device for use in a power supply circuit has first and second MOSFETS. The source-drain path of one of the MOSFETS are coupled to the source-drain path of the other, and a load element is coupled to a connection node of the source-drain paths. The second MOSFET is formed on a semiconductor substrate with a Schottky barrier diode. First gate electrodes of the second MOSFET are formed in trenches in a first region of the semiconductor substrate, while second gate electrodes of the second MOSFET are formed in trenches in a second region of the semiconductor substrate. The first and second gate electrodes are electrically connected together. Portions of the Schottky barrier diode are formed between adjacent ones of the second gate electrodes. A center-to-center spacing between adjacent first gate electrodes is smaller than a center-to-center spacing between adjacent second gate electrodes.
    Type: Grant
    Filed: May 9, 2012
    Date of Patent: April 23, 2013
    Assignee: Renesas Electronics Corporation
    Inventors: Nobuyuki Shirai, Nobuyoshi Matsuura, Yoshito Nakazawa
  • Publication number: 20120280315
    Abstract: A semiconductor device for use in a power supply circuit has first and second MOSFETS. The source-drain path of one of the MOSFETS are coupled to the source-drain path of the other, and a load element is coupled to a connection node of the source-drain paths. The second MOSFET is formed on a semiconductor substrate with a Schottky barrier diode. First gate electrodes of the second MOSFET are formed in trenches in a first region of the semiconductor substrate, while second gate electrodes of the second MOSFET are formed in trenches in a second region of the semiconductor substrate. The first and second gate electrodes are electrically connected together. Portions of the Schottky barrier diode are formed between adjacent ones of the second gate electrodes. A center-to-center spacing between adjacent first gate electrodes is smaller than a center-to-center spacing between adjacent second gate electrodes.
    Type: Application
    Filed: May 9, 2012
    Publication date: November 8, 2012
    Inventors: Nobuyuki SHIRAI, Nobuyoshi MATSUURA, Yoshito NAKAZAWA
  • Publication number: 20120175698
    Abstract: A semiconductor device which includes a gate electrode electrically connected to a gate portion made of a polysilicon film provided inside of a plurality of grooves formed in a striped form along a direction of a chip region. The gate electrode is formed as a film at the same layer level as a source electrode electrically connected to a source region formed between adjacent stripe-shaped grooves. The gate electrode is constituted of a gate electrode portion formed along a periphery of the chip region and a gate finger portion arranged to divide the chip region into halves. The source electrode is constituted of an upper portion and a lower portion relative to the gate finger portion, and the gate electrode and the source electrode are connected to a lead frame via a bump electrode.
    Type: Application
    Filed: January 13, 2012
    Publication date: July 12, 2012
    Inventors: Nobuyuki SHIRAI, Nobuyoshi MATSUURA