Patents by Inventor Nobuyuki Sugii

Nobuyuki Sugii has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20030062537
    Abstract: In a semiconductor multi-layer structure in which a first SiGe layer having a first conductivity-type and high impurity concentration, a second SiGe layer having the first conductivity-type and a low impurity concentration and a Si layer having a low impurity concentration are formed one on another in this order on a Si substrate of the first conductivity-type, a channel is formed in a part of the Si layer and a source electrode passes through the second SiGe layer of low impurity concentration to electrically contact the first SiGe layer of high impurity concentration or the substrate.
    Type: Application
    Filed: September 30, 2002
    Publication date: April 3, 2003
    Inventors: Nobuyuki Sugii, Masatoshi Morikawa, Isao Yoshida, Katsuyoshi Washio
  • Patent number: 6529304
    Abstract: Configurations of a light signal communication apparatus and an optical communication system suitable for speeding-up of the transmission of information based on a light signal and an increase in the capacity for the information transmission are disclosed. On the light signal transmitting side, excitation light is supplied to an active medium in accordance with a transmission signal to cause induced emission within the active medium, thereby generating signal light. The excitation light causes spontaneously-emitted light to fall on a semiconductor layer, and a voltage pulse corresponding to transmission information is applied to modulate the refractive index of the semiconductor layer, thereby Bragg-reflecting a specific wavelength component, after which it is sent to the active medium as the excitation light. The Bragg reflection and induced emission incident to it exhibit excellent response to a voltage signal having a pulse width of 1×10−9 seconds or less.
    Type: Grant
    Filed: September 17, 1999
    Date of Patent: March 4, 2003
    Assignee: Hitachi, Ltd.
    Inventors: Yoshinobu Kimura, Masanobu Miyao, Kiyokazu Nakagawa, Nobuyuki Sugii, Takuya Maruizumi
  • Publication number: 20030013305
    Abstract: A method of producing a strain-relaxed Si—Ge virtual substrate for use in a semiconductor substrate which is planar and of less defects for improving the performance of a field effect semiconductor device, which method comprises covering an Si—Ge layer formed on an SOI substrate with an insulating layer to prevent evaporation of Ge, heating the mixed layer of silicon and germanium at a temperature higher than a solidus curve temperature determined by the germanium content of the Si—Ge layer into a partially melting state, and diffusing germanium to the Si layer on the insulating layer, thereby solidifying the molten Si—Ge layer to obtain a strain-relaxed Si—Ge virtual substrate.
    Type: Application
    Filed: June 7, 2002
    Publication date: January 16, 2003
    Applicant: Hitachi, Ltd.
    Inventors: Nobuyuki Sugii, Shinya Yamaguchi, Katsuyoshi Washio
  • Publication number: 20010048108
    Abstract: At least one of a semiconductor thin-film for forming a picture display portion and a semiconductor thin-film for forming a peripheral circuit portion, which are accumulated on one common insulative substrate, is constructed with a semiconductor thin-film having a plural number of semiconductor crystalline portions formed to be divided and disposed in a matrix-like, and TFTs are provided in the semiconductor thin-film by bringing those semiconductor single crystal portions into active portions thereof. For that purpose, a crystallization accelerating material is adhered at the position of lattice points of a matrix and is treated with heating process, for forming the single crystal portions disposed in the matrix-like manner, so as to form the TFTs on the surface thereof, thereby completing the thin-film semiconductor integrated circuit device.
    Type: Application
    Filed: March 20, 2001
    Publication date: December 6, 2001
    Inventors: Seong-kee Park, Kiyokazu Nakagawa, Nobuyuki Sugii, Shinya Yamaguchi
  • Patent number: 5468806
    Abstract: Disclosed is a method of manufacturing a thin film of an oxide superconductor represented by formula Sr.sub.1-x Nd.sub.x CuO.sub.2 on a substrate. The oxide superconductor has a tetragonal crystal structure, the lattice constant in a-axis falling within a range of between 0.385 nm and 0.410 nm, and the lattice constant in c-axis being an integer number of times as much as a level falling within a range of between 0.310 nm and 0.350 nm. The method includes the steps of forming by epitaxial growth a film of a crystal having lattice constants close to those of the crystal of said oxide superconductor on a substrate, and forming a thin film of the oxide superconductor of a tetragonal crystal structure represented by general formula (I) by a thin film-forming technique.
    Type: Grant
    Filed: December 1, 1994
    Date of Patent: November 21, 1995
    Assignees: The Furukawa Electric Co., Ltd., Hitachi Ltd., Kabushiki Kaisha Toshiba, Central Research Institute of Electric Power Industry, International Superconductivity Technology Center
    Inventors: Kiyoshi Yamamoto, Nobuyuki Sugii, Koichi Kubo, Michiharu Ichikawa, Hisao Yamauchi
  • Patent number: 5446017
    Abstract: A superconductive oxide material having an infinite layer structure and having the following formula:A.sub.p B.sub.q Cu.sub.2 O.sub.4.+-.rwherein A and B are different and each represent an element selected from lanthanoid elements and elements belonging to Groups IA, IIA and IIIA of the Periodic Table, p is between 0.9 and 1.1, q is between 0.9 and 1.1 and r is between 0 and 0.6. The oxide material has a crystal structure belonging to a tetragonal system of P4/mmm and 1-123 having the following lattice parameters:3.8.ANG..ltoreq.a.ltoreq.4.0.ANG.7.6.ANG..ltoreq.c.ltoreq.8.0.ANG.or to an orthorhombic system of Pmmm and I-47 having the following lattice parmeters:3.8.ANG..ltoreq.a.ltoreq.3.95.ANG.3.82.ANG..ltoreq.b.ltoreq.4.0.ANG.7.6.ANG..ltoreq.c.ltoreq.8.0.ANG..
    Type: Grant
    Filed: April 12, 1993
    Date of Patent: August 29, 1995
    Assignees: Central Research Institute of Electric Power Industry, Tohoku Electric Power Co., Inc., International Superconductivity Technology Center
    Inventors: Takeshi Sakurai, Nobuyuki Sugii, Seiji Adachi, Michiharu Ichikawa, Yuji Yaegashi, Hisao Yamauchi, Masahiko Shimada, Hirotsugu Takizawa
  • Patent number: 5376309
    Abstract: Disclosed is a boride material for electronic elements, which is represented by a chemical formula of A.sub.1-x E.sub.x B.sub.12 (where A is Zr of Hf, E is Sc or Y, and 0.1.ltoreq.x.ltoreq.0.9) and the crystal system of which is a cubic one at a temperature not lower than its phase transition temperature and is a hexagonal one at a temperature not higher than its phase transition temperature. The boride material is prepared by mixing oxide powders or sulfate powders of the constitutive elements A and E and a boron powder followed by shaping the powder mixture and then sintering the shaped body.
    Type: Grant
    Filed: September 3, 1993
    Date of Patent: December 27, 1994
    Assignees: International Superconductivity Technology Center, Hokkaido Electric Power Co.
    Inventors: Kazuyuki Hamada, Nobuyuki Sugii, Mitsunobu Wakata, Kohichi Kubo, Kiyotaka Matsuura, Hisao Yamauchi