Patents by Inventor Nobuyuki Sugii

Nobuyuki Sugii has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20100258871
    Abstract: Characteristics of a semiconductor device having a FINFET are improved. The FINFET has: a channel layer arranged in an arch shape on a semiconductor substrate and formed of monocrystalline silicon; a front gate electrode formed on a part of an outside of the channel layer through a front gate insulating film; and a back gate electrode formed so as to be buried inside the channel layer through a back gate insulating film. The back gate electrode arranged inside the arch shape is arranged so as to pass through the front gate electrode.
    Type: Application
    Filed: April 13, 2010
    Publication date: October 14, 2010
    Inventors: Takashi Ishigaki, Ryuta Tsuchiya, Yusuke Morita, Nobuyuki Sugii
  • Publication number: 20100258869
    Abstract: An n well and a p well disposed at a predetermined interval on a main surface of a SOI substrate with a thin BOX layer are formed, and an nMIS formed on the p well has a pair of n-type source/drain regions formed on semiconductor layers stacked on a main surface of the SOI layer at a predetermined distance, a gate insulating film, a gate electrode and sidewalls sandwiched between the pair of n-type source/drain regions. A device isolation is formed between the n well and the p well, and a side edge portion of the device isolation extends toward a gate electrode side more than a side edge portion of the n-type source/drain region (sidewall of the BOX layer).
    Type: Application
    Filed: April 9, 2010
    Publication date: October 14, 2010
    Inventors: Yusuke MORITA, Ryuta Tsuchiya, Takashi Ishigaki, Hiroyuki Yoshimoto, Nobuyuki Sugii, Shinichiro Kimura
  • Patent number: 7812398
    Abstract: A semiconductor device and manufacturing method of the same is provided in which the driving current of a pMOSFET is increased, through a scheme formed easily using an existing silicon process. A pMOSFET is formed with a channel in a <100> direction on a (100) silicon substrate. A compressive stress is applied in a direction perpendicular to the channel by an STI.
    Type: Grant
    Filed: March 9, 2009
    Date of Patent: October 12, 2010
    Assignee: Hitachi, Ltd.
    Inventors: Shinichi Saito, Digh Hisamoto, Yoshinobu Kimura, Nobuyuki Sugii, Ryuta Tsuchiya
  • Publication number: 20090309159
    Abstract: Performance of a semiconductor device having a MIS transistor is improved. A semiconductor device includes: a pair of source/drain regions each formed by stacking a semiconductor layer on a main surface of a silicon substrate; a sidewall insulating film covering each sidewall of the source/drain regions; a gate electrode arranged so as to interpose a gate insulating film on the main surface of the silicon substrate at a position sandwiched by the sidewall insulating films in a plane; and extension regions formed to extend from a portion below and lateral to the gate electrode to a portion below and lateral to each of the source/drain regions, wherein a sidewall of the sidewall insulating film being adjacent to the gate insulating film and the gate electrode has an inclination of a forward tapered shape.
    Type: Application
    Filed: June 9, 2009
    Publication date: December 17, 2009
    Inventors: Yusuke MORITA, Ryuta TSUCHIYA, Takashi ISHIGAKI, Nobuyuki SUGII, Shinichiro KIMURA
  • Publication number: 20090283839
    Abstract: In order to provide a semiconductor device having a field effect transistor with a low power consumption and a high speed by use of the combination of Si and an element such as Ge, C or the like of the same group as Si, a strain is applied by a strain applying semiconductor layer 2 to a channel forming layer I having a channel of the field effect transistor formed therein so that the mobility of carriers in the channel is made larger than the mobility of carriers in that material of the channel forming layer which is unstrained.
    Type: Application
    Filed: July 20, 2009
    Publication date: November 19, 2009
    Applicant: RENESAS TECHNOLOGY CORP.
    Inventors: Nobuyuki SUGII, Kiyokazu NAKAGAWA, Shinya YAMAGUCHI, Masanobu MIYAO
  • Publication number: 20090261412
    Abstract: A semiconductor device and manufacturing method of the same is provided in which the driving current of a pMOSFET is increased, through a scheme formed easily using an existing silicon process. A pMOSFET is formed with a channel in a <100> direction on a (100) silicon substrate. A compressive stress is applied in a direction perpendicular to the channel by an STI.
    Type: Application
    Filed: March 9, 2009
    Publication date: October 22, 2009
    Inventors: Shinichi SAITO, Digh Hisamoto, Yoshinobu KIMURA, Nobuyuki SUGII, Ryuta TSUCHIYA
  • Patent number: 7579229
    Abstract: In order to provide a semiconductor device having a field effect transistor with a low power consumption and a high speed by use of the combination of Si and an element such as Ge, C or the like of the same group as Si, a strain is applied by a strain applying semiconductor layer 2 to a channel forming layer I having a channel of the field effect transistor formed therein so that the mobility of carriers in the channel is made larger than the mobility of carriers in that material of the channel forming layer which is unstrained.
    Type: Grant
    Filed: January 22, 2008
    Date of Patent: August 25, 2009
    Assignee: Renesas Technology Corp.
    Inventors: Nobuyuki Sugii, Kiyokazu Nakagawa, Shinya Yamaguchi, Masanobu Miyao
  • Publication number: 20090132974
    Abstract: Capacity-gate voltage characteristics of a field-effect transistor having plural gates are measured against a voltage change in each one of the gates for an inverted MOSFET and for an accumulated MOSFET, respectively. These measurements together with numerical simulations provided from a model for quantum effects are used to determine flat band voltages between the plural gates and a channel. Next, an effective normal electric field is calculated as a vector line integral by using a set of flat band voltages for the measured capacity as a lower integration limit. Lastly, mobility depending on the effective normal electric field is calculated from current-gate voltage characteristic measurements and capacity measurements in a source-drain path, and the calculated mobility is substituted into an equation for a current-voltage curve between source and drain.
    Type: Application
    Filed: January 31, 2008
    Publication date: May 21, 2009
    Inventors: Hiroyuki YOSHIMOTO, Nobuyuki Sugii, Shinichi Saito, Digh Hisamoto
  • Patent number: 7531853
    Abstract: A semiconductor device and manufacturing method of the same is provided in which the driving current of a pMOSFET is increased, through a scheme formed easily using an existing silicon process. A pMOSFET is formed with a channel in a <100> direction on a (100) silicon substrate. A compressive stress is applied in a direction perpendicular to the channel by an STI.
    Type: Grant
    Filed: May 9, 2007
    Date of Patent: May 12, 2009
    Assignee: Hitachi, Ltd.
    Inventors: Shinichi Saito, Digh Hisamoto, Yoshinobu Kimura, Nobuyuki Sugii, Ryuta Tsuchiya
  • Publication number: 20090096036
    Abstract: There is provided an SOI-MISFET including: an SOI layer; a gate electrode provided on the SOI layer interposing a gate insulator; and a first elevated layer provided higher in height from the SOI layer than the gate electrode at both sidewall sides of the gate electrode on the SOI layer so as to constitute a source and drain. Further, there is also provided a bulk-MISFET including: a gate electrode provided on a silicon substrate interposing a gate insulator thicker than the gate insulator of the SOI MISFET; and a second elevated layer configuring a source and drain provided on a semiconductor substrate at both sidewalls of the gate electrode. A the first elevated layer is thicker than the elevated layer, and the whole of the gate electrodes, part of the source and drain of the SOI-MISFET, and part of the source and drain of the bulk-MISFET are silicided.
    Type: Application
    Filed: October 9, 2008
    Publication date: April 16, 2009
    Inventors: Takashi ISHIGAKI, Ryuta Tsuchiya, Yusuke Morita, Nobuyuki Sugii, Shinichiro Kimura, Toshiaki Iwamatsu
  • Publication number: 20090045470
    Abstract: Provided is a technology capable of suppressing a reduction in electron mobility in a channel region formed in a strained silicon layer. A p type strained silicon layer is formed over a p type silicon-germanium layer formed over a semiconductor substrate. The p type strained layer has a thickness adjusted to be thicker than the critical film thickness at which no misfit dislocation occurs. Accordingly, misfit dislocations occur in the vicinity of the interface between the p type strained silicon layer and p type silicon-germanium layer. At a position which is below the end of a gate electrode and at which misfit dislocations occur, the impurity concentration of the n type strained silicon layer and n type silicon-germanium layer is 1×1019 cm?3 or less.
    Type: Application
    Filed: October 14, 2008
    Publication date: February 19, 2009
    Inventors: Masao KONDO, Nobuyuki SUGII, Yoshinobu KIMURA
  • Publication number: 20080258218
    Abstract: A MIS transistor having an inclined stacked source/drain structure increased in speed is provided. The MIS transistor comprises: a gate electrode formed on a substrate; a first sidewall insulating film formed on the substrate and along a sidewall of the gate electrode; source/drain semiconductor regions formed on a main surface of the substrate and respectively having one edge positioned under the sidewall of the gate electrode; a first stacked layer formed on the source/drain semiconductor regions and in contact with the first sidewall insulating film; a second sidewall insulating film formed on the stacked layer and in contact with the first sidewall insulating film; and a second stacked layer formed on the first stacked layer and in contact with the second sidewall insulating layer.
    Type: Application
    Filed: April 17, 2008
    Publication date: October 23, 2008
    Inventors: Yusuke Morita, Yoshinobu Kimura, Ryuta Tsuchiya, Nobuyuki Sugii, Shinichiro Kimura
  • Patent number: 7436046
    Abstract: Provided is a technology capable of suppressing a reduction in electron mobility in a channel region formed in a strained silicon layer. A p type strained silicon layer is formed over a p type silicon-germanium layer formed over a semiconductor substrate. The p type strained layer has a thickness adjusted to be thicker than the critical film thickness at which no misfit dislocation occurs. Accordingly, misfit dislocations occur in the vicinity of the interface between the p type strained silicon layer and p type silicon-germanium layer. At a position which is below the end of a gate electrode and at which misfit dislocations occur, the impurity concentration of the n type strained silicon layer and n type silicon-germanium layer is 1×1019 cm?3 or less.
    Type: Grant
    Filed: October 5, 2005
    Date of Patent: October 14, 2008
    Assignee: Renesas Technology Corp.
    Inventors: Masao Kondo, Nobuyuki Sugii, Yoshinobu Kimura
  • Publication number: 20080206961
    Abstract: In order to provide a semiconductor device having a field effect transistor with a low power consumption and a high speed by use of the combination of Si and an element such as Ge, C or the like of the same group as Si, a strain is applied by a strain applying semiconductor layer 2 to a channel forming layer I having a channel of the field effect transistor formed therein so that the mobility of carriers in the channel is made larger than the mobility of carriers in that material of the channel forming layer which is unstrained.
    Type: Application
    Filed: January 22, 2008
    Publication date: August 28, 2008
    Inventors: Nobuyuki Sugii, Kiyokazu Nakagawa, Shinya Yamaguchi, Masanobu Miyao
  • Publication number: 20080203403
    Abstract: The semiconductor integrated circuit (1) has a memory (4) and a logic circuit (5), which are mixedly palletized on a silicon substrate (2). The memory includes a partially-depleted type nMOS (6) having an SOI structure and formed on UTB (3). The partially-depleted type nMOS has a backgate region (14) under UTB, to which a voltage can be applied independently of a corresponding gate terminal. The logic circuit includes an nMOS (7) and a pMOS (8), and both are of a fully-depleted type, formed on UTB and have an SOI structure.
    Type: Application
    Filed: December 19, 2007
    Publication date: August 28, 2008
    Inventors: Takayuki Kawahara, Masanao Yamaoka, Nobuyuki Sugii
  • Publication number: 20080128863
    Abstract: Gases for film formation are introduced from a plurality of holes provided at a gas nozzle into a processing chamber of a batch-type CVD film-forming apparatus to cause a turbulence of the gases within the processing chamber. In the state where the chamber is kept at a pressure within an atmospheric and quasi-atmospheric pressure region, a silicon-germanium film is epitaxially grown on a semiconductor wafer placed within the processing chamber. Subsequently, a strained silicon film is epitaxially grown on the silicon-germanium film. Thereafter, a semiconductor element is formed in the semiconductor wafer on which the silicon-germanium film and the strained silicon film have been formed, respectively.
    Type: Application
    Filed: January 3, 2008
    Publication date: June 5, 2008
    Inventors: Yasuichi KONDO, Wataru Hirasawa, Nobuyuki Sugii
  • Publication number: 20080111134
    Abstract: To provide TFT of improved low-temperature polycrystalline layer that has higher electron mobility and assures less fluctuation in manufacture in view of realizing a liquid-crystal display device having a large display area by utilizing a glass substrate. A TFT having higher electron mobility can be realized within the predetermined range of characteristic fluctuation by utilizing the semiconductor thin-film (called quasi single crystal thin-film) formed of poly-crystal grain joined with the {111} twin-boundary of Diamond structure as the channel region (namely, active region) of TFT.
    Type: Application
    Filed: January 4, 2008
    Publication date: May 15, 2008
    Inventors: Shinya Yamaguchi, Masanobu Miyao, Nobuyuki Sugii, Seang-kee Park, Kiyokazu Nakagawa
  • Patent number: 7317207
    Abstract: To provide TFT of improved low-temperature polycrystalline layer that has higher electron mobility and assures less fluctuation in manufacture in view of realizing a liquid-crystal display device having a large display area by utilizing a glass substrate. A TFT having higher electron mobility can be realized within the predetermined range of characteristic fluctuation by utilizing the semiconductor thin-film (called quasi single crystal thin-film) formed of poly-crystal grain joined with the {111} twin-boundary of Diamond structure as the channel region (namely, active region) of TFT.
    Type: Grant
    Filed: June 7, 2005
    Date of Patent: January 8, 2008
    Assignee: Hitachi, Ltd.
    Inventors: Shinya Yamaguchi, Masanobu Miyao, Nobuyuki Sugii, Seang-kee Park, Kiyokazu Nakagawa
  • Publication number: 20070290264
    Abstract: The invention aims at increasing an effect of a strain applying technique for enhancing transistor performance in a fully depleted silicon-on-insulator (FDSOI) type transistor having a thin buried oxide (BOX) film. In an FDSOI type transistor having a very thin SOI structure (6), a stress generating region is formed on a back face side (5) of a very thin BOX layer (4) in order to apply strains to portions in which channels are intended to be formed. Desired portions on a back face side of the BOX layer (4) are amorphized by performing ion implantation, and are then recrystallized by performing a heat treatment in a state where a stress applying film (3) is formed, thereby transferring stresses from the stress applying film (3) to the portions in which the channels are intended to be formed. Thus, the stress generating region is formed.
    Type: Application
    Filed: February 13, 2007
    Publication date: December 20, 2007
    Inventors: Nobuyuki Sugii, Ryuta Tsuchiya, Yusuke Morita
  • Publication number: 20070284582
    Abstract: A semiconductor device and manufacturing method of the same is provided in which the driving current of a PMOSFET is increased, through a scheme formed easily using an existing silicon process. A PMOSFET is formed with a channel in a <100> direction on a (100) silicon substrate. A compressive stress is applied in a direction perpendicular to the channel by an STI.
    Type: Application
    Filed: May 9, 2007
    Publication date: December 13, 2007
    Inventors: SHINICHI SAITO, Digh Hisamoto, Yoshinobu Kimura, Nobuyuki Sugii, Ryuta Tsuchiya