Abstract: A semiconductor integrated circuit device has an open-drain-type output circuit in which an N-channel transistor has its source connected to a reference potential point and has its drain connected to an output terminal. The drain of the N-channel transistor is connected to the source of a P-channel transistor. The P-channel transistor has its source and gate connected together through a resistor, and has its drain connected to the reference potential point.

Abstract: A semiconductor integrated circuit device has a semiconductor chip, on which are formed a plurality of input/output circuits and input/output pads individually connected electrically thereto. The input/output pads are connected electrically to a plurality of inner leads formed on the frame on which the semiconductor chip is mounted. The input/output circuits are arranged in two rows along each edge of the semiconductor chip, with the first row of input/output circuits arranged closer to the edge than the second row of input/output circuits. The input/output pads connected to the first-row input/output circuits are arranged in two rows in such a way that the first and second rows of input/output pads sandwich the first row of input/output circuits. The input/output pads connected to the second-row input/output circuits are arranged to form a third row of input/output pads along the second row of input/output circuits.

Abstract: A semiconductor integrated circuit device has a plurality of types of power supply systems. In a corner area of a semiconductor integrated circuit chip, a diode region is formed that consists of a P region and an N region. On this diode region, a power-source line and a ground line are laid so that these lines and the diode region are coupled with a first wiring layer between them and thereby a static protection diode is added to the power supply systems.

Abstract: A semiconductor integrated circuit device has macrocells composed of CMOS transistors. In a first wiring layer of the macrocells, a power source line coupled to the sources of P-channel MOS transistors and a ground line coupled to the sources of N-channel MOS tranistors are formed so as to extend in a first direction. In a second wiring layer of the macrocells, a power supply line connected to the power source line, a ground voltage supply line connected to the ground line, a first bias line for feeding a bias to the N well for the P-channel MOS transistors, and a second bias line for feeding a bias to a semiconductor substrate are formed recurrently so as to extend-in a second direction perpendicular to the first direction.

Abstract: In a C-MOS type output circuit, desired connections between a P-MOS transistor and an N-MOS transistor are achieved without forming a third wiring layer.

Abstract: A semiconductor device is provided with a protection circuit, between a terminal and an input/output circuit of the semiconductor device, that protects the input/output circuit and an internal circuit of the semiconductor device against application of a high voltage due to static electricity. Protection is achieved by short-circuiting the terminal via a resistor with a power source voltage line or a reference potential line when a voltage exceeding a predetermined value is applied to the terminal.

Abstract: A CMOS integrated circuit apparatus has CMOS transistors having an LDD structure. A MOS transistor of a single drain structure for withstanding voltage and a jumper diode for withstanding voltage and latch up prevention are formed in parallel with each other between a power terminal and a ground terminal of the CMOS integrated circuit apparatus.