Abstract: An oscillation sieve, including a screen; an oscillator oscillating the screen to sieve a material; a feeder feeding the material onto the screen; a collector collecting the material having passed the screen; a remover removing the material not having passed the screen therefrom; a guide member fixed on the screen, guiding the material fed from the feeder and not having passed the screen to the remover, wherein the guide member is spiral member formed of an elastic material capable of following the oscillating screen.

Abstract: An oscillation sieve, including a screen; an oscillator oscillating the screen to sieve a material; a feeder feeding the material onto the screen; a collector collecting the material having passed the screen; a remover removing the material not having passed the screen therefrom; a guide member fixed on the screen, guiding the material fed from the feeder and not having passed the screen to the remover, wherein the guide member is spiral member formed of an elastic material capable of following the oscillating screen.

Abstract: A non-volatile semiconductor memory device having a memory cell in which operating potentials are few and the scale of the peripheral circuitry is reduced includes a select transistor having a source/drain on both sides of a channel of a semiconductor substrate and having a gate electrode disposed on the channel via a thick gate insulating film; an element isolation region formed on the semiconductor substrate in an area adjacent to the select transistor; an antifuse adjacent to the element isolation region, having a lower electrode formed on the semiconductor substrate and having an upper electrode disposed on the semiconductor substrate in an area between the element isolation region and lower electrode via a thin gate insulating film; and a connection contact electrically connecting the source and upper electrode and contacting the source and the upper electrode.

Abstract: A semiconductor memory device includes a first anti-fuse element and a second anti-fuse element, respectively composed of a transistor, wherein the first anti-fuse element and the second anti-fuse element are configured so as to be concomitantly programmable, respectively formed in P-wells on a substrate, and the adjacent P-wells are isolated by N-wells of an opposite conductivity type, formed therebetween.

Abstract: A plasma processing apparatus that enables formation of a deposit film on a surface of a grounding electrode to be prevented. A substrate processing chamber has therein a processing space in which plasma processing is carried out on a substrate, an RF electrode that applies radio frequency electrical power into the processing space, a DC electrode that applies a DC voltage into the processing space, and a grounding electrode at least part of which is exposed in the substrate processing chamber. The grounding electrode is disposed in a corner portion formed through intersection of a plurality of internal surfaces in the substrate processing chamber.

Abstract: According to the present invention, a gettering layer is deposited both on the side surfaces and the bottom surface of a semiconductor chip. The semiconductor chip is then mounted on the board of a package so that a Schottky barrier is formed on the bottom surface. With this structure, metal ions that pass through the board of the package can be captured by the defect layer deposited on the side surfaces and/or the bottom surface of the semiconductor chip, and by the Schottky barrier.

Abstract: A plasma processing apparatus includes a processing vessel capable of being vacuum evacuated; a first electrode disposed in the processing vessel in a state electrically floating via an insulating member or a space; a second electrode, arranged in the processing vessel to face and be in parallel to the first electrode with a specific interval, supporting a substrate to be processed; a processing gas supply unit for supplying a desired processing gas into a processing space surrounded by the first electrode, the second electrode and a sidewall of the processing vessel; and a first radio frequency power supply unit for applying a first radio frequency power to the second electrode to generate a plasma of the processing gas in the processing space. An electrostatic capacitance between the first electrode and the processing vessel is set such that a desired plasma density distribution is obtained for the generated plasma.

Abstract: A non-volatile semiconductor memory device having a memory cell in which operating potentials are few and the scale of the peripheral circuitry is reduced includes a select transistor having a source/drain on both sides of a channel of a semiconductor substrate and having a gate electrode disposed on the channel via a thick gate insulating film; an element isolation region formed on the semiconductor substrate in an area adjacent to the select transistor; an antifuse adjacent to the element isolation region, having a lower electrode formed on the semiconductor substrate and having an upper electrode disposed on the semiconductor substrate in an area between the element isolation region and lower electrode via a thin gate insulating film; and a connection contact electrically connecting the source and upper electrode and contacting the source and the upper electrode.

Abstract: A semiconductor memory device includes a first anti-fuse element and a second anti-fuse element, respectively composed of a transistor, wherein the first anti-fuse element and the second anti-fuse element are configured so as to be concomitantly programmable, respectively formed in P-wells on a substrate, and the adjacent P-wells are isolated by N-wells of an opposite conductivity type, formed therebetween.

Abstract: According to the present invention, a gettering layer is deposited both on the side surfaces and the bottom surface of a semiconductor chip. The semiconductor chip is then mounted on the board of a package so that a Schottky barrier is formed on the bottom surface. With this structure, metal ions that pass through the board of the package can be captured by the defect layer deposited on the side surfaces and/or the bottom surface of the semiconductor chip, and by the Schottky barrier.

Abstract: Obtained is a highly-reliable non-volatile memory without increasing the area of a memory cell or adding a step to a CMOS process. The non-volatile memory includes an SRAM cell configured of 6 MOS transistors, a first word line electrically connected to the gate of a first transfer MOS transistor, and a second word line electrically connected to the gate of a second transfer MOS transistor. During a write operation of a first PMOS transistor, a drive circuit applies a positive voltage whose absolute value is not larger than a junction breakdown voltage to an n-type well as well as the sources of first and second PMOS transistors, concurrently applying the positive voltage to the first word line and a ground voltage to the second word line and a first data line.

Abstract: A non-volatile semiconductor memory device having a memory cell in which operating potentials are few and the scale of the peripheral circuitry is reduced includes a select transistor having a source/drain on both sides of a channel of a semiconductor substrate and having a gate electrode disposed on the channel via a thick gate insulating film; an element isolation region formed on the semiconductor substrate in an area adjacent to the select transistor; an antifuse adjacent to the element isolation region, having a lower electrode formed on the semiconductor substrate and having an upper electrode disposed on the semiconductor substrate in an area between the element isolation region and lower electrode via a thin gate insulating film; and a connection contact electrically connecting the source and upper electrode and contacting the source and the upper electrode.

Abstract: A nonvolatile semiconductor memory device is provided in which stable transistor characteristics with little variation can be obtained, and sufficient threshold voltage and ON current fluctuations can be obtained. A source 2 and a drain 3 formed on a surface of a semiconductor substrate 1, and a gate electrode 5 formed via a gate insulating film 4 on the semiconductor substrate 1 between the source 2 and the drain 3 are provided, and a region of part of the gate electrode 5 forms a non-doped region 10 in which an impurity is not implanted in polysilicon, and another region of the gate electrode 5 forms a doped region 9 in which an impurity is implanted in the polysilicon.

Abstract: The number of process steps for manufacturing a non-volatile memory is reduced while the performance of the non-volatile memory is improved. The non-volatile memory has a memory cell in which first, second and third P-type diffusion regions are formed in an N-type well, a select gate is formed via a select-gate insulating film over a channel between the first and second P-type diffusion regions, and a floating gate is formed via a floating-gate insulating film over a channel between the second and third P-type diffusion regions. The non-volatile memory has a peripheral circuit in which fourth and fifth P-type diffusion regions are formed in an N-type well, and a peripheral-circuit gate is formed via a peripheral-circuit gate insulating film over a channel between the fourth and fifth P-type diffusion regions. The film thickness of the floating-gate insulating film is greater than that of the select-gate insulating film and peripheral-circuit gate insulating film.

Abstract: According to the present invention, a gettering layer is deposited both on the side surfaces and the bottom surface of a semiconductor chip. The semiconductor chip is then mounted on the board of a package so that a Schottky barrier is formed on the bottom surface. With this structure, metal ions that pass through the board of the package can be captured by the defect layer deposited on the side surfaces and/or the bottom surface of the semiconductor chip, and by the Schottky barrier.

Abstract: Obtained is a highly-reliable non-volatile memory without increasing the area of a memory cell or adding a step to a CMOS process. The non-volatile memory includes an SRAM cell configured of 6 MOS transistors, a first word line electrically connected to the gate of a first transfer MOS transistor, and a second word line electrically connected to the gate of a second transfer MOS transistor. During a write operation of a first PMOS transistor, a drive circuit applies a positive voltage whose absolute value is not larger than a junction breakdown voltage to an n-type well as well as the sources of first and second PMOS transistors, concurrently applying the positive voltage to the first word line and a ground voltage to the second word line and a first data line.

Abstract: A semiconductor memory device for reliably inducing a breakdown in the dielectric when utilizing an antifuse to write on the dielectric film even when the process scale has become more detailed. The semiconductor memory device includes an antifuse serving as the memory node, and a current regulator connected in serial with the antifuse. The current controller is comprised of a P-type semiconductor substrate and a reverse-conduction N-type well, a diode coupled to a P+ diffusion substrate of the same conducing type as the P-type semiconductor substrate. The antifuse contains at least a structure where an electrode is formed via a dielectric film on the reverse-conducting N+ diffusion layer and the P-type semiconductor substrate. The N+ diffusion layer is connected to the N-type well of diode, and the diode regulates the current.

Abstract: According to the present invention, a gettering layer is deposited both on the side surfaces and the bottom surface of a semiconductor chip. The semiconductor chip is then mounted on the board of a package so that a Schottky barrier is formed on the bottom surface. With this structure, metal ions that pass through the board of the package can be captured by the defect layer deposited on the side surfaces and/or the bottom surface of the semiconductor chip, and by the Schottky barrier.

Abstract: A plasma processing apparatus that enables formation of a deposit film on a surface of a grounding electrode to be prevented. A substrate processing chamber has therein a processing space in which plasma processing is carried out on a substrate, an RF electrode that applies radio frequency electrical power into the processing space, a DC electrode that applies a DC voltage into the processing space, and a grounding electrode at least part of which is exposed in the substrate processing chamber. The grounding electrode is disposed in a corner portion formed through intersection of a plurality of internal surfaces in the substrate processing chamber.

Abstract: A plasma processing apparatus includes a processing vessel capable of being vacuum evacuated; a first electrode disposed in the processing vessel in a state electrically floating via an insulating member or a space; a second electrode, arranged in the processing vessel to face and be in parallel to the first electrode with a specific interval, supporting a substrate to be processed; a processing gas supply unit for supplying a desired processing gas into a processing space surrounded by the first electrode, the second electrode and a sidewall of the processing vessel; and a first radio frequency power supply unit for applying a first radio frequency power to the second electrode to generate a plasma of the processing gas in the processing space. An electrostatic capacitance between the first electrode and the processing vessel is set such that a desired plasma density distribution is obtained for the generated plasma.