Abstract: A plasma processing apparatus includes a processing vessel capable of being vacuum evacuated; a first electrode installed in the processing vessel to be in a state electrically floating via an insulating member or a space; a second electrode disposed in the processing vessel to be in parallel to the first electrode with a specific interval, for supporting a target substrate thereon to face the first electrode; a processing gas supply unit for supplying a processing gas into a processing space between the first electrode, the second electrode and a sidewall of the processing vessel; and a first radio frequency power supply unit for applying a first radio frequency power to the second electrode to generate a plasma of the processing gas in the processing space. A protrusion projected toward the second electrode is formed at a central portion of the first electrode.

Abstract: A nonvolatile semiconductor memory device includes a substrate, a central structure, a second gate insulating film, a floating gate, and a control gate. The substrate has a trench. The central structure is formed so as to be embedded in the trench and protruded from the substrate. The second gate insulating film is formed on the substrate so as to be contact with the central structure. The floating gate is formed on the second gate insulating film. The control gate is formed so as to cover the floating gate through a insulating film;. The central structure includes an assistant gate and a first gate insulating film which is formed such that the assistance gate is surrounded with the first gate insulating film. The floating gate is formed in a side wall shape on the side surface of the central structure.

Abstract: A nonvolatile semiconductor storage device includes a plurality of memory cells, each including a drain formed above a substrate, a source formed at a bottom of a groove in the substrate, a floating gate formed above the substrate between the drain and a side surface of the groove, and a control gate formed above the floating gate. The groove is shared by adjacent memory cells. The side surface of the groove is substantially aligned with a side end of the floating gate. The groove is filled with an insulating film.

Abstract: According to the present invention, a gettering layer is deposited both on the side surfaces and the bottom surface of a semiconductor chip. The semiconductor chip is then mounted on the board of a package so that a Schottky barrier is formed on the bottom surface. With this structure, metal ions that pass through the board of the package can be captured by the defect layer deposited on the side surfaces and/or the bottom surface of the semiconductor chip, and by the Schottky barrier.

Abstract: A nonvolatile memory device includes source and drain regions formed in a semiconductor substrate, and an insulating film formed on a channel region between the source region and the drain region in the semiconductor substrate. The nonvolatile memory device also includes a dielectric film formed above the channel region to store electric charge, and a control gate formed on the dielectric film. Compressive stress in the channel region is equal to or less than 50 MPa.

Abstract: A nonvolatile semiconductor memory device includes a substrate, a central structure, a second gate insulating film, a floating gate, and a control gate. The substrate has a trench. The central structure is formed so as to be embedded in the trench and protruded from the substrate. The second gate insulating film is formed on the substrate so as to be contact with the central structure. The floating gate is formed on the second gate insulating film. The control gate is formed so as to cover the floating gate through a insulating film;. The central structure includes an assistant gate and a first gate insulating film which is formed such that the assistance gate is surrounded with the first gate insulating film. The floating gate is formed in a side wall shape on the side surface of the central structure.

Abstract: According to the present invention, a gettering layer is deposited both on the side surfaces and the bottom surface of a semiconductor chip. The semiconductor chip is then mounted on the board of a package so that a Schottky barrier is formed on the bottom surface. With this structure, metal ions that pass through the board of the package can be captured by the defect layer deposited on the side surfaces and/or the bottom surface of the semiconductor chip, and by the Schottky barrier.

Abstract: A nonvolatile memory device includes source and drain regions formed in a semiconductor substrate, and an insulating film formed on a channel region between the source region and the drain region in the semiconductor substrate. The nonvolatile memory device also includes a dielectric film formed above the channel region to store electric charge, and a control gate formed on the dielectric film. Compressive stress in the channel region is equal to or less than 50 MPa.

Abstract: The present invention provides a dry air supply device for supplying, into a target space, dry air from which moisture and organic materials have been removed, the device comprising: a plurality of rotors disposed in series, each of which is configured to carry an adsorbent thereon and is rotatably supported; partition members which are arranged at outermost end portions of the rotors and between the rotors so as to partition a rotary zone of each rotor into an adsorption zone, a regeneration zone and a cooling zone; a driving member which rotatably drives the rotors; a supply passage which allows sucked air to pass through the adsorption zone to obtain dry air from which moisture and organic materials have been removed, and which supplies the dry air into the target space; and an exhaust passage which allows a portion of the dry air to pass through the cooling zone, then heats the cooled air, and then allows the heated air to pass through the regeneration zone to separate the moisture and the organic materia

Abstract: According to the present invention, a method for manufacturing a nonvolatile semiconductor storage device is provided in which an element separating layer and first gate insulating layer are respectively formed onto a silicon base, followed by layering and patterning of a first polysilicon layer. A second gate insulating layer for forming an ONO structure and a second polysilicon layer are then sequentially formed and patterned. After formation of a gate oxide layer, a third polysilicon layer is layered and patterned to form a gate electrode. The second and first polysilicon layers are then patterned to respectively form control gate and floating gate.

Abstract: There is provided a non-volatile semiconductor memory device, including (a) a first gate insulating film formed on a channel region of a semiconductor substrate, (b) a floating gate electrode formed on the first gate insulating film, (c) a second gate insulating film formed on the floating gate electrode, (d) a control gate electrode formed on the second gate insulating film, and (e) an electric power source applying a gradually increasing voltage across the control gate electrode and the semiconductor substrate, the electric power source varying both an increment by which the voltage is increased and a period of time during which the voltage is kept constant, while data is being rewritten. The non-volatile semiconductor memory device is capable of increasing a rate at which data stored therein is deleted, without deleting data more than necessary.

Abstract: A plurality of memory cells are arranged in lattice arrangement to form a memory cell array. Each of the memory cells is provided with a source. Data in the memory cell can be electrically written and erased. Sources of all the memory cells are connected in common. Also, a source voltage control circuit having two or more kinds of load characteristics is connected to the sources connected in common. According to a load characteristics selected from a plurality of load characteristics, source voltage of the memory cell is controlled.

Abstract: In a memory cell including a floating gate, a gate insulation film and a control gate, after removing injected charges from the floating gate with tunneling currents through the gate insulation film, charges are removed from the gate insulation film by applying a pair of positive and negative voltage pulses to the control gate at least one time.

Abstract: A nonvolatile semiconductor memory includes a cell array prepared by arranging erasable and programmable memory cell transistors in rows and columns, word lines arranged in correspondence with the respective rows of the cell array and connected to the control gates of the memory cell transistors, digit lines arranged in correspondence with the respective columns of the cell array and connected to the drains of the memory cell transistors, source lines connected to the sources of the memory cell transistors, and a source power supply circuit for applying a source voltage to the source lines in an erase operation. This memory erases by the source voltage data in the memory cell transistors in the rows and columns of the cell array.

Abstract: In a nonvolatile semiconductor device having a floating gate formed over a semiconductor substrate, a control gate formed over the floating gate, a source region and a drain region formed within the semiconductor substrate, an erase or write operation is carried out by Fowler-Nordheim tunneling, so that carriers such as electrons and holes are expelled from the floating gate to one of the source and drain regions. Thereafter, carriers of a channel current flowing between the source and drain regions are enhanced and injected into the floating gate, thus converging a threshold voltage of the device.

Abstract: There is provided an involatile semiconductor memory deice comprising a virtual ground memory cell array which allows the read current to be increased without degrading the writing characteristic. A source/drain of a memory cell having a floating gate 3 is composed of a double diffusion layer comprising an n.sup.- -type diffusion layer 7 and an n.sup.+ -type diffusion layer 8, the n.sup.+ -type diffusion layer 8 overlaps with one end of the floating gate 3 and the other is provided with an offset of the n.sup.- -type diffusion layer 7.

Abstract: Data bits stored in a flash EEPROM are erased by biasing n-type source regions of floating gate type field effect transistors such that accumulated electrons are evacuated as Fowler-Nordheim tunneling current, and, the p-type semiconductor substrate, the n-type source regions and the control gate electrodes are, thereafter, biased to a negative voltage level, a first positive voltage level and a second positive voltage level for injecting hot electrons into the floating gate electrode depending upon the amount of residual electrons in each floating gate electrode, thereby self-calibrating the threshold level of the floating gate type field effect transistors.

Abstract: In a process of fabricating a floating gate type field effect transistor, an ion implantation for forming a drain region is repeated more than twice at different angles, and the drain region has an impurity profile gently changed by virtue of the ion implantation at the different angles so that a drain disturbe is effectively suppressed, thereby improving the stability of the data bit stored in the floating gate type field effect transistor.

Abstract: A method for erasing data stored in a non-volatile semiconductor memory is applied to a memory cell transistor including a p-type well region, a source and a drain formed within the p-type well region, and a composite gate including a floating gate electrode formed on the p-type well region. In the method, a plurality of pulses having a high positive voltage is applied to the p-type well region so that a product (I.times.N) of a pulse interval (I) and a number of the plurality of pulses (N) becomes not smaller than 0.1 s on condition that the control gate electrode is fixed to the ground level and the source and drain are kept at a floating state.

Abstract: A semiconductor non-volatile memory device with a memory cell has a memory transistor formed on a semiconductor substrate and a select transistor composed of a thin film transistor provided on an upper surface of the memory transistor and connected in series with the memory transistor. The space occupied by the memory cell is that of one transistor whereby the size of the overall memory cell can be made smaller.