Patents by Inventor Noriaki Sakamoto

Noriaki Sakamoto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7936569
    Abstract: In a hybrid integrated circuit device that is a circuit device of the present invention, a conductive pattern including pads is formed on a surface of a substrate. A first pad is formed to be relatively large since a heat sink is mounted thereon. A second pad is a small pad to which a chip component or a small signal transistor is fixed. In the present invention, a plated film made of nickel is formed on a surface of the first pad. Therefore, the first pad and a solder never come into contact with each other. Thus, a Cu/Sn alloy layer having poor soldering properties is not generated but a Ni/Sn alloy layer having excellent soldering properties is generated. Consequently, occurrence of sink in the melted solder is suppressed.
    Type: Grant
    Filed: January 30, 2006
    Date of Patent: May 3, 2011
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Sadamichi Takakusaki, Noriaki Sakamoto, Motoichi Nezu, Yusuke Igarashi
  • Patent number: 7935899
    Abstract: Provided is a circuit device in which an electronic circuit to be incorporated therein operates stably. A hybrid integrated circuit device includes multiple circuit boards which are disposed on approximately the same plane. An electronic circuit including a conductive pattern and a circuit element is formed on each top surface of the circuit boards. Furthermore, these circuit boards are integrally supported by a sealing resin. Moreover, a lead connected to the electronic circuit formed on the surface of the circuit board is led out from the sealing resin to the outside.
    Type: Grant
    Filed: August 30, 2006
    Date of Patent: May 3, 2011
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Sadamichi Takukusaki, Noriaki Sakamoto
  • Publication number: 20100293715
    Abstract: Provided is temperature-controlled air circulation type bedding which introduces the blowoff air generated by temperature control unit into an air flow passage provided around a bedding body so as to cool or warm the body of a person in the bedding, controls the blowoff air temperature to form a comfortable sleeping environment irrespective of an external atmosphere temperature, suppresses discharge of carbon dioxide gas, etc. with a compact configuration, and has low power consumption. The temperature-controlled air circulation type bedding includes a temperature control unit 2 which controls the blowoff air temperature by a cooling or heating action, and a bedding body 3 which provides an air flow passage 27 which allows the blowoff air from the temperature control unit to be introduced and circulated therethrough, and cools or warms the inside thereof.
    Type: Application
    Filed: October 21, 2008
    Publication date: November 25, 2010
    Inventors: Noriaki Sakamoto, Tatsuya Ozaki, Koichiro Ochiai, Kosaku Adachi, Yuji Emura, Hiroya Ishikawa
  • Publication number: 20100279596
    Abstract: Provided is a vehicle-mounted temperature control device capable of effectively discharging the exhaust air, which is generated during the driving of a temperature control unit which blows off cooled or warmed air, to the outside of a vehicle. A temperature control unit (1) which blows off the air temperature-controlled by a cooling or warming action is attached to the inside (2) of a vehicle, and an exhaust port (33) is provided at the wall (2a) of a vehicle body to discharge the exhaust air generated during the driving of the temperature control unit to the outside of the vehicle.
    Type: Application
    Filed: October 22, 2008
    Publication date: November 4, 2010
    Inventors: Yuji Emura, Hiroya Ishikawa, Keishi Matsui, Eiichi Okamoto, Takayuki Nakata, Noriaki Sakamoto, Koichiro Ochiai
  • Publication number: 20100263395
    Abstract: Provided is a vehicle-mounted temperature control device (2) capable of suppressing resource wasting or environmental contamination during an idling stop, an easily installed vehicle-mounted refrigeration unit which blows off cooled or warmed air to the inside of a vehicle, and selectively cooling or warming not only a napping cabin behind the driver's seat, but also the driver's seat. The vehicle-mounted temperature control device includes a refrigeration unit having a refrigeration cycle in which a compressor, a condenser, and an evaporator to which driving electric power is supplied by a battery 5 are annularly connected; a temperature control chamber formed from a heat-insulating wall body having a blowoff air trunk and a return air trunk and having a circulation fan and the evaporator in the refrigeration cycle housed therein; and a machine chamber in which the compressor, the condenser, and a radiation fan which cools the compressor and condenser are disposed.
    Type: Application
    Filed: October 30, 2008
    Publication date: October 21, 2010
    Inventors: Kosaku Adachi, Noriaki Sakamoto, Tatsuya Ozaki, Koichiro Ochiai, Yuji Emura, Hiroya Ishikawa, Takayuki Nakata
  • Publication number: 20100255639
    Abstract: A method for manufacturing a semiconductor device includes mounting a first chip over a first area of a chip mounting section of a lead frame and mounting a second chip over a second area of the chip mounting section, wherein the second area is adjacent to the first area via the slit. The chip mounting section is disposed on a flat heating jig. First pads of the first chip are connected with second pads of the second chip via first wires, respectively, and the first pads are connected with leads of the lead frame via second wires, respectively, the first chip, the second chip, the first wires and the second wires are sealed with a resin such that a part of each of the leads is exposed from the resin, and each of the leads is then separated from the lead frame.
    Type: Application
    Filed: June 17, 2010
    Publication date: October 7, 2010
    Inventors: Fujio Ito, Hiromichi Suzuki, Akihiko Kameoka, Noriaki Sakamoto
  • Patent number: 7772044
    Abstract: A method for manufacturing a semiconductor device includes mounting a first chip over a first area of a chip mounting section of a lead frame and mounting a second chip over a second area of the chip mounting section, wherein the second area is adjacent to the first area via the slit. The chip mounting section is disposed on a flat heating jig. First pads of the first chip are connected with second pads of the second chip via first wires, respectively, and the first pads are connected with leads of the lead frame via second wires, respectively. the first chip, the second chip, the first wires and the second wires are sealed with a resin such that a part of each of the leads is exposed from the resin, and each of the leads is then separated from the lead frame.
    Type: Grant
    Filed: November 3, 2008
    Date of Patent: August 10, 2010
    Assignee: Renesas Technology Corp.
    Inventors: Fujio Ito, Hiromichi Suzuki, Akihiko Kameoka, Noriaki Sakamoto
  • Publication number: 20090161324
    Abstract: A shielding case for accommodating a wiring board includes a board mounting member with a fitting member formed at an outer frame thereof so that the wiring board is fixed and held to the board mounting member through fitting of the fitting member into a through hole formed at the wiring board.
    Type: Application
    Filed: September 15, 2008
    Publication date: June 25, 2009
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Noriaki Sakamoto, Masahiro Kobayashi
  • Publication number: 20090135572
    Abstract: Provided is a circuit device in which an electronic circuit to be incorporated therein operates stably. A hybrid integrated circuit device includes multiple circuit boards which are disposed on approximately the same plane. An electronic circuit including a conductive pattern and a circuit element is formed on each top surface of the circuit boards. Furthermore, these circuit boards are integrally supported by a sealing resin. Moreover, a lead connected to the electronic circuit formed on the surface of the circuit board is led out from the sealing resin to the outside.
    Type: Application
    Filed: August 30, 2006
    Publication date: May 28, 2009
    Applicant: Sanyo Electric Co., Ltd.
    Inventors: Sadamichi Takakusaki, Noriaki Sakamoto
  • Publication number: 20090129038
    Abstract: Provided is a simplified structure of a circuit device in which a power element generating a large amount of heat is incorporated. The circuit device according to the present invention includes: a circuit board whose surface is covered with an insulating layer; a conductive pattern formed on the surface of the insulating layer; a circuit element electrically connected to the conductive pattern; and a lead connected to a pad formed of the conductive pattern. Furthermore, a power element is fixed to the top surface of a land portion formed of a part of the lead. Accordingly, the land portion serves as a heat sink, thereby contributing to heat dissipation.
    Type: Application
    Filed: August 30, 2006
    Publication date: May 21, 2009
    Applicant: SANYO ELECTRIC CO., LTD
    Inventors: Sadamichi Takakusaki, Noriaki Sakamoto
  • Patent number: 7529093
    Abstract: A first insulating layer is formed on the front surface of a circuit board, and a second insulating layer on the back surface. A conductive pattern is formed on the surface of the first insulating layer. Circuit elements are connected to the conductive pattern. Sealing resin covers the front and side surfaces of the circuit board. Furthermore, the sealing resin also covers the edge region of the back surface of the circuit board. Thus, it is ensured that the circuit board has a dielectric strength while exposing the back surface of the circuit board to the outside.
    Type: Grant
    Filed: November 28, 2005
    Date of Patent: May 5, 2009
    Assignee: Sanyo Electric Co., Ltd.
    Inventor: Noriaki Sakamoto
  • Patent number: 7521290
    Abstract: The method of the present invention includes a first step of preparing a substrate in which a plurality of circuit boards are integrally connected to one another, each of the circuit boards having conductive patterns which include pads formed on a surface of the circuit board; a second step of electrically connecting circuit elements to the respective conductive patterns on each of the circuit boards; a third step of positioning ends of leads above the respective pads by superposing a lead frame including the plurality of leads on the substrate, and fixing the leads to the pads; and a fourth step of separating the circuit boards from the substrate in a state where the leads are fixed to the respective pads on each of the circuit boards, and thus separating the leads from the lead frame.
    Type: Grant
    Filed: January 11, 2007
    Date of Patent: April 21, 2009
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Sadamichi Takakusaki, Noriaki Sakamoto
  • Publication number: 20090061563
    Abstract: A method for manufacturing a semiconductor device includes mounting a first chip over a first area of a chip mounting section of a lead frame and mounting a second chip over a second area of the chip mounting section, wherein the second area is adjacent to the first area via the slit. The chip mounting section is disposed on a flat heating jig. First pads of the first chip are connected with second pads of the second chip via first wires, respectively, and the first pads are connected with leads of the lead frame via second wires, respectively. the first chip, the second chip, the first wires and the second wires are sealed with a resin such that a part of each of the leads is exposed from the resin, and each of the leads is then separated from the lead frame.
    Type: Application
    Filed: November 3, 2008
    Publication date: March 5, 2009
    Inventors: Fujio ITO, Hiromichi SUZUKI, Akihiko KAMEOKA, Noriaki SAKAMOTO
  • Patent number: 7466024
    Abstract: A semiconductor device comprises a microcomputer chip, an SDRAM which is disposed alongside the microcomputer chip and is thinner than the microcomputer chip, a tub, a plurality of inner leads and outer leads, first wires that connect pads of the microcomputer chip and pads of the SDRAM, and second wires which connect the pads of the microcomputer chip and the inner leads and which are disposed so as to bridge over the SDRAM and are formed with loops at positions higher than loops of the first wires. An interface circuit for a memory bus is connected only between the chips, without connecting to external terminals, and is closed within a package. Therefore, pins can be utilized for other functions correspondingly and a multi-pin configuration can be achieved. Further, the cost of an SIP (semiconductor device) can be reduced owing to the adoption of a frame type.
    Type: Grant
    Filed: October 16, 2006
    Date of Patent: December 16, 2008
    Assignee: Renesas Technology Corp.
    Inventors: Fujio Ito, Hiromichi Suzuki, Akihiko Kameoka, Noriaki Sakamoto
  • Patent number: 7443043
    Abstract: A circuit device 10 comprises a die pad 11, bonding pads 12, a circuit element 9, affixed onto die pad 11, and an insulating resin 14, which seals die pad 11, bonding pads 12, and circuit element 9, and has a configuration wherein recessed parts 15 are formed at parts of the side surfaces of insulating resin 14, and side surface of the conductive patterns that are disposed at peripheral parts are exposed from recessed parts 15. By bonding pads 12, which are to become connecting electrodes to the exterior, being exposed at the side surfaces, fillets of a brazing material 19 are formed at the sides of the device when circuit device 10 is mounted.
    Type: Grant
    Filed: December 11, 2003
    Date of Patent: October 28, 2008
    Assignees: Sanyo Electric Co., Ltd., Kanto Sanyo Semiconductors Co., Ltd.
    Inventor: Noriaki Sakamoto
  • Publication number: 20080119065
    Abstract: A circuit device having improved packaging density is provided. A circuit device of the present invention includes: a circuit board having its surface covered with an insulating layer; conductive patterns formed on a surface of the insulating layer; circuit elements electrically connected to the conductive patterns; and leads connected to pads formed of the conductive patterns. Furthermore, a control element is fixed to an upper surface of a land part formed of a part of a lead, and a back surface of the land part is spaced apart from an upper surface of the circuit board.
    Type: Application
    Filed: October 30, 2007
    Publication date: May 22, 2008
    Applicants: SANYO ELECTRIC CO., LTD., SANYO SEMICONDUCTOR CO., LTD.
    Inventors: Sadamichi TAKAKUSAKI, Noriaki SAKAMOTO, Katsuyoshi MINO
  • Publication number: 20080099922
    Abstract: A first insulating layer is formed on a front surface of a rectangular circuit board. Conductive patterns having a predetermined shape are formed on a front surface of the first insulating layer. A semiconductor element and a chip element are electrically connected to the conductive patterns by use of solder or conductive paste. The conductive patterns, the semiconductor element and the chip element which are formed on the front surface of the circuit board, are covered with a sealing resin. Pads on the circuit board and leads are connected to each other by use of thin metal wires.
    Type: Application
    Filed: October 30, 2006
    Publication date: May 1, 2008
    Inventor: Noriaki Sakamoto
  • Patent number: 7364941
    Abstract: A circuit device manufacturing method is provided, wherein the adhesion of an overcoat resin, formed on a conductive wiring layer, to a sealing resin layer is improved by irradiating plasma onto the overcoat resin. A first conductive film 23A and a second conductive film 23B, which are laminated with an interlayer insulating layer 22 interposed in between, are formed. By selectively removing the first conductive film, a first conductive wiring layer 12A is formed and the first conductive wiring layer is covered with an overcoat resin 18. Overcoat resin 18 is irradiated with plasma to roughen its top surface. A sealing resin layer 17 is formed so as to cover the top surface of the roughened overcoat resin 18 and circuit elements 13.
    Type: Grant
    Filed: August 19, 2005
    Date of Patent: April 29, 2008
    Assignees: Sanyo Electric Co., Ltd., Kanto SANYO Semiconductors Co., Ltd.
    Inventors: Ryosuke Usui, Hideki Mizuhara, Yusuke Igarashi, Noriaki Sakamoto
  • Patent number: 7355272
    Abstract: A semiconductor device includes a wiring board, a first semiconductor chip (e.g. DRAM) that is flip-chip connected on the wiring board, a second semiconductor chip (e.g. DRAM) that is of the same type as the first semiconductor chip and is mounted face up on the first semiconductor chip such that the orientation of the arrangement of the pads is at 90° from that of the first semiconductor chip, a third semiconductor chip (e.g. microcomputer chip) disposed on the second semiconductor chip, wires, and a sealing medium. The wiring board has a plurality of common wiring patterns for electrically connecting first electrodes for the first semiconductor chip and second electrodes for the second semiconductor chip. The common wiring patterns can be disposed without crossing on the surface wire layer of the wiring board.
    Type: Grant
    Filed: February 4, 2005
    Date of Patent: April 8, 2008
    Assignee: Renesas Technology Corp.
    Inventors: Hiroshi Kuroda, Noriaki Sakamoto, Takafumi Kikuchi
  • Patent number: 7332808
    Abstract: A semiconductor module according to the invention includes: an island formed of a conductive material; a plurality of leads disposed in vicinity of the island; a resin sealing body which is mounted on the island and disposed such that a back surface of a circuit board on which semiconductor elements is exposed upward; a sensor which is mounted on the back surface of the circuit board; and a thin metallic wire which electrically connects the circuit board with the leads. The island, the resin sealing body, the sensor, and parts of the leads are sealed by a second sealing resin.
    Type: Grant
    Filed: March 29, 2006
    Date of Patent: February 19, 2008
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Noriaki Sakamoto, Chikara Kaneta, Yoshihiko Yanase, Yoshiyuki Kobayashi