Abstract: The present invention provides a low-profile and light-weight semiconductor device having improved product reliability and higher frequency performance. A multi-layer interconnect line structure is disposed just under circuit devices 410a and 410b. An Interlayer insulating film 405 that composes a part of the multi-layer interconnect line structure is formed of a material having a relative dielectric constant within a range from 1.0 to 3.7, and a dielectric loss tangent within a range from 0.0001 to 0.02.

Abstract: A toner for electrophotography, wherein the toner is prepared by a suspension polymerization or emulsion polymerization from a monomer composition comprising a monovinyl monomer and a coloring agent, and a filtration velocity of the toner is in the range of 0.1 to 3.0 mL/min. The filtration velocity is obtained by an evaluation method comprising following evaluation steps: (i) 15 mg of a toner is added to 5 mL of THF, and soluble component in the toner is dissolved in THF completely to prepare a sample liquid; and (ii) the sample liquid is filtrated at the temperature of 25° C. and pressure of 0.15 kgf/cm2 is applied using a filter wherein an area thereof is 4.0 cm2 and a pore size thereof is 0.45 ?m to measure a filtration time wherein 1 mL of the sample liquid is passed through the filter, and a filtration velocity is determined using the filtration time by a following formula, Filtration velocity (mL/min)=1 (mL)/filtration time (min).

Abstract: A first insulating layer is formed on the front surface of a circuit board, and a second insulating layer on the back surface. A conductive pattern is formed on the surface of the first insulating layer. Circuit elements are connected to the conductive pattern. Sealing resin covers the front and side surfaces of the circuit board. Furthermore, the sealing resin also covers the edge region of the back surface of the circuit board. Thus, it is ensured that the circuit board has a dielectric strength while exposing the back surface of the circuit board to the outside.

Abstract: A semiconductor device is provided wherein conductive paths 40, formed of crystal that grows better along the X-Y axis than along the Z axis, are embedded in an insulating resin 44, and the back surface of the conductive path 40 is exposed through the insulating resin 44 and sealed. With this arrangement, fractures of the conductive paths 40 embedded in the insulating resin 44 are suppressed.

Abstract: A method of manufacturing a circuit device of the present invention comprises the steps of: forming a conductive pattern including a first pad and a second pad on the surface of a substrate; applying a solder paste to the surface of the first pad and then thermally melting the solder paste, thus forming solder; fixing a circuit element to the second pad; and fixing a circuit element to the first pad with the solder therebetween. Furthermore, a flux constituting the solder paste contains sulfur. Since the sulfur is mixed into the solder paste, surface tension of the solder paste is lowered; accordingly occurrence of sink is suppressed.

Abstract: In a hybrid integrated circuit device that is a circuit device of the present invention, a conductive pattern including pads is formed on a surface of a substrate. A first pad is formed to be relatively large since a heat sink is mounted thereon. A second pad is a small pad to which a chip component or a small signal transistor is fixed. In the present invention, a plated film made of nickel is formed on a surface of the first pad. Therefore, the first pad and a solder never come into contact with each other. Thus, a Cu/Sn alloy layer having poor soldering properties is not generated but a Ni/Sn alloy layer having excellent soldering properties is generated. Consequently, occurrence of sink in the melted solder is suppressed.

Abstract: The method of the present invention includes a first step of preparing a substrate in which a plurality of circuit boards are integrally connected to one another, each of the circuit boards having conductive patterns which include pads formed on a surface of the circuit board; a second step of electrically connecting circuit elements to the respective conductive patterns on each of the circuit boards; a third step of positioning ends of leads above the respective pads by superposing a lead frame including the plurality of leads on the substrate, and fixing the leads to the pads; and a fourth step of separating the circuit boards from the substrate in a state where the leads are fixed to the respective pads on each of the circuit boards, and thus separating the leads from the lead frame.

Abstract: To provide a test technology capable of reducing a package size by reducing a number of terminals (pins) in a semiconductor integrated circuit of SIP or the like constituted by mounting a plurality of semiconductor chips to a single package, in SIP 102 constituted by mounting a plurality of semiconductor chips to a signal package of ASIC 100, SDRAM 101 and the like, a circuit of testing SDRAM 101 (SDRAMBIST 109) is provided at inside of ASIC 100, and SDRAM 101 is tested from outside of SDRAM 101, that is, from ASIC 100. By providing the test circuit of SDRAM 101 at inside of ASIC 100, it is not necessary to extrude a terminal for testing SDRAM 101 to outside of SIP 102.

Abstract: In the present invention there is formed a sheet-like board member 50 having conductive coating films, such as first pads 55 and die pads 59, formed thereon or a sheet-like board member 50 which has been half-etched by using conductive coating films such as first pads 55 and die pads 59. A hybrid IC can be manufactured by means of utilization of post-processing processes of a semiconductor manufacturer. Further, a hybrid IC can be manufactured without adoption of a support board, and hence there can be manufactured a hybrid IC which is of lower profile and has superior heat dissipation characteristics.

Abstract: To provide a circuit device having both of high heat releasing property and high breakdown voltage, and a method of manufacturing the same. A first insulating layer is formed on a front surface of a circuit board, and a second insulating layer is formed on a rear surface thereof. Conductive patterns are formed on a surface of the first insulating layer and are fixed to circuit elements. Furthermore, a metal board is stuck to a surface of the second insulating layer. A sealing resin covers front and side surfaces of the circuit board and additionally covers peripheral portions of the rear surface of the circuit board in a manner that the rear surface of the metal board is exposed. Thus, a heat releasing property and a withstand voltage property of the circuit board are ensured.

Abstract: A protection circuit device using a MOSFET has a plural of conductive paths separated electrically, a MOSFET chip integrating two power MOSFETs in one chip where a gate electrode and a source electrode are fixed on the desired conductive path, conductive material provided on a common drain electrode of the MOSFET, and insulating resin covering said MOSFET and supporting said conductive path in one body. Removing a drawing-around of the common drain electrode and fixing the source electrode directly on the conductive path, low ON-state resistance is realized.

Abstract: Die pads 50, 51, an external connecting electrode 52 and a bridge are covered with an insulating resin after half-etching, formed into a single package without a coupling member such as a supporting lead or adhesive tape. In addition, since no supporting board is required, a low-profile semiconductor device with improved heat radiation can be provided.

Abstract: A semiconductor device comprises a microcomputer chip, an SDRAM which is disposed alongside the microcomputer chip and is thinner than the microcomputer chip, a tub, a plurality of inner leads and outer leads, first wires that connect pads of the microcomputer chip and pads of the SDRAM, and second wires which connect the pads of the microcomputer chip and the inner leads and which are disposed so as to bridge over the SDRAM and are formed with loops at positions higher than loops of the first wires. An interface circuit for a memory bus is connected only between the chips, without connecting to external terminals, and is closed within a package. Therefore, pins can be utilized for other functions correspondingly and a multi-pin configuration can be achieved. Further, the cost of an SIP (semiconductor device) can be reduced owing to the adoption of a frame type.

Abstract: To provide a test technology capable of reducing a package size by reducing a number of terminals (pins) in a semiconductor integrated circuit of SIP or the like constituted by mounting a plurality of semiconductor chips to a single package, in SIP 102 constituted by mounting a plurality of semiconductor chips to a signal package of ASIC 100, SDRAM 101 and the like, a circuit of testing SDRAM 101 (SDRAMBIST 109) is provided at inside of ASIC 100, and SDRAM 101 is tested from outside of SDRAM 101, that is, from ASIC 100. By providing the test circuit of SDRAM 101 at inside of ASIC 100, it is not necessary to extrude a terminal for testing SDRAM 101 to outside of SIP 102.

Abstract: A semiconductor device is provided wherein conductive paths 40, formed of crystal that grows better along the X-Y axis than along the Z axis, are embedded in an insulating resin 44, and the back surface of the conductive path 40 is exposed through the insulating resin 44 and sealed. With this arrangement, fractures of the conductive paths 40 embedded in the insulating resin 44 are suppressed.

Abstract: A method for fabricating a circuit device includes preparing a laminating sheet comprising a conductive film, insulation resin formed on the surface of the conductive film, and a first conductive path layer formed on the surface of the insulation resin. Semiconductor elements are adhered and fixed on the first conductive path layer. A sealing resin is provided as an overcoat to the first conductive path layer and the semiconductor elements. The method includes forming a second conductive path layer by etching the conductive film into a predetermined pattern and forming an external electrode at predetermined points of the second conductive path layer.

Abstract: A method of manufacturing a semiconductor device is described. A board that includes a flat back face, corresponding to a resin sealing area, and a front face that has projections is provided. The projections are formed of a metal that is integral with the board and include (a) a bonding pad provided in an area surrounded by an area that contacts an upper die, (b) a wiring that is integrated with the bonding pad and which extends to a semiconductor element mounting area, and (c) an electrode provided in one body with the wiring. A semiconductor element is mounted on the semiconductor element area and electrically connected to the bonding pad. The board is placed on a lower die and resin is filled into a space formed by the board and upper die. The board is divided into multiple devices such that the projections are separated by removing the board exposed at the back face of the resin.

Abstract: After a trench 54 is formed in a conductive foil 60, the circuit elements are mounted, and the insulating resin is applied on the conductive foil 60 as the support substrate. After being inverted, the conductive foil 60 is polished on the insulating resin 50 as the support substrate for separation into the conductive paths. Accordingly, it is possible to fabricate the circuit device in which the conductive paths 51 and the circuit elements 52 are supported by the insulating resin 50, without the use of the support substrate. And the interconnects L1 to L3 requisite for the circuit are formed, and can be prevented from slipping because of the curved structure 59 and a visor 58.

Abstract: A semiconductor module according to the invention includes: an island formed of a conductive material; a plurality of leads disposed in vicinity of the island; a resin sealing body which is mounted on the island and disposed such that a back surface of a circuit board on which semiconductor elements is exposed upward; a sensor which is mounted on the back surface of the circuit board; and a thin metallic wire which electrically connects the circuit board with the leads. The island, the resin sealing body, the sensor, and parts of the leads are sealed by a second sealing resin.

Abstract: A circuit device manufacturing method is provided, wherein contaminants attached to the top surfaces of conductive patterns 21 are removed using plasma to thereby improve the adhesion of conductive patterns 21 to a sealing resin 28. By selective etching of a conductive foil 10, separation grooves 11 are formed, thereby forming conductive patterns 21. A semiconductor element 22A and other circuit elements are mounted onto desired locations of conductive patterns 21 and electrically connected with conductive patterns 21. By irradiating plasma onto conductive foil 10 from above, contaminants attached to the surfaces of separation grooves 11 are removed.