Patents by Inventor Norikazu Nakamura

Norikazu Nakamura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9920428
    Abstract: A film deposition apparatus includes: a plasma generating section configured to generate plasma between a cathode target and an anode; a film deposition chamber in which a base material is placed; and a magnetic-field filter section configured to remove a particle from the plasma by a magnetic field and to transfer the plasma to the film deposition chamber. The magnetic-field filter section includes: a first housing area to which a first voltage is applied; and a second housing area, provided downstream of the first housing area in the moving direction of the plasma, to which a second voltage is applied.
    Type: Grant
    Filed: December 10, 2015
    Date of Patent: March 20, 2018
    Assignee: FUJITSU LIMITED
    Inventors: Norikazu Nakamura, Shoichi Miyahara, Hiroshi Chiba
  • Publication number: 20180068923
    Abstract: A disclosed semiconductor device includes a buffer layer formed of a compound semiconductor on a substrate, a first semiconductor layer formed of a compound semiconductor on the buffer layer, a second semiconductor layer formed of a compound semiconductor on the first semiconductor layer, a gate electrode, a source electrode, and a drain electrode formed on the second semiconductor layer, and a heat dissipation part formed below the gate electrode. In the semiconductor device, all or part of the second semiconductor layer and the first semiconductor layer is present between the gate electrode and the heat dissipation part, the heat dissipation part includes a heat dissipation layer and a first intermediate layer formed between the heat dissipation layer and both of the buffer layer and first semiconductor layer, and the heat dissipation layer is formed of a material containing carbon.
    Type: Application
    Filed: August 18, 2017
    Publication date: March 8, 2018
    Applicant: FUJITSU LIMITED
    Inventors: JUNJI KOTANI, NORIKAZU NAKAMURA
  • Publication number: 20180069086
    Abstract: A semiconductor crystal substrate includes a first buffer layer formed of a nitride semiconductor over a substrate, a second buffer layer formed of a nitride semiconductor on the first buffer layer, a first semiconductor layer formed of a nitride semiconductor on or over the second buffer layer, and a second semiconductor layer formed of a nitride semiconductor on the first semiconductor layer. The Fe concentration of the first buffer layer is higher than the C concentration of the first buffer layer. The C concentration of the second buffer layer is higher than the Fe concentration of the second buffer layer.
    Type: Application
    Filed: August 28, 2017
    Publication date: March 8, 2018
    Applicant: FUJITSU LIMITED
    Inventors: Tetsuro Ishiguro, Atsushi Yamada, JUNJI KOTANI, NORIKAZU NAKAMURA
  • Publication number: 20180061765
    Abstract: A wiring substrate includes a first wiring structure and a second wiring structure having a higher wiring density. The second wiring structure includes a wiring layer formed on a first insulation layer of the first wiring structure. The wiring layer includes a first wiring pattern, the upper surface of which includes smooth and rough surfaces. A protective film, formed from a conductive material having a higher migration resistance than the wiring layer, covers only the smooth surface and includes a smooth upper surface. A second insulation layer stacked on the first insulation layer covers the wiring layer and the protective film. The smooth surface is continuous with and downwardly recessed from the smooth surface to expose a peripheral portion of the protective film. The second insulation layer covers upper, lower, and side surfaces of the peripheral portion.
    Type: Application
    Filed: August 24, 2017
    Publication date: March 1, 2018
    Inventors: YUSUKE GOZU, YUTA SAKAGUCHI, NORIKAZU NAKAMURA, NORIYOSHI SHIMIZU
  • Publication number: 20180047840
    Abstract: A semiconductor device includes a first semiconductor layer formed of a nitride semiconductor above a substrate, a second semiconductor layer formed of a material including InAlN or InAlGaN above the first semiconductor layer, a third semiconductor layer formed of a material including AlN above the second semiconductor layer, a fourth semiconductor layer formed of a material including GaN above the third semiconductor layer, a gate electrode formed above the fourth semiconductor layer, and a source electrode and a drain electrode formed on any one of the second semiconductor layer, the third semiconductor layer, and the fourth semiconductor layer.
    Type: Application
    Filed: October 24, 2017
    Publication date: February 15, 2018
    Applicant: FUJITSU LIMITED
    Inventors: Norikazu NAKAMURA, Junji KOTANI
  • Patent number: 9831310
    Abstract: A compound semiconductor device includes: a compound semiconductor multilayer structure including a first buffer layer composed of AlN; and a second buffer layer composed of AlGaN and formed above the first buffer layer, wherein the second buffer layer contains carbon, and wherein the concentration of carbon in the second buffer layer increases with increasing distance from a lower surface of the second buffer layer toward an upper surface of the second buffer layer.
    Type: Grant
    Filed: May 23, 2013
    Date of Patent: November 28, 2017
    Assignee: FUJITSU LIMITED
    Inventors: Junji Kotani, Norikazu Nakamura
  • Publication number: 20170229566
    Abstract: A semiconductor device includes a substrate, a buffer layer including a nitride semiconductor and formed over the substrate, a composition gradient layer including a nitride semiconductor and formed over the buffer layer, a first semiconductor layer including a nitride semiconductor and formed over the composition gradient layer, a second semiconductor layer including a nitride semiconductor and formed over the first semiconductor layer, and a gate electrode, a source electrode, and a drain electrode that are formed over the second semiconductor layer. The buffer layer is formed of a material including GaN, the composition gradient layer is formed of a material including Al, and the proportion of Al in the composition gradient layer increases from a first side of the composition gradient layer closer to the buffer layer toward a second side of the composition gradient layer closer to the first semiconductor layer.
    Type: Application
    Filed: December 20, 2016
    Publication date: August 10, 2017
    Applicant: FUJITSU LIMITED
    Inventors: Tetsuro Ishiguro, NORIKAZU NAKAMURA
  • Patent number: 9691890
    Abstract: A compound semiconductor device includes a compound semiconductor stacked structure, the compound semiconductor stacked structure including: an electron transit layer; an electron supply layer formed above the electron transit layer, the electron supply layer containing an n-type impurity; and a cap layer formed above the electron supply layer and containing the n-type impurity, in which in the electron supply layer, a concentration of the n-type impurity contained therein is non-uniform in a film thickness direction and a concentration of the n-type impurity in a surface of the cap layer side is lower than a maximum concentration of the n-type impurity in the electron supply layer.
    Type: Grant
    Filed: October 3, 2016
    Date of Patent: June 27, 2017
    Assignee: FUJITSU LIMITED
    Inventors: Norikazu Nakamura, Atsushi Yamada, Junji Kotani
  • Publication number: 20170125563
    Abstract: A compound semiconductor device includes: a first layer of nitride semiconductor, the first layer being doped with Fe; a channel layer of nitride semiconductor above the first layer; and a barrier layer of nitride semiconductor above the channel layer, wherein the channel layer includes: a two-dimensional electron gas region in which the two-dimensional electron gas exists; and an Al-containing region between the two-dimensional electron gas region and the first layer, an Al concentration in the Al-containing region being 5×1017 atoms/cm3 or more and less than 1×1019 atoms/cm3.
    Type: Application
    Filed: September 25, 2016
    Publication date: May 4, 2017
    Applicant: FUJITSU LIMITED
    Inventors: Tetsuro Ishiguro, NORIKAZU NAKAMURA, Atsushi Yamada
  • Publication number: 20170125533
    Abstract: A semiconductor apparatus includes a semiconductor chip including a first semiconductor layer formed over a substrate, a second semiconductor layer formed over the first semiconductor layer, and a gate electrode, a source electrode, and a drain electrode formed over the second semiconductor layer. The gate electrode is formed in a comb shape having a plurality of tooth parts. An interval between the tooth parts becomes narrower from a center part toward a peripheral part of the semiconductor chip. The source electrode is formed on one of two sides of each of the tooth parts in the gate electrode, and the drain electrode is formed on another of the two sides. The source electrodes and the drain electrodes formed between the tooth parts in the gate electrode have respective areas that are substantially the same in a plan view.
    Type: Application
    Filed: September 8, 2016
    Publication date: May 4, 2017
    Applicant: FUJITSU LIMITED
    Inventors: JUNJI KOTANI, NORIKAZU NAKAMURA
  • Publication number: 20170125516
    Abstract: A compound semiconductor device includes: a GaN-based channel layer; a barrier layer of nitride semiconductor above the channel layer; and a cap layer of nitride semiconductor above the barrier layer, wherein the cap layer includes: a first region doped with Fe; and a second region above the first region, a concentration of Fe in the second region being lower than a concentration of Fe in the first region.
    Type: Application
    Filed: September 22, 2016
    Publication date: May 4, 2017
    Applicant: FUJITSU LIMITED
    Inventors: Tetsuro Ishiguro, Atsushi Yamada, NORIKAZU NAKAMURA
  • Publication number: 20170125566
    Abstract: A compound semiconductor device includes a compound semiconductor stacked structure, the compound semiconductor stacked structure including: an electron transit layer; an electron supply layer formed above the electron transit layer, the electron supply layer containing an n-type impurity; and a cap layer formed above the electron supply layer and containing the n-type impurity, in which in the electron supply layer, a concentration of the n-type impurity contained therein is non-uniform in a film thickness direction and a concentration of the n-type impurity in a surface of the cap layer side is lower than a maximum concentration of the n-type impurity in the electron supply layer.
    Type: Application
    Filed: October 3, 2016
    Publication date: May 4, 2017
    Applicant: FUJITSU LIMITED
    Inventors: NORIKAZU NAKAMURA, ATSUSHI YAMADA, JUNJI KOTANI
  • Publication number: 20170125564
    Abstract: A semiconductor crystal substrate includes a substrate, a first semiconductor layer including a nitride semiconductor and formed over the substrate, a second semiconductor layer including a nitride semiconductor and formed over the first semiconductor layer, a first cap layer formed on the second semiconductor layer, and a second cap layer formed on the first cap layer. Each of the first semiconductor layer and the second semiconductor layer has a single-crystal structure, the first cap layer has one of a single-crystal structure and a polycrystalline structure, and the second cap layer has an amorphous structure.
    Type: Application
    Filed: September 26, 2016
    Publication date: May 4, 2017
    Applicant: FUJITSU LIMITED
    Inventors: JUNJI KOTANI, NORIKAZU NAKAMURA
  • Patent number: 9608083
    Abstract: A semiconductor device includes a first semiconductor layer formed over a substrate, a second semiconductor layer formed over the first semiconductor layer, a source electrode and a drain electrode formed over the second semiconductor layer, an insulating film formed over the second semiconductor layer, a gate electrode formed over the insulating film, and a protection film covering the insulating film, the protection film being formed by thermal CVD, thermal ALD, or vacuum vapor deposition.
    Type: Grant
    Filed: June 9, 2015
    Date of Patent: March 28, 2017
    Assignee: FUJITSU LIMITED
    Inventors: Shirou Ozaki, Masahito Kanamura, Norikazu Nakamura, Toyoo Miyajima, Masayuki Takeda, Keiji Watanabe, Toshihide Kikkawa, Kenji Imanishi, Toshihiro Ohki, Tadahiro Imada
  • Publication number: 20170050449
    Abstract: When an image is printed by inkjet printing on a print surface of a target medium, an overcoat layer is formed in a more appropriate manner. A printing method uses color ink heads 202 as exemplified colored ink heads, a clear ink head 204, and ultraviolet irradiators 206. The printing method includes a color printing step of printing a print image using a colored ink in at least a partial region on a print surface of a medium 50, a non-colored region clear printing step of applying a UV clear ink for printing in a region at least including a non-colored region in which ink droplets are not discharged in the color printing step, and an overcoat layer forming step of forming an overcoat layer that covers the print image using the UV clear ink in a region covering at least the print image printed in the color printing step.
    Type: Application
    Filed: April 17, 2015
    Publication date: February 23, 2017
    Applicant: MIMAKI ENGINEERING CO., LTD.
    Inventors: AKIRA IKEDA, NORIKAZU NAKAMURA, MOE ITO
  • Patent number: 9567674
    Abstract: A film deposition apparatus includes: a plasma generating section configured to generate plasma between a cathode target and an anode; a film deposition chamber in which a base material is placed; and a magnetic-field filter section configured to remove a particle from the plasma by a magnetic field and to transfer the plasma to the film deposition chamber. The magnetic-field filter section includes: a first housing area to which a first voltage is applied; and a second housing area, provided downstream of the first housing area in the moving direction of the plasma, to which a second voltage is applied.
    Type: Grant
    Filed: June 2, 2010
    Date of Patent: February 14, 2017
    Assignee: FUJITSU LIMITED
    Inventors: Norikazu Nakamura, Shoichi Miyahara, Hiroshi Chiba
  • Patent number: 9548365
    Abstract: A semiconductor device includes: a buffer layer formed over a substrate; a first semiconductor layer formed over the buffer layer by using a compound semiconductor; a second semiconductor layer formed over the first semiconductor layer by using a compound semiconductor; and a gate electrode, a source electrode, and a drain electrode formed over the second semiconductor layer, wherein the first semiconductor layer contains an impurity element serving as an acceptor and an impurity element serving as a donor; and in the first semiconductor layer, an acceptor concentration of the impurity element serving as the acceptor is greater than a donor concentration of the impurity element serving as the donor; and the donor concentration is greater-than over equal to 5×1016 cm?3.
    Type: Grant
    Filed: October 26, 2015
    Date of Patent: January 17, 2017
    Assignee: FUJITSU LIMITED
    Inventors: Junji Kotani, Norikazu Nakamura
  • Publication number: 20160359032
    Abstract: A compound semiconductor device includes: a carrier transit layer; a carrier supply layer that is formed over the carrier transit layer and is made of InAlN; and a spacer layer that is formed between the carrier transit layer and the carrier supply layer and is made of at least one of AlGaN and InAlGaN.
    Type: Application
    Filed: May 31, 2016
    Publication date: December 8, 2016
    Applicant: FUJITSU LIMITED
    Inventors: JUNJI KOTANI, NORIKAZU NAKAMURA, Tetsuro Ishiguro
  • Patent number: 9502525
    Abstract: An embodiment of a method of manufacturing a compound semiconductor device includes: forming an initial layer over a substrate; forming a buffer layer over the initial layer; forming an electron transport layer and an electron supply layer over the buffer layer; and forming a gate electrode, a source electrode and a gate electrode over the electron supply layer. The forming an initial layer includes: forming a first compound semiconductor film with a flow rate ratio being a first value, the flow rate ratio being a ratio of a flow rate of a V-group element source gas to a flow rate of a III-group element source gas; and forming a second compound semiconductor film with the flow rate ratio being a second value different from the first value over the first compound semiconductor film. The method further includes forming an Fe-doped region between the buffer layer and the electron transport layer.
    Type: Grant
    Filed: December 11, 2012
    Date of Patent: November 22, 2016
    Assignee: FUJITSU LIMITED
    Inventors: Tetsuro Ishiguro, Atsushi Yamada, Norikazu Nakamura, Kenji Imanishi
  • Publication number: 20160194757
    Abstract: A film deposition apparatus includes: a plasma generating section configured to generate plasma between a cathode target and an anode; a film deposition chamber in which a base material is placed; and a magnetic-field filter section configured to remove a particle from the plasma by a magnetic field and to transfer the plasma to the film deposition chamber. The magnetic-field filter section includes: a first housing area to which a first voltage is applied; and a second housing area, provided downstream of the first housing area in the moving direction of the plasma, to which a second voltage is applied.
    Type: Application
    Filed: December 10, 2015
    Publication date: July 7, 2016
    Applicant: FUJITSU LIMITED
    Inventors: Norikazu Nakamura, Shoichi Miyahara, Hiroshi Chiba