Patents by Inventor Norio Chujo
Norio Chujo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20140125398Abstract: Provided is a configuration of a driver integrated circuit that can output a voltage exceeding the withstand voltage of a process, and that satisfies required apparatus performance (high speed and high voltage). A differential input circuit, a level shift circuit, and an output circuit are manufactured by the same process and divided and disposed on three or more chips with different substrate potentials (sub-potentials). By setting different applied voltages to the substrates of the chips, an output voltage greater than the process withstand voltage can be provided (see FIG. 2).Type: ApplicationFiled: May 24, 2012Publication date: May 8, 2014Applicant: Hitachi, Ltd.Inventors: Wen Li, Norio Chujo, Masami Makuuchi, Takehito Kamimura
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Publication number: 20140023315Abstract: An optical module achieving optical coupling at a low cost and by a simple and convenient process is intended to be provided. For attaining the purpose, a transparent member sealing an optical device and an optical transmission channel are connected as an optical coupling structure. Specifically, optical coupling is achieved in an optical module having an optical device, a first substrate having the optical device mounted thereon, and a second substrate or a transparent resin provided over the first substrate so as to hermetically seal the optical device by connecting an optical transmission channel over the second substrate or the transparent resin at a portion in which light from the optical device is transmitted.Type: ApplicationFiled: November 18, 2011Publication date: January 23, 2014Applicant: Hitachi LtdInventors: Toshiaki Takai, Norio Chujo, Saori Hamamura
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Patent number: 8451063Abstract: A circuit having a sensor with a stray capacitance value. An output from the sensor is connected to the input of an amplifier while a negative capacitance circuit is electrically connected in parallel with the sensor output. The negative capacitance circuit reduces the effect of the sensor stray capacitance to provide an increased bandwidth and decreased noise on the amplifier output.Type: GrantFiled: September 29, 2010Date of Patent: May 28, 2013Assignee: Hitachi, Ltd.Inventors: Masayoshi Takahashi, Norio Chujo, Masami Makuuchi
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Patent number: 8437584Abstract: In fabricating an optical I/O array module, an optical waveguide provided with mirror parts, each having a tapered face, is formed on a substrate, a convex shaped member or a concave shaped member is placed at spots above the respective mirror parts of the optical waveguide, and laser diode arrays and photo diode arrays, provided with either a concave shape, or a convex shape, are mated with, or into the convex shaped member or the concave shaped member before being mounted. Further, there are formed multiple filmy layers, on which an LSI where a driver IC LSI of optical elements, and an amplifier LSI of the optical elements are integrated.Type: GrantFiled: July 27, 2010Date of Patent: May 7, 2013Assignee: Hitachi, Ltd.Inventors: Yasunobu Matsuoka, Toshiki Sugawara, Koichiro Adachi, Naoki Matsushima, Saori Hamamura, Madoka Minagawa, Norio Chujo
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Patent number: 8406581Abstract: A photoelectric composite wiring module, being superior in performances and mass-productivity thereof, and a transmission apparatus of applying that therein are provided. Optical devices 2a and 2b are disposed on a circuit board 1, so that they are optically coupled with optical guides 11 formed on the circuit board 1, wherein a filet-like resin is formed on a side surface of a bump, which is formed on side surfaces or/and upper portions of the optical devices, on an upper layer thereof being compressed a resin film to be adhered thereon, thereby forming an insulation film 31, and an electric wiring layer 3 is laminated, so that the electrodes of the optical devices 2 and wirings of the electric wiring layer are electrically connected with, and further thereon is mounted a semiconductor element 4; thereby obtaining the structure for brining the transmission speed to be high per channel, and for preventing the power consumption from increasing.Type: GrantFiled: June 2, 2010Date of Patent: March 26, 2013Assignee: Hitachi, Ltd.Inventors: Saori Hamamura, Naoki Matsushima, Madoka Minagawa, Satoshi Kaneko, Norio Chujo, Yasunobu Matsuoka, Toshiki Sugawara, Tsutomu Kono
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Patent number: 8401347Abstract: A photoelectric composite wiring module includes a circuit substrate, an optical device, an LSI (device) having a driver and an amplifier for the optical device, and a thin film wiring layer having an electrical wiring. The optical device is connected with the LSI by means of the electrical wiring. The optical device is formed on the circuit substrate and optically coupled to an optical waveguide formed in the circuit substrate. The thin film wiring layer is formed on the optical device to ensure that the optical device is electrically connected with the electrical wiring of the thin film wiring layer. The LSI is mounted on and electrically connected with the thin film wiring layer.Type: GrantFiled: November 23, 2009Date of Patent: March 19, 2013Assignee: Hitachi, Ltd.Inventors: Naoki Matsushima, Norio Chujo, Yasunobu Matsuoka, Toshiki Sugawara, Madoka Minagawa, Saori Hamamura, Satoshi Kaneko, Tsutomu Kono
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Patent number: 8358172Abstract: A peaking circuit for adjusting peaking of a high-frequency signal, comprises: a first inductor; a second inductor which is electromagnetically coupled with the first inductor; a signal input section which receives an input signal; a transistor which adjusts electric current passing through the second inductor according to the input signal inputted via the signal input section; and a signal output section which outputs a signal whose peaking has been adjusted by the first inductor. Mutual inductance of the electromagnetically coupled first and second inductors is changed by the adjustment of the electric current passing through the second inductor, according to the input signal inputted via the signal input section, with the use of the transistor, thereby adjusting the peaking of signal waveform of electric current passing through the first inductor, and the signal subjected to the peaking adjustment is outputted from the signal output section.Type: GrantFiled: February 9, 2011Date of Patent: January 22, 2013Assignee: Hitachi, Ltd.Inventors: Norio Chujo, Tsuneo Kawamata, Toshiaki Takai
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Patent number: 8324925Abstract: An output buffer includes inverters, a delay circuit for delaying an input signal, buffers and switches. The output buffer transmits a logic signal to a transmission path and, in accordance with an amount of signal attenuation in the transmission path, creates a waveform including four or more kinds of signal voltages. The buffers are redundantly connected in parallel, and the number of buffers concurrently turn ON is controlled by respective switches provided in series with output resistors of the buffers. By selecting the buffers of switches which are turned ON, the preemphasis amount and a number of preemphasis taps are adjusted through a selector logic selection signal so that the preemphasis amount is made variable and the ON resistance of the buffers is made constant.Type: GrantFiled: May 13, 2011Date of Patent: December 4, 2012Assignee: Hitachi, Ltd.Inventors: Satoshi Muraoka, Norio Chujo, Ritsuro Orihashi
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Publication number: 20120128292Abstract: A photoelectric composite wiring module, being superior in performances and mass-productivity thereof, and a transmission apparatus of applying that therein are provided. Optical devices 2a and 2b are disposed on a circuit board 1, so that they are optically coupled with optical guides 11 formed on the circuit board 1, wherein a filet-like resin is formed on a side surface of a bump, which is formed on side surfaces or/and upper portions of the optical devices, on an upper layer thereof being compressed a resin film to be adhered thereon, thereby forming an insulation film 31, and an electric wiring layer 3 is laminated, so that the electrodes of the optical devices 2 and wirings of the electric wiring layer are electrically connected with, and further thereon is mounted a semiconductor element 4; thereby obtaining the structure for brining the transmission speed to be high per channel, and for preventing the power consumption from increasing.Type: ApplicationFiled: June 2, 2010Publication date: May 24, 2012Applicant: Hitachi-Ltd.Inventors: Saori Hamamura, Naoki Matsushima, Madoka Minagawa, Satoshi Kaneko, Norio Chujo, Yasunobu Matsuoka, Toshiki Sugawara, Tsutomu Kono
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Publication number: 20120075021Abstract: A circuit having a sensor with a stray capacitance value. An output from the sensor is connected to the input of an amplifier while a negative capacitance circuit is electrically connected in parallel with the sensor output. The negative capacitance circuit reduces the effect of the sensor stray capacitance to provide an increased bandwidth and decreased noise on the amplifier output.Type: ApplicationFiled: September 29, 2010Publication date: March 29, 2012Applicant: Hitachi, LtdInventors: Masayoshi Takahashi, Norio Chujo, Masami Makuuchi
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Patent number: 8067984Abstract: There is provided a variable gain circuit system which is inductorless and capable of achieving a high gain and a wide band by elements for achieving variable gain to prevent decreasing a gain or deteriorating the band. The variable gain circuit includes: transistors; a resistor connected as a load of each transistor; a voltage source applying a bias voltage to each gate of the transistors; a switch selectively connecting the voltage source or a ground potential to each gate of the transistors in accordance with gain setting; and a current source connected to a common input. A drain of each transistor is connected to an input of a circuit in a subsequent stage.Type: GrantFiled: June 9, 2010Date of Patent: November 29, 2011Assignee: Hitachi, Ltd.Inventors: Takehito Kamimura, Norio Chujo
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Publication number: 20110241778Abstract: A peaking circuit for adjusting peaking of a high-frequency signal, comprises: a first inductor; a second inductor which is electromagnetically coupled with the first inductor; a signal input section which receives an input signal; a transistor which adjusts electric current passing through the second inductor according to the input signal inputted via the signal input section; and a signal output section which outputs a signal whose peaking has been adjusted by the first inductor. Mutual inductance of the electromagnetically coupled first and second inductors is changed by the adjustment of the electric current passing through the second inductor, according to the input signal inputted via the signal input section, with the use of the transistor, thereby adjusting the peaking of signal waveform of electric current passing through the first inductor, and the signal subjected to the peaking adjustment is outputted from the signal output section.Type: ApplicationFiled: February 9, 2011Publication date: October 6, 2011Inventors: Norio CHUJO, Tsuneo Kawamata, Toshiaki Takai
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Publication number: 20110215830Abstract: An output buffer includes inverters, a delay circuit for delaying an input signal, buffers and switches. The output buffer transmits a logic signal to a transmission path and, in accordance with an amount of signal attenuation in the transmission path, creates a waveform including four or more kinds of signal voltages. The buffers are redundantly connected in parallel, and the number of buffers concurrently turn ON is controlled by respective switches provided in series with output resistors of the buffers. By selecting the buffers of switches which are turned ON, the preemphasis amount and a number of preemphasis taps are adjusted through a selector logic selection signal so that the preemphasis amount is made variable and the ON resistance of the buffers is made constant.Type: ApplicationFiled: May 13, 2011Publication date: September 8, 2011Inventors: Satoshi MURAOKA, Norio Chujo, Ritsuro Orihashi
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Patent number: 8005130Abstract: A transmitting and receiving technique in which a load on data signal lines is reduced while maintaining a communication quality, thereby making it possible to improve the throughput of data channels. In a transceiver, a transmitter side has an encoder circuit that transmits a bit sequence obtained by encoding link information to a clock signal line, and a receiver side has a clock and data recovery circuit 17 that extracts a clock component from a signal received from the clock signal line, a decoder circuit 19 that decodes the extracted signal to reproduce the link information, and a bit deskew circuit 21 that adjusts a skew that is lower than one bit on the basis of a clock component.Type: GrantFiled: July 13, 2007Date of Patent: August 23, 2011Assignee: Hitachi, Ltd.Inventors: Hidehiro Toyoda, Tatsuya Saito, Hiroki Yamashita, Norio Chujo
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Publication number: 20110181271Abstract: A peaking circuit according to the present invention includes amplifiers connected in multiple stages and feedback circuits for feedback to an input from two or more output points with different gains as seen from the input. The peaking circuit is configured to be able to change an amount of feedback of the feedback circuits.Type: ApplicationFiled: January 26, 2011Publication date: July 28, 2011Inventors: Norio CHUJO, Takehito Kamimura
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Patent number: 7969751Abstract: A high-speed signal transmission apparatus comprises: a housing; a plurality of daughter boards juxtaposed to one another in the housing; board-side connectors each provided on corresponding each of the juxtaposed daughter boards; and cable-side connectors fixed in the housing; wherein each of the board-side connectors is insertable/removable into/from corresponding each of the cable-side connectors, and wherein a cable group whose impedance matching can be achieved makes connection between the predetermined cable-side connectors.Type: GrantFiled: July 10, 2008Date of Patent: June 28, 2011Assignee: Hitachi Cable, Ltd.Inventors: Keiichi Yamamoto, Norio Chujo, Takashi Kumakura, Yosuke Ishimatsu
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Patent number: 7969197Abstract: An output buffer includes inverters, a delay circuit for delaying an input signal, buffers and switches. The output buffer transmits a logic signal to a transmission path and, in accordance with an amount of signal attenuation in the transmission path, creates a waveform including four or more kinds of signal voltages. The buffers are redundantly connected in parallel, and the number of buffers concurrently turn ON is controlled by respective switches provided in series with output resistors of the buffers. By selecting the buffers of switches which are turned ON, the preemphasis amount and a number of preemphasis taps are adjusted through a selector logic selection signal so that the preemphasis amount is made variable and the ON resistance of the buffers is made constant.Type: GrantFiled: March 3, 2010Date of Patent: June 28, 2011Assignee: Hitachi, Ltd.Inventors: Satoshi Muraoka, Norio Chujo, Ritsuro Orihashi
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Patent number: 7965765Abstract: In an adjustment method of waveform equalization coefficient, one of jitter and amplitude is measured only in a case of an arbitrary signal sequence and a waveform equalization coefficient is adjusted. Particularly, using a signal of received signals other than a 010 signal or a 101 signal, code inversion time is measured. Since the code inversion time in a case where such signals are used becomes steeper in comparison with that in the conventional technique, adjustment time of the waveform equalization coefficient can be reduced.Type: GrantFiled: December 28, 2007Date of Patent: June 21, 2011Assignee: Hitachi, Ltd.Inventors: Hisaaki Kanai, Norio Chujo, Masayoshi Yagyu
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Patent number: 7902860Abstract: In a semiconductor circuit, an impedance adjustment circuit having the characteristics same as those of a circuit having the nonlinear resistance characteristics is configured to include an operating point calculation circuit automatically calculating an operating point with a reference resistance through feedback control, and an impedance calculation circuit calculating the impedance at the operating point found by the operating point calculation circuit. The impedance adjustment circuit is also provided with an impedance determination circuit that determines whether or not the impedance found by the impedance calculation circuit is in a predetermined range. These components, i.e., the operating point calculation circuit, the impedance calculation circuit, and the impedance determination circuit, are provided each two for High-side and Low-side impedance adjustment use.Type: GrantFiled: June 25, 2008Date of Patent: March 8, 2011Assignee: Hitachi, Ltd.Inventors: Keiichi Yamamoto, Norio Chujo, Toru Yazaki, Hisaaki Kanai
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Publication number: 20110026878Abstract: In fabricating an optical I/O array module, an optical waveguide provided with mirror parts, each having a tapered face, is formed on a substrate, a convex shaped member or a concave shaped member is placed at spots above the respective mirror parts of the optical waveguide, and laser diode arrays and photo diode arrays, provided with either a concave shape, or a convex shape, are mated with, or into the convex shaped member or the concave shaped member before being mounted. Further, there are formed multiple filmy layers, on which an LSI where a driver IC LSI of optical elements, and an amplifier LSI of the optical elements are integrated.Type: ApplicationFiled: July 27, 2010Publication date: February 3, 2011Applicant: Hitachi, Ltd.Inventors: Yasunobu MATSUOKA, Toshiki Sugawara, Koichiro Adachi, Naoki Matsushima, Saori Hamamura, Madoka Minagawa, Norio Chujo