Patents by Inventor Norio Hasegawa

Norio Hasegawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7489907
    Abstract: A transmitter for averagedly suppressing the variation in input level of an amplifier according to variation in carrier level. The transmitter includes an input power calculation section for calculating mean input power of each carrier, an output power calculating section for calculating mean output power of each carrier after the carrier band is limited, a monitoring section for identifying a carrier having the maximum mean input power, acquiring the maximum value, acquiring the mean output power of the identified carrier, determining the ratio of the mean input power to the mean output power, and calculating level control information which is the ratio of the ratio determined above to a predetermined expected value, and a signal level adjusting section for adjusting the level of a multicarrier signal by multiplying the level control information outputted from the monitoring section.
    Type: Grant
    Filed: October 20, 2003
    Date of Patent: February 10, 2009
    Assignee: Hitachi Kokusai Electric Inc.
    Inventors: Norio Hasegawa, Tetsuhiko Miyatani, Hisashi Kawai, Masami Yoshida, Jun Watanabe
  • Publication number: 20080200126
    Abstract: In a transmitter that suppresses the peak level of a multi-carrier signal produced by synthesizing a plurality of carrier signals, high signal quality is maintained for any transmission signal pattern, for example. In a peak power suppression means shown in the drawings, suppression signal generation means 7 to 18 generate a peak level suppression signal having a level according to levels of respective carrier signals for frequencies of the respective carrier signals contained in the multi-carrier signal. Suppression signal subtraction means 19, 20 subtract, from the multi-carrier signal, the peak level suppression signal generated by the suppression signal generation means 7 to 18.
    Type: Application
    Filed: February 13, 2008
    Publication date: August 21, 2008
    Inventors: Takashi Okada, Jun Watanabe, Takahiro Todate, Norio Hasegawa
  • Patent number: 7387867
    Abstract: In a massed region of each of a plurality of transfer areas of a mask a plurality of light transmission patterns are formed by opening a half-tone film. A phase shifter is disposed in each of the light transmission patterns so that a 180° phase inversion occurs between the lights that transmit through adjacent light transmission patterns. In a sparse region of the plurality of transfer areas a solitary light transmission pattern is formed by opening the half-tone film. Both shape and size are the same among the light transmission patterns, which are disposed symmetrically in both the massed and sparse regions about the center between the transfer areas. The phase shifters in the massed regions are disposed so that the phase of each phase shifter in one of the transfer areas comes to be opposed to that of its counterpart in the other transfer area. In the exposure process, those transfer areas are overlaid one upon another in the same chip region.
    Type: Grant
    Filed: October 19, 2004
    Date of Patent: June 17, 2008
    Assignee: Hitachi, Ltd.
    Inventors: Norio Hasegawa, Katsuya Hayano, Shoji Hotta
  • Patent number: 7361530
    Abstract: Productivity of a semiconductor integrated circuit device is improved. According to how many times the photomask is used, a photomask having an opaque pattern made of metal and a photomask having an opaque pattern made of a resist film are properly used, and thereby an exposure treatment is performed.
    Type: Grant
    Filed: March 7, 2007
    Date of Patent: April 22, 2008
    Assignee: Renesas Technology Corporation
    Inventors: Tsuneo Terasawa, Toshihiko Tanaka, Ko Miyazaki, Norio Hasegawa, Kazutaka Mori
  • Publication number: 20080057408
    Abstract: A semitransparent phase shifting mask has, in the periphery of a pattern element area, a light shielding portion which is formed by a semitransparent phase shifting portion and a transparent portion with the optimal size combination. A pattern is formed employing the semitransparent phase shifting mask.
    Type: Application
    Filed: March 16, 2005
    Publication date: March 6, 2008
    Inventors: Norio Hasegawa, Fumio Murai, Katsuya Hayano
  • Patent number: 7252910
    Abstract: A mask fabrication time is shortened. By patterning an electron-sensitive resist film coated on a main surface of a mask substrate, a pellicle is mounted on the main surface of the mask substrate immediately after a resist pattern made from an electron beam sensitive resist film and having light-shielding characteristics with respect to exposure light is formed. Subsequently, by irradiating a laser beam to defect made from the electron beam sensitive resist film with the pellicle being mounted on the mask substrate, the defect is removed. Since the defect can be removed without removing the pellicle, the mask fabrication time can be shortened.
    Type: Grant
    Filed: January 23, 2004
    Date of Patent: August 7, 2007
    Assignees: Renesas Technology Corp., Dai Nippon Printing Co., Ltd.
    Inventors: Norio Hasegawa, Katsuya Hayano, Shinji Kubo, Yasuhiro Koizumi, Yasushi Kawai
  • Publication number: 20070155052
    Abstract: Productivity of a semiconductor integrated circuit device is improved. According to how many times the photomask is used, a photomask having an opaque pattern made of metal and a photomask having an opaque pattern made of a resist film are properly used, and thereby an exposure treatment is performed.
    Type: Application
    Filed: March 7, 2007
    Publication date: July 5, 2007
    Inventors: Tsuneo Terasawa, Toshihiko Tanaka, Ko Miyazaki, Norio Hasegawa, Kazutaka Mori
  • Publication number: 20070128556
    Abstract: To alleviate the absolute value control accuracy of phases in a mask having a groove shifter structure, transfer regions formed at different planar positions on the same plane of the same mask are subjected to a multiple exposure by scanning exposure. Although. identical mask patterns are formed over the transfer regions respective groove shifters provided to these mask patterns are arranged opposite from each other.
    Type: Application
    Filed: January 11, 2007
    Publication date: June 7, 2007
    Inventors: Norio Hasegawa, Akira Imai, Katsuya Hayano
  • Patent number: 7205222
    Abstract: Productivity of a semiconductor integrated circuit device is improved. According to how many times the photomask is used, a photomask having an opaque pattern made of metal and a photomask having an opaque pattern made of a resist film are properly used, and thereby an exposure treatment is performed.
    Type: Grant
    Filed: December 28, 2004
    Date of Patent: April 17, 2007
    Assignee: Renesas Technology Corp.
    Inventors: Tsuneo Terasawa, Toshihiko Tanaka, Ko Miyazaki, Norio Hasegawa, Kazutaka Mori
  • Publication number: 20070051777
    Abstract: This invention provides a soldering method capable of solving soldering defects due to excess molten solder in the case of soldering while applying an inner pressure into a through-hole of a lead component mounting substrate: (a) In a primary soldering step, a lead component mounting substrate is lowered, and the rear surface thereof is put close to or brought into close contact with an upper end opening edge of a nozzle. Simultaneously, the soldering surface of the molten solder supplied to the nozzle is elevated. (b) In a secondary soldering step, the rear surface of the lead component mounting substrate is relatively spaced from the soldering surface of molten solder by lowering the soldering surface. (c) In a lead separating step, the lead component mounting substrate is elevated while tilting the lead component mounting substrate.
    Type: Application
    Filed: September 5, 2006
    Publication date: March 8, 2007
    Applicants: TAMURA CORPORATION, TAMURA FA SYSTEM CORPORATION, HITACHI, LTD.
    Inventors: Takahito Yamaguchi, Norio Hasegawa, Toru Kato, Hideki Mukuno, Masahiko Asano
  • Patent number: 7172853
    Abstract: To alleviate the absolute value control accuracy of phases in a mask having a groove shifter structure, transfer regions formed at different planar positions on the same plane of the same mask are subjected to a multiple exposure by scanning exposure. Although identical mask patterns are formed over the transfer regions respective groove shifters provided to these mask patterns are arranged opposite from each other.
    Type: Grant
    Filed: February 4, 2004
    Date of Patent: February 6, 2007
    Assignee: Renesas Technology Corp.
    Inventors: Norio Hasegawa, Akira Imai, Katsuya Hayano
  • Patent number: 7125651
    Abstract: In order to suppress or prevent the occurrence of foreign matter in the manufacture of a semiconductor integrated circuit device by the use of a photo mask constituted in such a manner that a resist film is made to function as a light screening film, inspection or exposure treatment is carried out, when the photo mask 1PA1 has been mounted on a predetermined apparatus such as, e.g., an inspection equipment or aligner, in the state in which a mounting portion 2 of the predetermined apparatus is contacted with that region of a major surface of a mask substrate 1a of the photo mask 1PA1 in which a light shielding pattern 1b and a mask pattern 1mr, each formed of a resist film, on the major surface of the mask substrate 1a do not exist.
    Type: Grant
    Filed: October 1, 2003
    Date of Patent: October 24, 2006
    Assignee: Renesas Technology Corp.
    Inventors: Norio Hasegawa, Tsuneo Terasawa, Toshihiko Tanaka
  • Patent number: 7115344
    Abstract: A semitransparent phase shifting mask has, in the periphery of a pattern element area, a light shielding portion which is formed by a semitransparent phase shifting portion and a transparent portion with the optimal size combination. A pattern is formed employing the semitransparent phase shifting mask.
    Type: Grant
    Filed: February 13, 2004
    Date of Patent: October 3, 2006
    Assignee: Renesas Technology Corp.
    Inventors: Norio Hasegawa, Fumio Murai, Katsuya Hayano
  • Publication number: 20060189282
    Abstract: A transmitter for averagedly suppressing the variation in input level of an amplifier according to variation in carrier level. The transmitter comprises an input power calculation section (16) for calculating mean input power of each carrier, an output power calculating section (17) for calculating mean output power of each carrier after the carrier band is limited, a monitoring section (18) for identifying a carrier having the maximum mean input power, acquiring the maximum value, acquiring the mean output power of the identified carrier, determining the ratio of the mean input power to the mean output power, and calculating level control information which is the ratio of the ratio determined above to a predetermined expected value, and a signal level adjusting section (15) for adjusting the level of a multicarrier signal by multiplying the level control information outputted from the monitoring section (18).
    Type: Application
    Filed: October 20, 2003
    Publication date: August 24, 2006
    Inventors: Norio Hasegawa, Tetsuhiko Miyatani, Hisashi Kawai, Masami Yoshida, Jun Watanabe
  • Publication number: 20060171254
    Abstract: An image data processing device has an image identifying unit and a file generating unit. The image identifying unit identifies a common image that is common to each page and a non-common image that differs from page to page on the basis of inputted image data including a plurality of pages. The file generating unit generates separate files of the common image and the non-common image.
    Type: Application
    Filed: December 12, 2005
    Publication date: August 3, 2006
    Applicant: FUJI XEROX CO., LTD.
    Inventors: Ayumi Onishi, Nobuo Inoue, Minoru Sodeura, Masataka Kamiya, Junji Kannari, Sadao Furuoya, Norio Hasegawa
  • Publication number: 20060160054
    Abstract: An automatic grading method has processes of reading, identifying and calculating. A process of reading a document is performed and the document has one or more answers. A process of identifying the answers from the document is also performed. A process of calculating a score of the document based on a score of each answer is performed.
    Type: Application
    Filed: December 12, 2005
    Publication date: July 20, 2006
    Applicant: FUJI XEROX CO., LTD.
    Inventors: Ayumi Onishi, Nobuo Inoue, Minoru Sodeura, Masataka Kamiya, Junji Kannari, Sadao Furuoya, Norio Hasegawa
  • Publication number: 20060110667
    Abstract: An area for fabricating a photomask having light-shielding patterns each formed of an organic film, and areas for fabricating a semiconductor integrated circuit device are provided within the same clean room. A manufacturing device and an inspecting device are commonly used during the fabrication of the photomask and the fabrication of the semiconductor integrated circuit device.
    Type: Application
    Filed: January 3, 2006
    Publication date: May 25, 2006
    Inventors: Norio Hasegawa, Toshihiko Tanaka, Tsuneo Terasawa, Aritoshi Sugimoto
  • Patent number: 7042038
    Abstract: An active region (L) with a metal insulator semiconductor field effect transistor (MISFET) (Qs) formed therein for selection of a DRAM memory cell, which makes up a memory cell of the DRAM, is arranged to have an island-like pattern that linearly extends in an X direction on one principal surface of a semiconductor substrate (1). The memory-cell selection MISFET (Qs) has an insulated gate electrode (7) (word line WL) that extends along a Y direction on the principal surface of the semiconductor substrate (1) with the same width kept along the length thereof, which gate electrode is arranged to oppose another gate electrode (7) (word line WL) adjacent thereto at a prespecified distance or pitch that is narrower than said width.
    Type: Grant
    Filed: September 4, 2003
    Date of Patent: May 9, 2006
    Assignee: Hitachi, Ltd.
    Inventors: Makoto Yoshida, Takahiro Kumauchi, Yoshitaka Tadaki, Isamu Asano, Norio Hasegawa, Keizo Kawakita
  • Patent number: 7001712
    Abstract: Densely disposed patterns constituting a semiconductor integrated circuit device are divided into a first mask pattern and a second mask pattern 28B such that a phase shifter S can be disposed, and a predetermined pattern is transferred on a semiconductor substrate by multiple-exposure thereof. The second mask pattern 28B has a main light transferring pattern 26c1, a plurality of auxiliary light transferring patterns 26c2 disposed thereabout, and a phase shifter S disposed in the main light transferring pattern 26c1. The auxiliary light transferring patterns 26c2 are disposed such that respective distances from a center of each thereof to a center of the main light transferring pattern 26c1 are substantially equal. With this arrangement, a densely disposed pattern is transferred with sufficient process transfer margin.
    Type: Grant
    Filed: July 22, 2003
    Date of Patent: February 21, 2006
    Assignee: Renesas Technology Corp.
    Inventors: Akira Imai, Katsuya Hayano, Norio Hasegawa
  • Patent number: 6986952
    Abstract: A chemical compound capable of emitting visible light and having electrical conductivity comprises a main chain that consists of at least one substituted or non-substituted 2,5-thiophenediyl group and at least one substituted or non-substituted 9-carbazolyl group that bonds to at least one of two terminals of the main chain. The chemical compound is used in a luminescent material, an EL device that includes a luminous layer, and a display apparatus that includes a plurality of EL devices.
    Type: Grant
    Filed: June 10, 2003
    Date of Patent: January 17, 2006
    Assignee: Mitsumi Electric Co., Ltd.
    Inventors: Youichi Itagaki, Norio Hasegawa