Patents by Inventor Norio Hasegawa

Norio Hasegawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20050277065
    Abstract: By using a high-accuracy mask capable of being manufactured through a simplified step, a semiconductor device manufacturing method of forming a desired pattern over a wafer is provided. A relatively narrow groove pattern and a groove pattern wider than the narrow groove pattern are formed, and a shade film made of, for example, a resist film is formed in the relatively wide groove pattern. As a concrete method of manufacturing a mask, after applying a resist film onto the quartz glass substrate, exposure and developing processings are performed, whereby the resist film is patterned. The patterned resist film is used as a mask to form the groove patterns in the quartz glass substrate (dry etching). Subsequently, after removing the patterned resist film, a new resist film is applied. Then, patterning is performed to form the shade film only in the groove pattern.
    Type: Application
    Filed: June 8, 2005
    Publication date: December 15, 2005
    Inventors: Norio Hasegawa, Katsuya Hayano
  • Patent number: 6958292
    Abstract: In order to shorten the period for the development and manufacture of a semiconductor integrated circuit device, at the time of transferring integrated circuit patterns onto a wafer by an exposure process, a photomask PM1 is used which is provided partially with light shielding patterns 3a formed of a resist film, in addition to light shielding patterns formed of a metal.
    Type: Grant
    Filed: February 12, 2003
    Date of Patent: October 25, 2005
    Assignee: Renesas Technology Corp.
    Inventors: Norio Hasegawa, Joji Okada, Toshihiko Tanaka, Kazutaka Mori, Ko Miyazaki
  • Publication number: 20050208427
    Abstract: A semiconductor device manufacturing method which shortens the turnaround time for semiconductor devices. In this method, shading material of resist film lies over a main surface of mask blanks and light-transmitting patterns are made as openings in the shading material. A planarizing film is formed so as to cover the shading material and phase shifters of resist film are formed on the flat top surface of the planarizing film. For exposure, pattern is used. Multiple exposure with two or more exposure areas is made in one chip area, where the exposure areas have patterns equal in shape, size, and arrangement, and phase shifters arranged alternately, so that a line pattern is transferred onto a positive type photoresist film of a semiconductor wafer.
    Type: Application
    Filed: January 7, 2005
    Publication date: September 22, 2005
    Inventors: Katsuya Hayano, Norio Hasegawa
  • Patent number: 6939649
    Abstract: A method of fabrication of a semiconductor integrated circuit device uses a mark having, on a first main surface of a mask substrate, a first light transmitting region, a second light transmitting region disposed at the periphery of the first light transmitting region and permitting inversion of the phase of light transmitted through the second light transmitting region relative to light transmitted through the first light transmitting region, and a light shielding region disposed at the periphery of the second light transmitting region. The second light transmitting region is formed from a first film deposited over the first main surface of the mask substrate, said light shielding region is formed by a second film deposited over the first main surface of the mask substrate via said first film, and at least one of said first film and second is formed from a resist film.
    Type: Grant
    Filed: September 30, 2002
    Date of Patent: September 6, 2005
    Assignee: Renesas Technology Corp.
    Inventors: Shoji Hotta, Norio Hasegawa, Toshihiko Tanaka
  • Patent number: 6936406
    Abstract: In order to shorten the period for the development and manufacture of a semiconductor integrated circuit device, at the time of transferring integrated circuit patterns onto a wafer by an exposure process, a photomask PM1 is used which is provided partially with light shielding patterns 3a formed of a resist film, in addition to light shielding patterns formed of a metal.
    Type: Grant
    Filed: February 12, 2003
    Date of Patent: August 30, 2005
    Assignee: Renesas Technology Corp.
    Inventors: Norio Hasegawa, Joji Okada, Toshihiko Tanaka, Kazutaka Mori, Ko Miyazaki
  • Publication number: 20050158638
    Abstract: A semitransparent phase shifting mask has, in the periphery of a pattern element area, a light shielding portion which is formed by a semitransparent phase shifting portion and a transparent portion with the optimal size combination. A pattern is formed employing the semitransparent phase shifting mask.
    Type: Application
    Filed: March 16, 2005
    Publication date: July 21, 2005
    Inventors: Norio Hasegawa, Fumio Murai, Katsuya Hayano
  • Patent number: 6902868
    Abstract: In order to shorten the period for the development and manufacture of a semiconductor integrated circuit device, at the time of transferring integrated circuit patterns onto a wafer by an exposure process, a photomask PM1 is used which is provided partially with a light shielding patterns 3a formed of a resist film, in addition to light shielding patterns formed of a metal.
    Type: Grant
    Filed: June 28, 2001
    Date of Patent: June 7, 2005
    Assignee: Renesas Technology Corp.
    Inventors: Norio Hasegawa, Joji Okada, Toshihiko Tanaka, Kazutaka Mori, Ko Miyazaki
  • Publication number: 20050112504
    Abstract: Productivity of a semiconductor integrated circuit device is improved. According to how many times the photomask is used, a photomask having an opaque pattern made of metal and a photomask having an opaque pattern made of a resist film are properly used, and thereby an exposure treatment is performed.
    Type: Application
    Filed: December 28, 2004
    Publication date: May 26, 2005
    Inventors: Tsuneo Terasawa, Toshihiko Tanaka, Ko Miyazaki, Norio Hasegawa, Kazutaka Mori
  • Patent number: 6893801
    Abstract: On the occasion of the aligning process to transfer a predetermined pattern to a semiconductor wafer by irradiating a photoresist on the semiconductor wafer with an aligning laser beam of the modified lighting via a photomask MK, the photomask MK allocating, to provide periodicity, the main apertures to transfer the predetermined pattern as the apertures formed by removing a part of the half-tone film on the mask substrate and the auxiliary apertures not resolved on the semiconductor wafer as the apertures formed by removing a part of the half-tone film is used to improve the resolution of the pattern.
    Type: Grant
    Filed: January 9, 2004
    Date of Patent: May 17, 2005
    Assignee: Renesas Technology Corp.
    Inventors: Osamu Inoue, Norio Hasegawa, Shuji Ikeda
  • Patent number: 6893785
    Abstract: A method of manufacturing an electronic device, such as a high-speed semiconductor integrated circuit device, provides improved dimensional accuracy in transferring fine patterns. Photolithography for gate patterns and wiring patterns is carried out by exposing a halftone phase-shift mask having shade areas made of resist with an oblique illumination system, and photolithography for contact hole patterns is carried out by using a photomask having a metal shade film with metal alignment wafer marks.
    Type: Grant
    Filed: October 15, 2003
    Date of Patent: May 17, 2005
    Assignee: Hitachi, Ltd.
    Inventors: Toshihiko Tanaka, Norio Hasegawa
  • Publication number: 20050090120
    Abstract: In a massed region of each of a plurality of transfer areas of a mask a plurality of light transmission patterns are formed by opening a half-tone film. A phase shifter is disposed in each of the light transmission patterns so that a 180° phase inversion occurs between the lights that transmit through adjacent light transmission patterns. In a sparse region of the plurality of transfer areas a solitary light transmission pattern is formed by opening the half-tone film. Both shape and size are the same among the light transmission patterns, which are disposed symmetrically in both the massed and sparse regions about the center between the transfer areas. The phase shifters in the massed regions are disposed so that the phase of each phase shifter in one of the transfer areas comes to be opposed to that of its counterpart in the other transfer area. In the exposure process, those transfer areas are overlaid one upon another in the same chip region.
    Type: Application
    Filed: October 19, 2004
    Publication date: April 28, 2005
    Inventors: Norio Hasegawa, Katsuya Hayano, Shoji Hotta
  • Publication number: 20050063485
    Abstract: A transmitter that effectively suppresses the peak level of transmit signals is equipped with peak reduction signal generating means that generates a peak reduction signal having a level based on a transmit signal level threshold for determining a peak of the transmit signal and on a transmit signal peak level and having a phase based on the phase of the transmit signal, peak reduction signal processing means that subjects the peak reduction signal to band restriction and orthogonal modulation, and transmit signal level suppressing means that subtracts the peak reduction signal subjected to band restriction and orthogonal modulation from the transmit signal.
    Type: Application
    Filed: September 15, 2004
    Publication date: March 24, 2005
    Inventors: Norio Hasegawa, Tetsuhiko Miyatani, Yoshihiko Akaiwa
  • Patent number: 6849540
    Abstract: Productivity of a semiconductor integrated circuit device is improved. According to how many times the photomask is used, a photomask having an opaque pattern made of metal and a photomask having an opaque pattern made of a resist film are properly used, and thereby an exposure treatment is performed.
    Type: Grant
    Filed: August 15, 2001
    Date of Patent: February 1, 2005
    Assignee: Renesas Technology Corp.
    Inventors: Tsuneo Terasawa, Toshihiko Tanaka, Ko Miyazaki, Norio Hasegawa, Kazutaka Mori
  • Patent number: 6846598
    Abstract: In order to shorten the time required to change or correct a mask pattern over a mask, light-shielding patterns formed of a resist film for integrated circuit pattern transfer are partly provided over a mask substrate constituting a photomask in addition to light-shielding patterns formed of a metal for the integrated circuit pattern transfer.
    Type: Grant
    Filed: October 17, 2003
    Date of Patent: January 25, 2005
    Assignee: Hitachi, Ltd.
    Inventors: Norio Hasegawa, Toshihiko Tanaka, Joji Okada, Kazutaka Mori, Ko Miyazaki
  • Patent number: 6841399
    Abstract: The manufacturing time of a mask is shortened. In a defect inspection of a mask having a light-shielding portion composed of a resist film, the presence or absence of defects, such as burr and film loss of a resist pattern on the mask, and foreign matters, etc. is inspected by reading optical information on either or both of reflection light and transmission light with respect to inspection light irradiated to the mask by the use of a foreign-matter inspection system. More specifically, in the inspection of the mask, it is possible to perform the defect inspection without performing a comparison inspection that requires a great amount of measuring time and advanced techniques. Therefore, the inspecting process of the mask can be simplified, and also the inspecting time of the mask can be shortened.
    Type: Grant
    Filed: January 23, 2003
    Date of Patent: January 11, 2005
    Assignees: Renesas Technology Corp., Dai Nippon Printing Co., Ltd.
    Inventors: Norio Hasegawa, Katsuya Hayano, Shinji Kubo, Yasuhiro Koizumi, Hironobu Takaya, Morihisa Hoga
  • Patent number: 6824958
    Abstract: Disclosed is a technique capable of reducing the manufacturing time of a photomask. In a method of transferring a predetermined pattern onto a semiconductor wafer by reduced projection exposure using a product mask manufactured by performing the reduced projection exposure to a pattern of an IP mask Mm1, the IP mask Mm1 is designed to have a resist mask structure in which a light-shielding pattern thereof is constituted of an organic film such as a resist film.
    Type: Grant
    Filed: December 26, 2001
    Date of Patent: November 30, 2004
    Assignee: Renesas Technology Corp.
    Inventors: Katsuya Hayano, Norio Hasegawa
  • Patent number: 6800421
    Abstract: In order to shorten the time needed for fabricating semiconductor integrated circuit devices, a wafer is exposed while a chip area with defects of a mask is covered with a masking blade for light shielding.
    Type: Grant
    Filed: November 30, 2001
    Date of Patent: October 5, 2004
    Assignee: Renesas Technology Corp.
    Inventors: Norio Hasegawa, Toshihiko Tanaka
  • Patent number: 6794207
    Abstract: In order to shorten the period for the development and manufacture of a semiconductor integrated circuit device, at the time of transferring integrated circuit patterns onto a wafer by an exposure process, a photomask PM1 is used which is provided partially with light shielding patterns 3a formed of a resist film, in addition to light shielding patterns formed of a metal.
    Type: Grant
    Filed: February 12, 2003
    Date of Patent: September 21, 2004
    Assignee: Renesas Technology Corp.
    Inventors: Norio Hasegawa, Joji Okada, Toshihiko Tanaka, Kazutaka Mori, Ko Miyazaki
  • Publication number: 20040166363
    Abstract: A chemical compound capable of emitting visible light and having electrical conductivity comprises a main chain that consists of at least one substituted or non-substituted 2,5-thiophenediyl group and at least one substituted or non-substituted 9-carbazolyl group that bonds to at least one of two terminals of the main chain. The chemical compound is used in a luminescent material, an EL device that includes a luminous layer, and a display apparatus that includes a plurality of EL devices.
    Type: Application
    Filed: June 10, 2003
    Publication date: August 26, 2004
    Applicant: MITSUMI ELECTRIC CO., LTD.
    Inventors: Youichi Itagaki, Norio Hasegawa
  • Publication number: 20040161707
    Abstract: A semitransparent phase shifting mask has, in the periphery of a pattern element area, a light shielding portion which is formed by a semitransparent phase shifting portion and a transparent portion with the optimal size combination. A pattern is formed employing the semitransparent phase shifting mask.
    Type: Application
    Filed: February 13, 2004
    Publication date: August 19, 2004
    Applicant: RENESAS TECHNOLOGY CORP.
    Inventors: Norio Hasegawa, Fumio Murai, Katsuya Hayano