Patents by Inventor Norio Suzuki

Norio Suzuki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20050260911
    Abstract: The present invention provides a nanoporous fiber being substantially free from coarse pores and having homogeneously dispersed nanopores, unlike conventional porous fibers. A porous fiber has pores each having a diameter of 100 nm or less, in which the area ratio of pores each having a diameter of 200 nm or more to the total cross section of the fiber is 1.5% or less, and the pores are unconnected pores, or a porous fiber has pores each having a diameter of 100 nm or less, in which the area ratio of pores each having a diameter of 200 nm or more to the total cross section of the fiber is 1.5% or less, the pores are connected pores, and the fiber has a strength of 1.0 cN/dtex or more.
    Type: Application
    Filed: July 28, 2003
    Publication date: November 24, 2005
    Inventors: Takashi Ochi, Akira Kishiro, Shuichi Nonaka, Takaaki Mihara, Norio Suzuki
  • Patent number: 6967141
    Abstract: A semiconductor integrated circuit device and a method of manufacturing the same. The surface of a substrate of an active region surrounded by an element isolation trench is horizontally flat in the center portion of the active region but falls toward the side wall of the element isolation trench in the shoulder portion of the active region. This inclined surface contains two inclined surfaces having different inclination angles. The first inclined surface near the center portion of the active region is relatively steep and the second inclined surface near the side wall of the element isolation trench is gentler than the first inclined surface. The surface of the substrate in the shoulder portion of the active region is wholly rounded and has no angular portion.
    Type: Grant
    Filed: August 17, 2004
    Date of Patent: November 22, 2005
    Assignee: Renesas Technology Corp.
    Inventors: Kenji Kanamitsu, Kouzou Watanabe, Norio Suzuki, Norio Ishitsuka
  • Publication number: 20050245045
    Abstract: A method for manufacturing a semiconductor integrated circuit device including a first field effect transistor having a gate insulating film formed over a first element forming region of a main surface of a semiconductor substrate; and a second field effect transistor having a gate insulating film formed over a second element forming region of the main surface of the semiconductor substrate and made thinner than the gate insulating film of the first field effect transistor.
    Type: Application
    Filed: July 12, 2005
    Publication date: November 3, 2005
    Inventors: Shoji Shukuri, Norio Suzuki, Yasuhiro Taniguchi
  • Publication number: 20050237603
    Abstract: A method for manufacturing a semiconductor integrated circuit device includes the steps of forming an isolation trench in an isolation region of a semiconductor substrate, filling the isolation trench up to predetermined middle position in its depth direction with a first insulating film deposited by a coating method, filling a remaining depth portion of the isolation trench into which the first insulating film is filled with a second insulating film, then forming a plurality of patterns on the semiconductor substrate, filling a trench forming between the plurality of patterns up to predetermined middle position in a trench depth direction with a third insulating film deposited by a coating method, and filling a remaining portion of the trench into which the third insulating film is filled with a fourth insulating film that is more difficult to etch than the third insulating film.
    Type: Application
    Filed: June 10, 2005
    Publication date: October 27, 2005
    Inventors: Hidenori Sato, Norio Suzuki, Akira Takamatsu, Hiroyuki Maruyama, Takeshi Saikawa, Katsuhiko Hotta, Hiroyuki Ichizoe
  • Publication number: 20050239257
    Abstract: A method for manufacturing a semiconductor integrated circuit device includes the steps of forming an isolation trench in an isolation region of a semiconductor substrate, filling the isolation trench up to predetermined middle position in its depth direction with a first insulating film deposited by a coating method, filling a remaining depth portion of the isolation trench into which the first insulating film is filled with a second insulating film, then forming a plurality of patterns on the semiconductor substrate, filling a trench forming between the plurality of patterns up to predetermined middle position in a trench depth direction with a third insulating film deposited by a coating method, and filling a remaining portion of the trench into which the third insulating film is filled with a fourth insulating film that is more difficult to etch than the third insulating film.
    Type: Application
    Filed: June 10, 2005
    Publication date: October 27, 2005
    Inventors: Hidenori Sato, Norio Suzuki, Akira Takamatsu, Hiroyuki Maruyama, Takeshi Saikawa, Katsuhiko Hotta, Hiroyuki Ichizoe
  • Publication number: 20050220856
    Abstract: A phospholipid derivative represented by the formula (1) (Z represents a residue of a compound having 3 to 10 hydroxyl groups; AO represents an oxyalkylene group having 2 to 4 carbon atoms; R1CO and R2CO represent an acyl group having 8 to 22 carbon atoms; X represents hydrogen atom, an alkali metal atom, ammonium or an organic ammonium; “a” represents an integer of 0 to 4; “b” represents 0 or 1; Q represents hydrogen atom or methyl group; m represents an average number of moles of the oxyalkylene group added; and m, k1, k2, and k3 are numbers satisfying the following conditions: 3?m?200, 9?m×(k1+k2+k3)?1000, 1?k1?2, 0?k2?9 and 0?k3?9, and 3?k1+k2+k3?10), which is highly safe for living bodies, and is suitably used for solubilization and dispersion of physiologically active substances and the like, or in the fields of drug delivery systems such as liposomes and cosmetics.
    Type: Application
    Filed: March 28, 2003
    Publication date: October 6, 2005
    Inventors: Chika Itoh, Kazuhiro Kubo, Syunsuke Ohhashi, Tohru Yasukohchi, Hiroshi Kikuchi, Norio Suzuki, Miho Kurosawa, Hitoshi Yamauchi
  • Publication number: 20050196935
    Abstract: A process of producing a semiconductor device having a highly reliable groove isolation structure with a desired radius of curvature formed at the groove upper edge and without formation of any step. The device is produced by reducing the stress generation around the groove upper edge of an element isolation groove on a semiconductor substrate, thereby optimizing the shape of an element isolation groove and making the device finer and improving the device electric characteristics.
    Type: Application
    Filed: April 19, 2005
    Publication date: September 8, 2005
    Inventors: Norio Ishitsuka, Hideo Miura, Shuji Ikeda, Norio Suzuki, Yasushi Matsuda, Yasuko Yoshida, Hirohiko Yamamoto, Masamichi Kobayashi, Akira Takamatsu, Hirofumi Shimizu, Kazushi Fukuda, Shinichi Horibe, Toshio Nozoe
  • Publication number: 20050187249
    Abstract: The present invention relates to an aqueous solution containing a physiologically active substance which may have a substituent and which has an amidino group, wherein the pH of the solution is higher than 2 and equal to or lower than 4. The invention also relates to a lyophilized product obtained by drying the solution, to an injection containing the aqueous solution or the lyophilized product, and to an injection kit.
    Type: Application
    Filed: May 13, 2003
    Publication date: August 25, 2005
    Applicant: Daiichi Pharmaceutical Co., Ltd.
    Inventors: Yoshimine Fuji, Norio Suzuki
  • Publication number: 20050178109
    Abstract: An exhaust gas purifying apparatus for an internal combustion engine having an exhaust system. The apparatus includes a NOx purifying device provided in the exhaust system. This device removes NOx from exhaust gases when a concentration of oxygen in the exhaust gases is higher than a concentration of reducing components in the exhaust gases; generates ammonia and retains the generated ammonia when the concentration of reducing components in the inflowing exhaust gases is higher than the concentration of oxygen; and purifies NOx with the retained ammonia when the concentration of reducing components in the inflowing exhaust gases is lower than the concentration of oxygen. A residual amount of ammonia retained in the NOx purifying device is estimated. The concentration of reducing components in the exhaust gases is switched with respect to the concentration of oxygen according to the estimated residual amount.
    Type: Application
    Filed: February 1, 2005
    Publication date: August 18, 2005
    Inventors: Katsuji Wada, Hiroshi Ohno, Norio Suzuki, Tomoko Morita
  • Publication number: 20050166579
    Abstract: An exhaust gas purifying apparatus for an internal combustion engine having an exhaust system. The exhaust gas purifying apparatus includes a NOx purifying device provided in the exhaust system for purifying NOx in exhaust gases, and a temperature sensor for detecting a temperature of the NOx purifying device. The NOx purifying device has NOx absorbing capacity and generates ammonia and retains the generated ammonia when the air-fuel ratio is set to a value on the rich side with respect to the stoichiometric ratio. The NOx purifying device purifies NOx with the retained ammonia when the air-fuel ratio is set to a value on a lean side with respect to the stoichiometric ratio. The air-fuel ratio is enriched to a value on the rich side with respect to the stoichiometric ratio so as to increase an amount of reducing components in the exhaust gases flowing into the NOx purifying device.
    Type: Application
    Filed: December 16, 2004
    Publication date: August 4, 2005
    Inventors: Norio Suzuki, Katsuji Wada
  • Publication number: 20050148155
    Abstract: A method for manufacturing a semiconductor integrated circuit device includes the steps of forming an isolation trench in an isolation region of a semiconductor substrate, filling the isolation trench up to predetermined middle position in its depth direction with a first insulating film deposited by a coating method, filling a remaining depth portion of the isolation trench into which the first insulating film is filled with a second insulating film, then forming a plurality of patterns on the semiconductor substrate, filling a trench forming between the plurality of patterns up to predetermined middle position in a trench depth direction with a third insulating film deposited by a coating method, and filling a remaining portion of the trench into which the third insulating film is filled with a fourth insulating film that is more difficult to etch than the third insulating film.
    Type: Application
    Filed: February 11, 2005
    Publication date: July 7, 2005
    Inventors: Hidenori Sato, Norio Suzuki, Akira Takamatsu, Hiroyuki Maruyama, Takeshi Saikawa, Katsuhiko Hotta, Hiroyuki Ichizoe
  • Patent number: 6902788
    Abstract: The present invention provides a heat-insulating structure using a fluff-like heat-insulating material such as cellulose insulation fibers, capable of allowing convenient handling and preventing a so-called settling-down phenomenon in which the top of the heat-insulating material will settle down with time. The heat-insulating structure comprises a plurality of strap-shaped partition members 2 arranged to define an array of heat-insulating segments therebetween, and cellulose insulation fibers filled in each of the heat-insulating segments. A surface member 3 such as an underlying member or a facing member may be adhesively attached to the exposed surface of the interleaved structure of the partition members and the heat-insulating segments filled with the cellulose insulation fibers to provide a discrete heat-insulating panel.
    Type: Grant
    Filed: July 25, 2002
    Date of Patent: June 7, 2005
    Assignee: Hikari Toshi Sougou Sekkei
    Inventor: Norio Suzuki
  • Patent number: 6883496
    Abstract: In the event that an abnormality is detected in a throttle valve driving apparatus, an upper limit value for a throttle valve opening is set according to a vehicle speed when a brake switch is not switched on. When the brake switch is on, the upper limit value is set at a predetermined idle opening. When the target opening which is calculated according to an accelerator pedal depression amount is larger than the upper limit value, the target opening is changed to the upper limit value.
    Type: Grant
    Filed: July 8, 2003
    Date of Patent: April 26, 2005
    Assignee: Honda Giken Kogyo Kabushiki Kaisha
    Inventors: Norio Suzuki, Yosuke Tachibana, Jun Takahashi
  • Patent number: 6881646
    Abstract: A process of producing a semiconductor device having a highly reliable groove isolation structure with a desired radius of curvature formed at the groove upper edge and without formation of any step. The device is produced by reducing the stress generation around the groove upper edge of an element isolation groove on a semiconductor substrate, thereby optimizing the shape of an element isolation groove and making the device finer and improving the device electric characteristics.
    Type: Grant
    Filed: March 21, 2003
    Date of Patent: April 19, 2005
    Assignees: Renesas Technology Corp., Hitachi ULSI Systems Co., Ltd.
    Inventors: Norio Ishitsuka, Hideo Miura, Shuji Ikeda, Norio Suzuki, Yasushi Matsuda, Yasuko Yoshida, Hirohiko Yamamoto, Masamichi Kobayashi, Akira Takamatsu, Hirofumi Shimizu, Kazushi Fukuda, Shinichi Horibe, Toshio Nozoe
  • Patent number: 6858515
    Abstract: A semiconductor device free from electric failure in transistors at upper trench edges can be produced by a simplified process comprising basic steps of forming a pad oxide film on the circuit-forming side of a semiconductor substrate; forming an oxidation prevention film on the pad oxide film; removing the oxidation presention film and the pad oxide film at a desired position, thereby exposing the surface of the semiconductor substrate; horizontally recessing the pad oxide film, etching the exposed surface of the semiconductor substrate by isotropic etching; forming a trench to a desired depth, using the oxidation prevention film as a mask; horizontally recessing the pad oxide film; oxidizing the trench formed in the semiconductor substrate; embedding an embedding isolation film in the oxidized trench; removing the embedding isolation film formed on the oxidation prevention film; removing the oxidation prevention film formed on the circuit-forming side of the semiconductor substrate; and removing the pad oxi
    Type: Grant
    Filed: August 12, 2003
    Date of Patent: February 22, 2005
    Assignee: Renesas Technology Corp.
    Inventors: Norio Ishitsuka, Hideo Miura, Shuji Ikeda, Yasuko Yoshida, Norio Suzuki, Kozo Watanabe, Kenji Kanamitsu
  • Publication number: 20050014340
    Abstract: A semiconductor integrated circuit device and a method of manufacturing the same. The surface of a substrate of an active region surrounded by an element isolation trench is horizontally flat in the center portion of the active region but falls toward the side wall of the element isolation trench in the shoulder portion of the active region. This inclined surface contains two inclined surfaces having different inclination angles. The first inclined surface near the center portion of the active region is relatively steep and the second inclined surface near the side wall of the element isolation trench is gentler than the first inclined surface. The surface of the substrate in the shoulder portion of the active region is wholly rounded and has no angular portion.
    Type: Application
    Filed: August 17, 2004
    Publication date: January 20, 2005
    Inventors: Kenji Kanamitsu, Kouzou Watanabe, Norio Suzuki, Norio Ishitsuka
  • Patent number: 6838374
    Abstract: To suppress oxidation of the inner walls of element isolation grooves otherwise occurring during thermal oxidation processes, a nitrogen introducing layer, that has a lower diffusion coefficient relative to an oxidizing agent, is formed at the surface portion of a silicon oxide film buried within an element isolation groove. This nitrogen introduced layer functions as a barrier layer for precluding the oxidizer (such as oxygen, water or the like) in vapor phase from diffusing into the silicon oxide film during thermal processing steps. The nitrogen introduced layer is formed by performing nitrogen ion implantation into the entire surface of a substrate and subsequently applying thermal processing to the substrate to thereby activate the nitrogen that has been doped.
    Type: Grant
    Filed: June 14, 2002
    Date of Patent: January 4, 2005
    Assignee: Renesas Technology Corp.
    Inventors: Toshiya Uenishi, Satoshi Meguro, Masaharu Kubo, Masataka Kato, Hideo Miura, Norio Suzuki
  • Publication number: 20040262265
    Abstract: A manufacturing method of semiconductor device capable of suppressing or preventing formation of a dissolution region of composition atoms such as a pit in a semiconductor wafer. After oxide film on a semiconductor wafer is removed by dipping plural pieces of the semiconductor wafer accommodated in a carrier into chemical liquid containing fluoro acid, chemical liquid adhering to the semiconductor wafer is washed out of the semiconductor wafer by rinse processing using de-ionized water. At least in the rinse processing of this wet processing, light is projected to the semiconductor wafer from a light source provided on a wet etching apparatus. Adjusting electromotive force caused by battery reaction at a pn junction of the semiconductor wafer by adjusting the state of the light L enables generation of a pit in the semiconductor wafer.
    Type: Application
    Filed: June 25, 2004
    Publication date: December 30, 2004
    Applicant: Trecenti Technologies, Inc.
    Inventors: Michimasa Funabashi, Masakatsu Kuwabara, Kazunori Nemoto, Hiroyuki Mima, Norio Suzuki
  • Patent number: 6821854
    Abstract: A protection film is formed on a silicon oxide film 6 formed on the surface of a semiconductor substrate, a silicon oxide film is removed from a region where a thin gate-insulating film is to be formed by using, as a mask, a photoresist pattern that covers a region where a thick gate-insulating film is to be formed, and, then, the photoresist pattern is removed followed by washing. Then, the semiconductor substrate is heat-oxidized or a film is deposited thereon to form gate-insulating films having different thicknesses.
    Type: Grant
    Filed: August 5, 2002
    Date of Patent: November 23, 2004
    Assignee: Renesas Technology Corp.
    Inventors: Takayuki Kanda, Atsushi Hiraiwa, Norio Suzuki, Satoshi Sakai, Shuji Ikeda, Yasuko Yoshida, Shinichi Horibe
  • Publication number: 20040219727
    Abstract: Over the principal surface of a semiconductor substrate body containing an impurity of a predetermined conduction type, there is formed an epitaxial layer which contains an impurity of the same conduction type as that of the former impurity and the same concentration as the designed one of the former impurity. After this, there are formed a well region which has the same conduction type as that of said impurity and its impurity concentration gradually lowered depthwise of said epitaxial layer. The well region is formed with the gate insulating films of MIS•FETs.
    Type: Application
    Filed: June 7, 2004
    Publication date: November 4, 2004
    Inventors: Hiroto Kawagoe, Tatsumi Shirasu, Shogo Kiyota, Norio Suzuki, Eiichi Yamada, Yuji Sugino, Manabu Kitano, Yoshihiko Sakurai, Takashi Naganuma, Hisashi Arakawa