Patents by Inventor Norio Suzuki

Norio Suzuki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Semiconductor integrated circuit device and method of fabricating the same
    Publication number: 20030003644
    Abstract: To suppress oxidation of inner walls of element isolation grooves otherwise occurring during thermal oxidation processes. A nitrogen introducing layer less in diffusion coefficient relative to an oxidizing agent is formed at the surface portion of a silicon oxide film as buried within an element isolation groove. This nitrogen introduce layer functions as a barrier layer for precluding the oxidizer (such as oxygen, water or else) in vapor phase from diffusing into the silicon oxide film at thermal processing steps. The nitrogen introduce layer is formed by performing nitrogen ion implantation into an entire surface of a substrate and subsequently applying thermal processing to the substrate to thereby activate the nitrogen doped.
    Type: Application
    Filed: June 14, 2002
    Publication date: January 2, 2003
    Inventors: Toshiya Uenishi, Satoshi Meguro, Masaharu Kubo, Masataka Kato, Hideo Miura, Norio Suzuki
  • Method of manufacturing a semiconductor integrated circuit device
    Publication number: 20030003639
    Abstract: A protection film is formed on a silicon oxide film 6 formed on the surface of a semiconductor substrate, a silicon oxide film is removed from a region where a thin gate-insulating film is to be formed by using, as a mask, a photoresist pattern that covers a region where a thick gate-insulating film is to be formed, and, then, the photoresist pattern is removed followed by washing. Then, the semiconductor substrate is heat-oxidized or a film is deposited thereon to form gate-insulating films having different thicknesses.
    Type: Application
    Filed: August 5, 2002
    Publication date: January 2, 2003
    Inventors: Takayuki Kanda, Atsushi Hiraiwa, Norio Suzuki, Satoshi Sakai, Shuji Ikeda, Yasuko Yoshida, Shinichi Horibe
  • Method of manufacturing semiconductor devices
    Patent number: 6498100
    Abstract: In a method of manufacturing a semiconductor device having a memory mat portion in which an active region and a field region are formed densely, after a polishing stopper film is deposited on a semiconductor substrate, there are formed grooves by etching a polishing stopper film of a field region and the semiconductor substrate. Then, after an insulating film is deposited so as to fill the grooves, then insulating film is partly removed from the memory mat portion by etching. Under this state, the insulating film is chemically mechanically polished until the polishing stopper film is exposed. The film thickness of the polishing stopper film on the active region can be reduced, and an electrical element isolation characteristic of the field region can be improved.
    Type: Grant
    Filed: November 30, 2001
    Date of Patent: December 24, 2002
    Assignee: Hitachi, Ltd.
    Inventors: Akio Nishida, Kikuo Kusukawa, Toshiaki Yamanaka, Natsuki Yokoyama, Shinichiro Kimura, Norio Suzuki, Osamu Tsuchiya, Atsushi Ogishima
  • Semiconductor wafer processing apparatus for transferring a wafer mount
    Patent number: 6462411
    Abstract: A semiconductor wafer processing apparatus comprises a reaction furnace capable of heating inside thereof, a wafer mount for mounting a semiconductor wafer thereon and a transfer device. The wafermount includes an opening which is greater than the semiconductor wafer and which has a circle shape or a shape substantially similar to an outer periphery of the semiconductor wafer, and includes a wafer supporting portion projecting inwardly of the opening for supporting the semiconductor wafer. The transfer device is capable of holding the wafer mount outside the semiconductor wafer as viewed from a vertical direction, and transferring the wafer mount carrying the semiconductor wafer thereon substantially horizontally into and/or out from the reaction furnace.
    Type: Grant
    Filed: December 4, 1998
    Date of Patent: October 8, 2002
    Assignee: Kokusai Electric Co., LTD
    Inventors: Tomoji Watanabe, Nobuyuki Mise, Toshiyuki Uchino, Norio Suzuki, Yoshihiko Sakurai, Toshiya Uenishi, Yohsuke Inoue, Yasuhiro Inokuchi, Fumihide Ikeda
  • Electronic device and attachment structure thereof
    Patent number: 6456505
    Abstract: An electronic device having a plurality of leader patterns, and penetration portions penetrating the leader patterns, provided in an extension portion of a printed board projecting from a housing. The respective leader patterns are configured to function as connection terminals by connecting directly to lands on a mother board without the use of separate metal terminals.
    Type: Grant
    Filed: July 19, 2001
    Date of Patent: September 24, 2002
    Assignee: Alps Electric Co., Ltd.
    Inventors: Norio Suzuki, Hideharu Otake
  • Composition for gene transfer into cells
    Publication number: 20020111326
    Abstract: The present invention is directed to a composition for gene transfer which composition contains a quaternary ammonium salt represented by formula (1): 1
    Type: Application
    Filed: January 2, 2002
    Publication date: August 15, 2002
    Applicant: DAIICHI PHARMACEUTICAL CO., LTD.
    Inventors: Kenichi Tanaka, Hiroshi Kikuchi, Norio Suzuki
  • Fuel supply conrol system for internal combustion engine
    Patent number: 6405527
    Abstract: There is provided a fuel supply control system for an internal combustion engine, which is capable of controlling fuel cutoff according to an amount of oxygen stored in a catalytic converter to thereby enhance the purification rate of the catalytic converter while maintaining excellent fuel economy, thereby making it possible to improve exhaust emission characteristics. An amount of oxygen stored in the catalytic converter 13 arranged in an exhaust pipe 12 of an engine 3 is estimated (steps S1 to S29). A deceleration condition of the engine is detected (steps S35, S36). When the deceleration condition is detected, supply of fuel to the engine is cut off (step S41). The cutoff of fuel supply is controlled based on the oxygen storage amount OSC (steps S31, S32, S40, S41).
    Type: Grant
    Filed: January 30, 2001
    Date of Patent: June 18, 2002
    Assignee: Honda Giken Kogyo Kabushiki Kaisha
    Inventors: Norio Suzuki, Toru Kitamura
  • Method for manufacturing semiconductor device
    Patent number: 6403446
    Abstract: Manufacturing a semiconductor device avoiding an increase of transistor leak current or reduction of the withstanding voltage characteristics is by at least one of: The pad oxide film is removed along the substrate surface from the upper edge of the groove over a distance ranging from 5 to 40 nm: The exposed surface of the semiconductor substrate undergoes removal by isotropic etching within 20 nm; and oxidizing a groove portion formed in a semiconductor substrate in an oxidation environment with a gas ratio of hydrogen (H2) to oxygen (O2) being less than or equal to 0.5, an increase of the curvature radius beyond 3nm is achieved without associating the risk of creation of any level difference on the substrate surface at or near the upper groove edge portions in a groove separation structure.
    Type: Grant
    Filed: March 28, 2000
    Date of Patent: June 11, 2002
    Assignee: Hitachi, Ltd.
    Inventors: Norio Ishitsuka, Hideo Miura, Shuji Ikeda, Yasuko Yoshida, Norio Suzuki, Masayuki Kojima, Kota Funayama
  • Process for manufacturing a semiconductor wafer, a semiconductor wafer, process for manufacturing a semiconductor integrated circuit device, and semiconductor integrated circuit device
    Publication number: 20020061615
    Abstract: Over the principal surface of a semiconductor substrate body containing an impurity of a predetermined conduction type, there is formed an epitaxial layer which contains an impurity of the same conduction type as that of the former impurity and the same concentration as the designed one of the former impurity. After this, there are formed a well region which has the same conduction type as that of said impurity and its impurity concentration gradually lowered depthwise of said epitaxial layer The well region is formed with the gate insulating films of MIS·FETs.
    Type: Application
    Filed: December 14, 2001
    Publication date: May 23, 2002
    Inventors: Hiroto Kawagoe, Tatsumi Shirasu, Shogo Kiyota, Norio Suzuki, Eiichi Yamada, Yuji Sugino, Manabu Kitano, Yoshihiko Sakurai, Takashi Naganuma, Hisashi Arakawa
  • Process for manufacturing a semiconductor wafer, a semiconductor wafer, process for manufacturing a semiconductor integrated circuit device, and semiconductor integrated circuit device
    Publication number: 20020055204
    Abstract: Over the principal surface of a semiconductor substrate body containing an impurity of a predetermined conduction type, there is formed an epitaxial layer which contains an impurity of the same conduction type as that of the former impurity and the same concentration as the designed one of the former impurity. After this, there are formed a well region which has the same conduction type as that of said impurity and its impurity concentration gradually lowered depthwise of said epitaxial layer. The well region is formed with the gate insulating films of MIS.FETS.
    Type: Application
    Filed: December 5, 2001
    Publication date: May 9, 2002
    Inventors: Hiroto Kawagoe, Tatsumi Shirasu, Shogo Kiyota, Norio Suzuki, Eiichi Yamada, Yuji Sugino, Manabu Kitano, Yoshihiko Sakurai, Takashi Naganuma, Hisashi Arakawa
  • Method of manufacturing semiconductor devices
    Publication number: 20020055261
    Abstract: In a method of manufacturing a semiconductor device having a memory mat portion in which an active region and a field region are formed densely, after a polishing stopper film is deposited on a semiconductor substrate, there are formed grooves by etching a polishing stopper film of a field region and the semiconductor substrate. Then, after an insulating film is deposited so as to fill the grooves, then insulating film is partly removed from the memory mat portion by etching. Under this state, the insulating film is chemically mechanically polished until the polishing stopper film is exposed. The film thickness of the polishing stopper film on the active region can be reduced, and an electrical element isolation characteristic of the field region can be improved.
    Type: Application
    Filed: November 30, 2001
    Publication date: May 9, 2002
    Applicant: Hitachi, Ltd.
    Inventors: Akio Nishida, Kikuo Kusukawa, Toshiaki Yamanaka, Natsuki Yokoyama, Shinichiro Kimura, Norio Suzuki, Osamu Tsuchiya, Atsushi Ogishima
  • Method of manufacturing semiconductor devices
    Patent number: 6380085
    Abstract: In a method of manufacturing a semiconductor device having a memory mat portion in which an active region and a field region are formed densely, after a polishing stopper film is deposited on a semiconductor substrate, there are formed grooves by etching a polishing stopper film of a field region and the semiconductor substrate. Then, after an insulating film is deposited so as to fill the grooves, then insulating film is partly removed from the memory mat portion by etching. Under this state, the insulating film is chemically mechanically polished until the polishing stopper film is exposed. The film thickness of the polishing stopper film on the active region can be reduced, and an electrical element isolation characteristic of the field region can be improved.
    Type: Grant
    Filed: December 29, 2000
    Date of Patent: April 30, 2002
    Assignee: Hitachi, Ltd.
    Inventors: Akio Nishida, Kikuo Kusukawa, Toshiaki Yamanaka, Natsuki Yokoyama, Shinichiro Kimura, Norio Suzuki, Osamu Tsuchiya, Atsushi Ogishima
  • Method for manufacturing semiconductor integrated circuit device having deposited layer for gate insulation
    Patent number: 6376316
    Abstract: A method for manufacturing a semiconductor integrated circuit device including a first field effect transistor having a gate insulating film formed over a first element forming region of a main surface of a semiconductor substrate; and a second field effect transistor having a gate insulating film formed over a second element forming region of the main surface of the semiconductor substrate and made thinner than the gate insulating film of the first field effect transistor.
    Type: Grant
    Filed: December 9, 1998
    Date of Patent: April 23, 2002
    Assignee: Hitachi, Ltd.
    Inventors: Shoji Shukuri, Norio Suzuki, Yasuhiro Taniguchi
  • Composition for gene introduction into cell
    Patent number: 6372714
    Abstract: The present invention is directed to a composition for gene transfer which composition contains a quaternary ammonium salt represented by formula (1): wherein A represents (wherein each of R1, R2, R3, R4 and R5, which are identical to or different from one another, represents a C9-C17 aliphatic group); X1 represents a halogen atom; and n is an integer from 1 to 10 inclusive; and a method for introducing a gene into a cell by use of the composition. The composition enables effective delivery and expression of a gene which previously could not be effectively expressed in cells due to the low ratio at which the gene is delivered into cells. Therefore, the composition is advantageously used as a gene transfer reagent or a pharmaceutical.
    Type: Grant
    Filed: October 7, 1999
    Date of Patent: April 16, 2002
    Assignee: Daiichi Pharmaceutical Co., Ltd.
    Inventors: Kenichi Tanaka, Hiroshi Kikuchi, Norio Suzuki
  • Process for manufacturing a semiconductor wafer, a semiconductor wafer, process for manufacturing a semiconductor integrated circuit device, and semiconductor integrated circuit device
    Patent number: 6368905
    Abstract: Over the principal surface of a semiconductor substrate body containing an impurity of a predetermined conduction type, there is formed an epitaxial layer which contains an impurity of the same conduction type as that of the former impurity and the same concentration as the designed one of the former impurity. After this, there are formed a well region which has the same conduction type as that of said impurity and its impurity concentration gradually lowered depthwise of said epitaxial layer. The well region is formed with the gate insulating films of MIS.FETs.
    Type: Grant
    Filed: February 25, 2000
    Date of Patent: April 9, 2002
    Assignee: Hitachi, Ltd.
    Inventors: Hiroto Kawagoe, Tatsumi Shirasu, Shogo Kiyota, Norio Suzuki, Eiichi Yamada, Yuji Sugino, Manabu Kitano, Yoshihiko Sakurai, Takashi Naganuma, Hisashi Arakawa
  • Evaporative emission control system for internal combustion engine
    Patent number: 6347617
    Abstract: Disclosed herein is an evaporative emission control system which can prevent changes in fuel component in the fuel tank and vacuum boiling in the fuel pump to thereby accurately control the air-fuel ratio to a desired value and ensure smooth supply of the fuel. The control system includes an evaporative fuel passage for connecting a fuel tank and an intake system of an internal combustion engine, and a control valve is provided in the evaporative fuel passage for opening and closing the evaporative fuel passage. It is determined whether or not a fuel temperature is higher than or equal to a predetermined fuel temperature. If the fuel temperature is higher than or equal to the predetermined fuel temperature, the opening operation of the control valve is disabled.
    Type: Grant
    Filed: June 29, 2000
    Date of Patent: February 19, 2002
    Assignee: Honda Giken Kogyo Kabushiki Kaisha
    Inventors: Toru Kitamura, Norio Suzuki, Naohiro Kurokawa, Tetsuya Ishiguro, Takeshi Suzuki, Toshiaki Ichitani
  • METHOD FOR MANUFACTURING SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE HAVING DEPOSITED LAYER FOR GATE INSULATION
    Publication number: 20020019100
    Abstract: A method for manufacturing a semiconductor integrated circuit device including a first field effect transistor having a gate insulating film formed over a first element forming region of a main surface of a semiconductor substrate; and a second field effect transistor having a gate insulating film formed over a second element forming region of the main surface of the semiconductor substrate and made thinner than the gate insulating film of the first field effect transistor.
    Type: Application
    Filed: December 9, 1998
    Publication date: February 14, 2002
    Inventors: SHOJI SHUKURI, NORIO SUZUKI, YASUHIRO TANIGUCHI
  • Semiconductor device and production thereof
    Publication number: 20020019146
    Abstract: A semiconductor device produced by forming an oxide film on a substrate, heat treating the oxide film at a temperature of 800° C. or higher in an inert atmosphere, followed by conventional steps for formation of a transistor, is improved in electrical reliability due to relaxation of stress generated in the oxide film or in the surface of substrate.
    Type: Application
    Filed: October 16, 2001
    Publication date: February 14, 2002
    Inventors: Hideo Miura, Shuji Ikeda, Norio Suzuki, Yasuhide Hagiwara, Hiroyuki Ohta, Asao Nishimura
  • Semiconductor integrated circuit device and having deposited layer for gate insulation
    Publication number: 20020014641
    Abstract: A method for manufacturing a semiconductor integrated circuit device including a first field effect transistor having a gate insulating film formed over a first element forming region of a main surface of a semiconductor substrate; and a second field effect transistor having a gate insulating film formed over a second element forming region of the main surface of the semiconductor substrate and made thinner than the gate insulating film of the first field effect transistor.
    Type: Application
    Filed: September 25, 2001
    Publication date: February 7, 2002
    Inventors: Shoji Shukuri, Norio Suzuki, Yasuhiro Taniguchi
  • Method for manufacturing semiconductor integrated circuit device having floating gate and deposited film
    Publication number: 20020009851
    Abstract: A method for manufacturing a semiconductor integrated circuit device including a first field effect transistor having a gate insulating film formed over a first element forming region of a main surface of a semiconductor substrate; and a second field effect transistor having a gate insulating film formed over a second element forming region of the main surface of the semiconductor substrate and made thinner than the gate insulating film of the first field effect transistor.
    Type: Application
    Filed: September 25, 2001
    Publication date: January 24, 2002
    Inventors: Shoji Shukuri, Norio Suzuki, Yasuhiro Taniguchi