Patents by Inventor Noriyoshi Shimizu

Noriyoshi Shimizu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • SEMICONDUCTOR PACKAGE, SEMICONDUCTOR PACKAGE MANUFACTURING METHOD AND SEMICONDUCTOR DEVICE
    Publication number: 20130119562
    Abstract: A semiconductor package includes a semiconductor chip, a first insulating layer formed to cover the semiconductor chip, a wiring structure formed on the first insulating layer. The wiring structure has an alternately layered configuration including wiring layers electrically connected to the semiconductor chip and interlayer insulating layers each located between one of the wiring layers and another. The interlayer insulating layers include an outermost interlayer insulating layer located farthest from a surface of the first insulating layer. A groove formed in the outermost interlayer insulating layer passes through the outermost interlayer insulating layer in a thickness direction.
    Type: Application
    Filed: November 2, 2012
    Publication date: May 16, 2013
    Applicant: Shinko Electric Industries Co., LTD.
    Inventors: Noriyoshi Shimizu, Akio Rokugawa, Osamu Inoue
  • Semiconductor device having a conductor buried in an opening
    Patent number: 8415798
    Abstract: A semiconductor device includes a first conductor formed over a semiconductor device; an insulation film formed over the semiconductor substrate and the first conductor and having an opening arriving at the first conductor; a first film formed in the opening and formed of a compound containing Zr; a second film formed over the first film in the opening and formed of an oxide containing Mn; and a second conductor buried in the opening and containing Cu.
    Type: Grant
    Filed: June 16, 2010
    Date of Patent: April 9, 2013
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Nobuyuki Ohtsuka, Noriyoshi Shimizu
  • Adhesive for Teeth-Straightening Members
    Publication number: 20130071804
    Abstract: The present invention discloses an adhesive for orthodontic attachments, which contains (A) a polymerizable monomer, (B) a polymerization initiator and (C) a fluorescent dye and, when cured, exhibits a fluorescence spectrum having a peak at 400 to 800 nm. As the polymerization initiator (B), there is preferably used a compound which generates a radical through the transfer of hydrogen between two components, or a compound which generates a radical species through intramolecular cleavage. As the fluorescent dye (C), a coumarin type dye is used preferably.
    Type: Application
    Filed: November 9, 2012
    Publication date: March 21, 2013
    Applicants: TOKUYAMA DENTAL CORPORATION, NIHON UNIVERSITY
    Inventors: Yasuhiro Namura, Noriyoshi Shimizu, Shizuka Amma, Takeshi Suzuki, Hideki Kazama
  • Semiconductor package
    Patent number: 8378492
    Abstract: There is provided a method of manufacturing a semiconductor package. The method includes: (a) providing a semiconductor chip having a first surface and a second surface opposite to the first surface, wherein a pad is formed on the first surface; (b) disposing the semiconductor chip on a supporting substrate such that the first surface is directed upward; (c) forming an encapsulation resin layer on the supporting substrate so as to cover the semiconductor chip; and (d) polishing the encapsulation resin layer to expose a top surface of the pad.
    Type: Grant
    Filed: November 22, 2010
    Date of Patent: February 19, 2013
    Assignee: Shinko Electric Industries Co., Ltd.
    Inventors: Noriyoshi Shimizu, Akio Rokugawa
  • Method of forming wiring structure and semiconductor device comprising underlying refractory metal layers
    Patent number: 8373274
    Abstract: A micronized wiring structure is obtained by optimizing film forming modes of barrier metal films as being adapted respectively to a via-hole and a wiring groove, wherein sputtering processes are adopted herein, which are specifically the multi-step sputtering process for formation of the barrier metal film over the via-hole, and the one-step, low-power sputtering process for formation of the barrier metal film over the wiring groove, to thereby realize improved electric characteristics such as via-hole resistance and wiring resistance, and improved wiring reliabilities such as Cu filling property and electro-migration resistance.
    Type: Grant
    Filed: February 15, 2008
    Date of Patent: February 12, 2013
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Hisaya Sakai, Noriyoshi Shimizu
  • Semiconductor device having a multilevel interconnect structure and method for fabricating the same
    Patent number: 8304908
    Abstract: A multilevel interconnect structure in a semiconductor device includes a first insulating layer formed on a semiconductor wafer, a Cu interconnect layer formed on the first insulating layer, a second insulating layer formed on the Cu interconnect layer, and a metal oxide layer formed at an interface between the Cu interconnect layer and the second insulating layer. The metal oxide layer is formed by immersion-plating a metal, such as Sn or Zn, on the Cu interconnect layer and then heat-treating the plated layer in an oxidizing atmosphere.
    Type: Grant
    Filed: March 19, 2009
    Date of Patent: November 6, 2012
    Assignees: Semiconductor Technology Academic Research Center, National University Corporation Tohoku University
    Inventors: Junichi Koike, Yoshito Fujii, Jun Iijima, Noriyoshi Shimizu, Kazuyoshi Maekawa, Koji Arita, Ryotaro Yagi, Masaki Yoshimaru
  • Method of manufacturing a semiconductor package and semiconductor package having an electrode pad with a small pitch
    Patent number: 8288875
    Abstract: A board on which a wiring having an electrode pad is formed is prepared. A resist film is formed on the board in order to cover the wiring and then the resist film is left on the electrode pad through patterning. An inorganic insulating film is formed on the board in order to cover the wiring and then the resist film is removed, thereby removing the inorganic insulating film provided on the resist film to leave the inorganic insulating film between the wirings. A solder resist layer is formed on the board in order to cover the wiring and then the electrode pad is exposed.
    Type: Grant
    Filed: March 29, 2010
    Date of Patent: October 16, 2012
    Assignee: Shinko Electric Industries Co., Ltd.
    Inventors: Noriyoshi Shimizu, Akio Rokugawa
  • SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME
    Publication number: 20120181695
    Abstract: A semiconductor device includes a semiconductor substrate, an oxygen-containing insulating film disposed above the above-described semiconductor substrate, a concave portion disposed in the above-described insulating film, a copper-containing first film disposed on an inner wall of the above-described concave portion, a copper-containing second film disposed above the above-described first film and filled in the above-described concave portion, and a manganese-containing oxide layer disposed between the above-described first film and the above-described second film. Furthermore, a copper interconnection is formed on the above-described structure by an electroplating method and, subsequently, a short-time heat treatment is conducted at a temperature of 80° C. to 120° C.
    Type: Application
    Filed: March 29, 2012
    Publication date: July 19, 2012
    Applicant: FUJITSU SEMICONDUCTOR LIMITED
    Inventors: Masaki HANEDA, Michie SUNAYAMA, Noriyoshi SHIMIZU, Nobuyuki OHTSUKA, Yoshiyuki NAKAO, Takahiro TABIRA
  • SEMICONDUCTOR PACKAGE MANUFACTURING METHOD AND SEMICONDUCTOR PACKAGE
    Publication number: 20120153457
    Abstract: According to one embodiment, there is provided a semiconductor package manufacturing method utilizing a support body in which a first layer is stacked on a second layer, the method including: a first step of forming an opening in the first layer to expose the second layer therethrough; a second step of arranging a semiconductor chip on the second layer through the opening; a third step of forming a resin portion on the first layer to cover the semiconductor chip; and a fourth step of forming a wiring structure on the resin portion so as to be electrically connected to the semiconductor chip.
    Type: Application
    Filed: December 16, 2011
    Publication date: June 21, 2012
    Applicant: SHINKO ELECTRIC INDUSTRIES CO., LTD.
    Inventors: Noriyoshi Shimizu, Akio Rokugawa, Hirokazu Yoshino
  • Method of manufacturing a multilayer interconnection structure in a semiconductor device
    Patent number: 8168532
    Abstract: A semiconductor device includes a semiconductor substrate, an oxygen-containing insulating film disposed above the above-described semiconductor substrate, a concave portion disposed in the above-described insulating film, a copper-containing first film disposed on an inner wall of the above-described concave portion, a copper-containing second film disposed above the above-described first film and filled in the above-described concave portion, and a manganese-containing oxide layer disposed between the above-described first film and the above-described second film. Furthermore, a copper interconnection is formed on the above-described structure by an electroplating method and, subsequently, a short-time heat treatment is conducted at a temperature of 80° C. to 120° C.
    Type: Grant
    Filed: November 10, 2008
    Date of Patent: May 1, 2012
    Assignee: Fujitsu Limited
    Inventors: Masaki Haneda, Michie Sunayama, Noriyoshi Shimizu, Nobuyuki Ohtsuka, Yoshiyuki Nakao, Takahiro Tabira
  • Semiconductor device with a barrier film
    Patent number: 8133813
    Abstract: A method of manufacturing a semiconductor device, including forming an opening in an interlevel insulating film disposed on a semiconductor substrate, forming an auxiliary film containing a predetermined metal element, to cover an inner surface of the opening, forming a main film to fill the opening after forming the auxiliary film, the main film containing, as a main component, Cu used as a material of an interconnection main layer, and performing a heat treatment before or after forming the main film, thereby diffusing the predetermined metal element of the auxiliary film onto a surface of the interlevel insulating film facing the auxiliary film, so as to form a barrier film on the interlevel insulating film within the opening, the barrier film containing, as a main component, a compound of the predetermined metal element with a component element of the interlevel insulating film.
    Type: Grant
    Filed: April 14, 2011
    Date of Patent: March 13, 2012
    Assignee: Semiconductor Technology Academic Research Center
    Inventors: Junichi Koike, Makoto Wada, Shingo Takahashi, Noriyoshi Shimizu, Hideki Shibata, Satoshi Nishikawa, Takamasa Usui, Hayato Nasu, Masaki Yoshimaru
  • Method of manufacturing semiconductor device
    Patent number: 8119524
    Abstract: A first film containing a first metal material having a diffusion preventing function for copper, a second film containing oxygen-contained copper film, a third film containing copper and a second metal material which exhibits a diffusion preventing function for copper by bonding with oxygen, and a fourth film of copper as the main material are formed in an opening formed in an insulating film, and then a barrier layer containing the first metal material, the second metal material and oxygen is formed by thermal processing between the insulating film and the fourth film.
    Type: Grant
    Filed: December 14, 2010
    Date of Patent: February 21, 2012
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Michie Sunayama, Noriyoshi Shimizu
  • Manufacture method for semiconductor device using damascene method
    Patent number: 8101513
    Abstract: (a) A recess is formed through an insulating film formed over a semiconductor substrate. (b) After the recess is formed, a temperature of the substrate is raised to 300° C. or higher at a temperature rising rate of 10° C./s or slower and a first degassing process is executed. (c) After the first degassing process, a conductive film is deposited on the insulating film, the conductive film being embedded in the recess. (d) The deposited conductive film is polished until the insulating film is exposed. It is possible to suppress occurrence of defects during CMP to be performed after a conductive member is deposited on the surface of the insulating film having a recess formed therethrough.
    Type: Grant
    Filed: March 3, 2006
    Date of Patent: January 24, 2012
    Assignee: Fujitsu Limited
    Inventors: Tsuyoshi Kanki, Nobuyuki Ohtsuka, Hisaya Sakai, Noriyoshi Shimizu
  • Method of manufacturing semiconductor device suitable for forming wiring using damascene method
    Patent number: 8071474
    Abstract: (a1) A concave portion is formed in an interlayer insulating film formed on a semiconductor substrate. (a2) A first film of Mn is formed by CVD, the first film covering the inner surface of the concave portion and the upper surface of the insulating film. (a3) Conductive material essentially consisting of Cu is deposited on the first film to embed the conductive material in the concave portion. (a4) The semiconductor substrate is annealed. During the period until a barrier layer is formed having also a function of improving tight adhesion, it is possible to ensure sufficient tight adhesion of wiring members and prevent peel-off of the wiring members.
    Type: Grant
    Filed: August 10, 2010
    Date of Patent: December 6, 2011
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Noriyoshi Shimizu, Nobuyuki Ohtsuka, Hideki Kitada, Yoshiyuki Nakao
  • Semiconductor device using metal nitride as insulating film and its manufacture method
    Patent number: 8067309
    Abstract: A first insulating film is formed on a semiconductor substrate. A second insulating film made of insulating metal nitride is formed on the first insulating film. A recess is formed through the second insulating film and reaches a position deeper than an upper surface of the first insulating film. A conductive member is buried in the recess. A semiconductor device is provided whose interlayer insulating film can be worked easily even if it is made to have a low dielectric constant.
    Type: Grant
    Filed: September 26, 2008
    Date of Patent: November 29, 2011
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Noriyoshi Shimizu, Yoshiyuki Nakao, Hiroki Kondo, Takashi Suzuki, Nobuyuki Nishikawa
  • Semiconductor device with reduced increase in copper film resistance
    Patent number: 8067836
    Abstract: A semiconductor device includes an insulating film including oxygen formed over a semiconductor substrate, a recess formed in the insulating film, a refractory metal film formed on the inner wall of the recess, a metal film including copper, manganese, and nitrogen formed on the refractory metal film, and a copper film formed on the metal film to fill in the recess.
    Type: Grant
    Filed: April 29, 2009
    Date of Patent: November 29, 2011
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Masaki Haneda, Noriyoshi Shimizu, Nobuyuki Ohtsuka, Yoshiyuki Nakao, Michie Sunayama, Takahiro Tabira
  • Manufacturing method of semiconductor device
    Patent number: 8003527
    Abstract: A semiconductor device manufacturing method includes forming an interlayer dielectric film above a semiconductor substrate; forming a first wiring trench with a first width and a second wiring trench with a second width that is larger than the first width inr the interlayer dielectric film; forming a first seed layer that includes a first additional element in the first wiring trench and the second wiring trench; forming a first copper layer over the first seed layer; removing the first copper layer and the first seed layer in the second wiring trench while leaving the first copper layer and the first seed layer in the first wiring trench; forming a second seed layer in the second wiring trench after removing the first copper layer and the first seed layer in the second wiring trench; and forming a second copper layer over the second seed layer.
    Type: Grant
    Filed: July 26, 2010
    Date of Patent: August 23, 2011
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Michie Sunayama, Noriyoshi Shimizu
  • Semiconductor device fabrication method
    Patent number: 8003518
    Abstract: A semiconductor device fabrication method including the steps of: forming an interlayer insulating film on a substrate; forming an opening in the interlayer insulating film; forming an alloy layer containing manganese and copper to cover the inner surface of the opening; forming a first copper layer of a material containing primarily copper on the alloy layer to fill the opening; forming, on the first copper layer, a second copper layer of a material containing primarily copper and a higher concentration of oxygen, carbon or nitrogen than the first copper layer; heating the substrate on which the second copper layer has been formed; and removing the second copper layer.
    Type: Grant
    Filed: September 24, 2009
    Date of Patent: August 23, 2011
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Masaki Haneda, Noriyoshi Shimizu, Michie Sunayama
  • Method of manufacturing semiconductor apparatus, and semiconductor apparatus
    Patent number: 7994055
    Abstract: A method of manufacturing a semiconductor apparatus which includes the steps of forming a via hole and a wire trench reaching an underlying wire in an interlayer insulation film formed on the underlying wire, forming an diffusion barrier film on said underlying wire exposed through said via hole, on an inner wall of said via hole and on an inner wall of said wire trench, forming a seed layer on said underlying wire and on said diffusion barrier film formed on the inner wall of said via hole and the inner wall of said wire trench while concurrently said diffusion barrier film deposited on the bottom of said via hole is being etched, and forming metal wire in said via hole and in said wire trench.
    Type: Grant
    Filed: January 30, 2008
    Date of Patent: August 9, 2011
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Hisaya Sakai, Noriyoshi Shimizu
  • SEMICONDUCTOR DEVICE WITH A BARRIER FILM
    Publication number: 20110189849
    Abstract: A method of manufacturing a semiconductor device, including forming an opening in an interlevel insulating film disposed on a semiconductor substrate, forming an auxiliary film containing a predetermined metal element, to cover an inner surface of the opening, forming a main film to fill the opening after forming the auxiliary film, the main film containing, as a main component, Cu used as a material of an interconnection main layer, and performing a heat treatment before or after forming the main film, thereby diffusing the predetermined metal element of the auxiliary film onto a surface of the interlevel insulating film facing the auxiliary film, so as to form a barrier film on the interlevel insulating film within the opening, the barrier film containing, as a main component, a compound of the predetermined metal element with a component element of the interlevel insulating film.
    Type: Application
    Filed: April 14, 2011
    Publication date: August 4, 2011
    Applicant: SEMICONDUCTOR TECHNOLOGY ACADEMIC RESEARCH CENTER
    Inventors: Junichi KOIKE, Makoto Wada, Shingo Takahashi, Noriyoshi Shimizu, Hideki Shibata, Satoshi Nishikawa, Takamasa Usui, Hayato Nasu, Masaki Yoshimaru