Abstract: An interface circuit which is connected to a function unit such as a memory reduces the number of structural elements by using structural elements in common, and also realizes a plurality of different function circuits. The interface circuit connected with the function unit uses the structural elements for a plurality of circuits in common, and obtains necessary functions by controlling the structural elements. The interface circuit has first and second electronic devices such as FETs connected in series, and an external terminal, formed at an intermediate connected portion between the first electronic device and the second electronic device, to which the function unit is connected, and constitutes a function circuit part having different functions by controlling the first electronic device and the second electronic device.

Abstract: A signal transmission method and a signal transmission device capable of easily transmitting a signal with a small number of signal lines. A data signal of time slot count N+? with bit count N is longitudinal-lateral converted into a data signal of time slot count N with bit count N+?. so as to create a null time ? and a control signal is inserted into the null time ?, thereby converting the parallel signal containing the data signal and the control signal into a serial signal for transmission.

Abstract: A digital DLL device is provided which can reduce an error with respect to a target delay amount. The device provides a delay to an input clock signal so as to equally divide a clock cycle T thereof into N parts, and includes first variable delay sections and second variable delay sections, each of which is formed of an arbitrary number of unit delay buffers connected in series with one another. A phase comparison section makes a compare between the phase of the input clock signal and the phase of an output signal which is the input signal having been delayed while passing through all the first and second variable delay sections, and outputs a result of the comparison. A delay control section calculates a total number of unit delay buffers S required based on the phase comparison result, sets a quotient Q of S divided by N to be the number of unit delay buffers for each of the first variable delay sections, and allocates a remainder R of S divided by N to the second variable delay sections, respectively.

Abstract: A data transmission system efficiently transmits data of high quality by accurately restoring the sequence of the transmitted data at a receiving circuit. The data transmission system includes a periodic data generating unit for generating periodic data, a parallel/serial converting unit for multiplexing parallel transmission data and the periodic data and converting multiplexed data into serial data, a serial data sending unit for sending the serial data, a serial data receiving unit for receiving the serial data, a serial/parallel converting unit for converting the serial data into parallel data, a periodic data string detecting unit for detecting a periodic data string from strings of the parallel data, and a transmission data restoring unit for restoring the transmission data based on the detected periodic data string.

Abstract: A data transmission system efficiently transmits data of high quality by accurately restoring the sequence of the transmitted data at a receiving circuit. The data transmission system includes a periodic data generating unit for generating periodic data, a parallel/serial converting unit for multiplexing parallel transmission data and the periodic data and converting multiplexed data into serial data, a serial data sending unit for sending the serial data, a serial data receiving unit for receiving the serial data, a serial/parallel converting unit for converting the serial data into parallel data, a periodic data string detecting unit for detecting a periodic data string from strings of the parallel data, and a transmission data restoring unit for restoring the transmission data based on the detected periodic data string.

Abstract: A differential input circuit which can positively operate over a wide input range is provided. The differential input circuit includes a first constant current source of a current mirror type which generates a positive current and a second constant current source of a current mirror type which generates a negative current. The first and second constant current sources constitute a differential amplifier circuit. A current switch which is connected to a positive input and a negative input is also connected to said first and second constant current sources so that an operating point of the differential amplifier circuit can be changed.

Abstract: A digital-to-analog converter of a current addition type using weighted resistors, includes an input resistor network (4) for providing a resistance dependent on a digital input signal having a predetermined number of bits, and an adder (3) having a first input terminal coupled to the input resistor network and a second input terminal connectable to receive a reference potential, for adding a signal obtained at the first input terminal and the reference potential. The adder also has an output terminal via which a result of an adding operation is output, and the result of the adding operation shows an analog signal corresponding to the digital input signal.

Abstract: A successive approximation analog to digital converter is provided with a variable reference voltage. A comparator compares an analog input voltage and an analog comparison voltage to obtain a digital output signal. Before the analog comparison voltage becomes lower than the analog input voltage, the first time after the analog to digital conversion starts, the second digital signal is changed in response to a first clock signal to decrease the reference voltage so that the first digital signal output form the first register is not changed. After the analog comparison voltage becomes lower than the analog input voltage the first time after the analog to digital conversion starts, the second digital signal is not changed so that the reference voltage is kept constant. The first digital signal is then changed in response to a second clock signal and the digital output signal to change the analog comparison voltage, whereby the bit member of the digital-to-analog converter is reduced.