Abstract: A first dynamic flash memory cell formed on a first Si pillar 25a including an N+ layer 21a, a P layer 22a, and an N+ layer 21b, and a second dynamic flash memory cell formed on a second Si pillar 25b including a P layer 22b and an N+ layer 21c, the first dynamic flash memory cell and the second dynamic flash memory cell sharing the N+ layer 21b that is connected to a first bit line BL1, are stacked on top of one another on a P-layer substrate 20 to form a dynamic flash memory. In plan view, a first plate line PL1, a first word line WL1, a second word line WL2, and a second plate line PL2 extend in the same direction and are formed to be perpendicular to a direction in which the first bit line BL1 extends.

Abstract: A memory device includes a plurality of pages arrayed in a column direction in a plan view, each page being constituted by a plurality of memory cells arrayed in a row direction on a substrate. Each of the memory cells included in each of the pages includes a semiconductor base material, first and second impurity regions positioned at respective ends of the semiconductor base material, first, second, and third gate conductor layers. The first and second impurity regions, the first, second, and third gate conductor layers are connected to a source line, a bit line, a first select gate line, a plate line, and a second select gate line, respectively. Upon operation end of page write operation and page read operation, voltage of the plate line is set to negative voltage lower than 0 V through capacitive coupling of the plate line and each of the first and second select gate lines to improve data retention characteristics of a write memory cell.

Abstract: A memory device including a semiconductor element includes two stacked memory cells including a first impurity region, first and second gate conductor layers, a second impurity region, third and fourth gate conductor layers, and a third impurity region on a P layer substrate in order from below in a vertical direction and configured to perform data write, read, and erase operation with voltage applied to each gate conductor layer. The first impurity region is connected to a first bit line. One of the first and second gate conductor layers and the other are connected to a word line and a plate line, respectively. The third and fourth gate conductor layers are each connected to the word line or plate line connected to the second or first gate conductor layer, respectively. The second and third impurity regions are connected to a source line and a second bit line, respectively.

Abstract: A first N+ layer, a first P layer, a second N+ layer, a second P layer, and a third N+ layer are formed on a P layer substrate in order from below vertically, a first gate insulating layer surrounds the first P layer, a second gate insulating layer surrounds the second P layer, first and second gate conductor layers surround the first gate insulating layer, and third and fourth gate conductor layers surround the second gate insulating layer. A first wiring layer is connected to the first N+ layer, a second wiring layer is connected to the second N+ layer, and a third wiring layer is connected to the third N+ layer. The first and second gate conductor layers, the second wiring layer, and the third and fourth gate conductor layers have identical shapes in a plan view and are orthogonal to the first and third wiring layers.

Abstract: A memory device includes pages in a column direction on a substrate and memory cells in each page in a row direction in plan view. Each memory cell includes a semiconductor base, first and second impurity regions, connected to a source line and a bit line, respectively, at both ends of the semiconductor base, and first and second gate conductor layers, one of which is connected to a word line and the other of which is connected to a plate line. Page erase, page write, and read operations are performed by controlling voltages applied to the source, bit, word, and plate lines. A first operation of outputting data of a first page to an input/output circuit via a sense amplifier circuit and a second operation of reading data of a second page of the same bank as the first page to the bit line are performed in parallel.

Abstract: A memory device includes pages arranged in columns and each constituted by a plurality of memory cells on a substrate, voltages applied to a first gate conductor layer, a second gate conductor layer, a first impurity layer, and a second impurity layer in each memory cell included in each of the pages are controlled to perform a page write operation of retaining, inside a channel semiconductor layer, a group of positive holes generated by an impact ionization phenomenon or by a gate-induced drain leakage current, and the voltages applied to the first gate conductor layer, the second gate conductor layer, the first impurity layer, and the second impurity layer are controlled to perform a page erase operation of discharging the group of positive holes from inside the channel semiconductor layer.

Abstract: A memory device includes pages in a column direction on a substrate and memory cells in each page in a row direction in plan view. Each memory cell includes a semiconductor base, first and second impurity regions, connected to a source line and a bit line, respectively, at both ends of the semiconductor base, and first and second gate conductor layers, one of which is connected to a word line and the other of which is connected to a plate line. A continuous operation of a page erase operation and a page write operation is performed by controlling voltages applied to the source line, the bit line, the word line, and the plate line without performing a reset operation for returning the voltage applied to the plate line to a ground voltage.

Abstract: A memory device includes pages in a column direction on a substrate and memory cells in each page in a row direction in plan view. Each memory cell includes a semiconductor base, first and second impurity regions at both ends of the semiconductor base, and first and second gate conductor layers. A page erase operation, a page write operation, and a page read operation are performed by controlling voltages applied to the first and second impurity regions and the first and second gate conductor layers. In a first page group including at least one page, a refresh operation of increasing positive holes is performed in a memory cell storing logical data “1”. The refresh operation is performed continuously to an N-th page group.

Abstract: Si pillars 22a to 22d stand on an N+ layer 21 connected to a source line SL. Lower portions of the Si pillars 22a to 22d are surrounded by a HfO2 layer 25a, which is surrounded by TiN layers 26a and 26b that are respectively connected to plate lines PL1 and PL2 and are isolated from each other. Upper portions of the Si pillars 22a to 22d are surrounded by a HfO2 layer 25b, which is surrounded by TiN layers 28a and 28b that are respectively connected to word lines WL1 and WL2 and are isolated from each other. A thickness Lg1 of the TiN layer 26a on a line X-X? is smaller than twice a thickness Lg2 of the TiN layer 26a on a line Y-Y? and is larger than or equal to the thickness Lg2. The thickness Lg1 of the TiN layer 28a on the line X-X? is smaller than twice the thickness Lg2 of the TiN layer 28a on the line Y-Y?.

Abstract: A dynamic flash memory includes a p layer as a semiconductor base material, first and second n+ layers on opposite sides thereof, first and second gate insulating layers in contact with each other and partially covering the p layer, and first and second gate conductor layers electrically isolated from each other and respectively provided on the first and second gate insulating layers. The first and second n+ layers and first and second gate conductor layers are respectively connected to source, bit, word, and plate lines. During writing, 1.0 V, 1.5 V, and 1.2 V are sequentially applied to the bit, plate, and word lines, respectively. During erasing, 2 V is applied to the plate line, and then, a voltage applied to each terminal is always set 0 V or greater (e.g., 0.6 V for the bit line). Further, during reading, voltages are sequentially applied to the bit, plate, and word lines.

Abstract: A memory device includes pages, each being composed of a plurality of memory cells arrayed on a substrate in row form, and controls voltages to be applied to a first gate conductor layer, a second gate conductor layer, a first impurity layer, and a second impurity layer of each of the memory cells included in the pages to perform a page write operation of holding a hole group generated by an impact ionization phenomenon or a gate induced drain leakage current in a channel semiconductor layer, and controls voltages to be applied to the first gate conductor layer, the second gate conductor layer, the third gate conductor layer, the fourth gate conductor layer, the first impurity layer, and the second impurity layer to perform a page erase operation of removing the hole group out of the channel semiconductor layer.

Abstract: A memory device includes a page made up of plural memory cells arranged in a column on a substrate, and a page write operation is performed to hold positive hole groups generated by an impact ionization phenomenon, in a channel semiconductor layer by controlling voltages applied to a first gate conductor layer, a second gate conductor layer, a first impurity region, and a second impurity region of each memory cell contained in the page and a page erase operation is performed to remove the positive hole groups out of the channel semiconductor layer by controlling voltages applied to the first gate conductor layer, the second gate conductor layer, the first impurity region, and the second impurity region.

Abstract: A memory device includes pages arranged in a column direction and each constituted by memory cells arranged in a row direction in plan view on a substrate, each memory cell includes a semiconductor body, first and second impurity regions, and first and second gate conductor layers, and in a page read operation, a first refresh operation of increasing by an impact ionization phenomenon, the number of positive holes in the semiconductor body of a memory cell for which page writing has been performed and a second refresh operation of decreasing the number of positive holes in the semiconductor body of a memory cell for which page writing has not been performed are performed and a third refresh operation for a memory cell, in a page, in which the logical “1” data is stored is performed by using latch data in a sense amplifier circuit.

Abstract: A semiconductor memory device includes a semiconductor base body (Si pillar) erected or horizontally laid on a substrate; first and second impurity regions located on opposite ends of the semiconductor base body; and gate insulating layer and first and second gate conductor layers located between the impurity regions, surrounding the semiconductor base body. By applying voltages to the impurity regions and gate conductor layers, a current is passed between the impurity regions, thereby causing impact ionization phenomenon in a semiconductor base body to generate electron groups and positive hole groups. A memory write operation is performed to remove the electron groups from the semiconductor base body and hold part of the positive hole groups in the semiconductor base body. A memory erase operation is performed by removing positive hole groups held in the semiconductor base body from the first and/or second impurity region(s). Two semiconductor elements make up one memory cell.

Abstract: A second band-like mask material layer having a first band-like mask material layer of a same planar shape on its top is formed on a mask material layer on a semiconductor layer. Then, fourth band-like mask material layers having third band-like mask material layers of same planar shape on their top are formed on both side surfaces of the first and second band-like mask material layers. Sixth band-like mask material layers having fifth band-like mask material layers of same planar shape on their top are formed on the outside thereof. Then, an orthogonal band-like mask material layer is formed on the first band-like mask material layer, in a direction orthogonal to a direction in which the first band-like mask material layer extends. Semiconductor pillars are formed on overlapping areas of this orthogonal band-like mask material layer and the second and sixth band-like mask material layers by etching the semiconductor layer.

Abstract: A memory device includes pages arranged in a column direction and each constituted by memory cells arranged in a row direction on a substrate, each memory cell includes a semiconductor body, first and second impurity regions, and first and second gate conductor layers, the first and second impurity regions and first and second gate conductor layers are connected to source, bit, word, and plate lines respectively, and a page read operation includes a first refresh operation of increasing by an impact ionization phenomenon, a group of positive holes in the semiconductor body of a memory cell for which page writing has been performed and a subsequent second refresh operation of making some of a group of positive holes in the semiconductor body of a memory cell for which page writing has not been performed disappear and decreasing the number of positive holes.

Abstract: A memory apparatus includes a page including a plurality of memory cells arranged in a column on a substrate. Each of voltages applied to first and second gate conductor layers and first and second impurity layers in each memory cell included in the page is controlled to perform a page write operation of retaining holes, which have been formed through an impact ionization phenomenon or using a gate induced drain leakage current, in a semiconductor base material, or each of voltages applied to the first and second gate conductor layers, third and fourth gate conductor layers, and the first and second impurity layers is controlled to perform a page erase operation of removing the holes from the semiconductor base material, and further lowering a voltage of the semiconductor base material through capacitive coupling with the first gate conductor layer and the second gate conductor layer.

Abstract: A memory device includes pages arranged in a column direction and each constituted by memory cells arranged in a row direction on a substrate, each memory cell includes a semiconductor body, first and second impurity regions, and first and second gate conductor layers, the first and second impurity regions and first and second gate conductor layers are connected to source, bit, word, and plate lines respectively, and voltages applied to these lines are controlled to perform an erase operation of collecting a group of positive holes in the semiconductor body of a selected memory cell in a part adjacent to the first gate conductor layer and making some of the group of positive holes disappear and a page write operation of increasing by an impact ionization phenomenon, the number of positive holes in the semiconductor body of a selected memory cell in a page.

Abstract: A memory device includes pages each constituted by a plurality of memory cells arranged in columns on a substrate, voltages applied to a first gate conductor layer, a second gate conductor layer, a first impurity region, and a second impurity region in each memory cell included in each page are controlled to perform a page write operation of retaining a group of positive holes, generated by an impact ionization phenomenon or a gate-induced drain leakage current, inside a semiconductor body, the voltages applied to the first gate conductor layer, the second gate conductor layer, the first impurity region, and the second impurity region are controlled to perform a page erase operation of discharging the group of positive holes from inside the semiconductor body and further lowering a voltage of the semiconductor body with capacitive coupling with the first gate conductor layer and with the second gate conductor layer, and in the page erase operation, at least two or more pages are simultaneously selected from a

Abstract: A semiconductor element memory device includes a first block including first memory cells arranged in a matrix, and/or a second block including second memory cells each formed of two memory cells. The memory device is configured to perform a data hold operation of controlling voltages to be applied to plate lines, word lines, a source line, odd-numbered bit lines, and even-numbered bit lines to hold, in a semiconductor base, a positive hole group generated by an impact ionization phenomenon or a gate-induced drain leakage current, and a data erase operation of controlling voltages to be applied to the plate lines, the word lines, the source line, the odd-numbered bit lines, and the even-numbered bit lines to discharge the positive hole group from the semiconductor base. The number of first blocks and the number of second blocks are variable in the memory device that is in operation.