Abstract: A plurality of dynamic flash memory cells are arranged in a matrix on a substrate, a first dynamic flash memory cell and a second dynamic flash memory cell overlap each other in a vertical direction or horizontal direction of a substrate, and voltages applied to a select gate line common to the memory cells, a plate line, a first bit line and a second bit line that are independent, and a source line are controlled to perform a data erase operation of the first and second dynamic flash memory cells, an independent data write operation or data write prohibition operation of the first and second dynamic flash memory cells, and a data read operation of the first and second dynamic flash memory cells.

Abstract: A first insulating layer 21 is disposed on a substrate 20. N+ layers 2 are separated from the insulating layer and in directions horizontal and vertical to the substrate. P layers 1 contact the n+ layers 2 and extend in the horizontal direction. N+ layers 3 contact the p layers 1. Gate insulating layers 4 cover the p layers 1 and part of the n+ layers 2 and 3. Second gate conductor layers 6 are electrically separated from a first gate conductor layer 5 contacting the gate insulating layers 4. A conductor layer 12 contacts the n+ layers 2. A conductor layer 13 contacts the n+ layers 3. A second insulating layer 22 contacts the first gate conductor layer 5, the n+ layers 2, and the conductor layer 12. A third insulating layer 23 contacts the second gate conductor layers 6, the n+ layers 3, and the conductor layer 13.

Abstract: A p layer extending in a direction horizontal to a substrate is provided separately from the substrate. An n+ layer is provided on one side of the layer. A gate insulating layer partially covers the layers. A gate conductor layer partially covers the layer. A gate insulating layer partially covering the layer is provided separately from the layer. A gate conductor layer partially covers the layer. An n+ layer is provided at part of the p layer between the layers. The layers are connected to a bit line, a source line, a word line, and a plate line, respectively. Memory operation of a dynamic flash memory cell is performed by manipulating voltage of each line.

Abstract: A memory device includes pages each composed of memory cells arrayed in columns on a substrate. A page write operation of retaining a hole group formed by impact ionization inside a channel semiconductor layer, and a page erase operation of discharging the hole group from the channel semiconductor layer are performed. A first impurity layer is connected to a source line, a second impurity layer to a bit line, a first gate conductor layer to a first selection gate line, a second gate conductor layer to a plate line, a third gate conductor layer to a second selection gate line, and a bit line to a sense amplifier circuit. Page data of a memory cell group selected in at least one page is read to the bit line. Zero volts or less is applied to the plate line of the memory cell connected to an unselected page.

Abstract: On a substrate Sub, a semiconductor base material (Si pillar) that stands on the substrate in a vertical direction or that extends along the substrate in a horizontal direction a first impurity layer and a second impurity layer that are disposed on respective ends of the semiconductor base material, a first gate conductor layer, and a second gate conductor layer that surround the semiconductor base material between the first impurity layer and the second impurity layer, and a channel semiconductor layer are disposed. Voltages are applied to perform a memory write operation of discharging a group of electrons from the channel semiconductor layer and retaining some of a group of positive holes in the channel semiconductor layer generated inside the channel semiconductor layer by a gate-induced drain leakage current, and a memory erase operation of discharging the group of positive holes retained in the channel semiconductor layer.

Abstract: First and second impurity layers are formed on a first semiconductor layer on a substrate. A third gate insulating layer covers side walls of the impurity layers and the first semiconductor layer. First and second gate conductor layers and a second insulating layer are formed in a groove, and n+-layers connected to source and bit lines are formed at ends of a second semiconductor layer formed on the second impurity layer and covered with a second gate insulating layer, on which a third gate conductor layer connected to a word line is formed. An operation of maintaining holes generated in a channel region of the second semiconductor layer by impact ionization or a GIDL current near the gate insulating layer and an operation of discharging the holes from the channel region are performed by controlling voltages applied to the source, bit, and word lines and first and second plate lines.

Abstract: A plurality of dynamic flash memory cells are arranged in a matrix shape on a substrate, a first dynamic flash memory cell and a second dynamic flash memory cell overlap each other in a vertical or horizontal direction of the substrate, voltages applied to a selection gate line, a plate line, and a bit line which are common to the first and second dynamic flash memory cells, an independent first source line, and an independent second source line are controlled to perform a data erase operation on the first and second dynamic flash memory cells, a data write operation on one of the first and second dynamic flash memory cells, a data write-protect operation on another of the first and second dynamic flash memory cells, and a data read operation on one of the first and second dynamic flash memory cells.

Abstract: A memory device includes pages including memory cells arranged on a substrate. Voltages applied to first and second gate conductor layers and first and second impurity regions in each memory cell are controlled to retain a group of positive holes. The first and second impurity regions and first and second gate conductor layers are connected to source, bit, plate, and word lines. In a page write operation, a channel semiconductor layer is at a first data retention voltage. In a page erase operation, the group of positive holes are discharged by controlling the voltages, the channel semiconductor layer is at a second data retention voltage, a positive voltage pulse is applied to at least one of the word and plate lines of a selected page, and a ground voltage is applied to the word and plate lines of a non-selected page and to all of the source and bit lines.

Abstract: A memory device includes pages each including memory cells arranged on a substrate. Voltages applied to first and second gate conductor layers and first and second impurity layers in each memory cell are controlled to retain a group of positive holes. In a page write operation, a voltage of the channel semiconductor layer is made equal to a first data retention voltage. In a page erase operation, the group of positive holes are discharged by controlling the voltages, the voltage of the channel semiconductor layer is made equal to a second data retention voltage, and erase and ground voltages are applied to selected and non-selected pages respectively. The first and second impurity layers and first and second gate conductor layers are connected to source, bit, plate, and word lines. The source, word, and plate lines are disposed parallel to the pages. The bit line is disposed perpendicular to the pages.

Abstract: In a semiconductor device including a memory element, a first mask material layer formed in a self-aligned manner and second mask material layers formed on both sides of the first mask material layer are used to form a second gate insulating layer and a second gate conductor layer 35 at the area of the first mask material layer and N layers and N+ layers at the areas of the second mask material layers, and a P-layer semiconductor pillar, a first gate insulating layer, a first gate conductor layer, a second gate insulating layer, a second gate conductor layer, N layers, and N+ layers, which are all elements constituting a memory cell, are formed in a self-aligned manner.

Abstract: A memory device includes pages each constituted by memory cells on a substrate. Voltages applied to first and second gate conductor layers and impurity layers in each memory cell are controlled to retain positive holes inside a channel semiconductor layer. In a page write operation, the voltage of the channel semiconductor layer is set to a first data retention voltage. In a page erase operation, the applied voltages are controlled to discharge the positive holes, and the voltage of the channel semiconductor layer is set to a second data retention voltage. At a second time after a first time, a memory re-erase operation is performed for the channel semiconductor layers at the second data retention voltage at the first time. At a third time after the second time, a memory re-write operation is performed for the channel semiconductor layers at the first data retention voltage at the first time.

Abstract: A first block in which a plurality of dynamic flash memory cells are arrange in a matrix shape on a substrate includes a first dynamic flash memory cell and a second dynamic flash memory cell. A second block disposed relative to the first block in a perpendicular direction or a parallel direction of the substrate includes a third dynamic flash memory cell and a fourth dynamic flash memory cell. Thus, dynamic flash memory cells are formed.

Abstract: A first block in which a plurality of dynamic flash memory cells are arrange in a matrix shape on a substrate includes a first dynamic flash memory cell and a second dynamic flash memory cell. A second block structured so as to be, together with the first block, in a mirror-symmetric configuration with respect to a shared shielded line includes a third dynamic flash memory cell and a fourth dynamic flash memory cell. Thus, dynamic flash memory cells are formed.

Abstract: A three-dimensional laminated dynamic flash memory device includes a plurality of laminated memory cells on a substrate. In a first memory cell, a semiconductor layer is made of a first semiconductor layer extending in a first direction and a second semiconductor layer connected to one side of the first semiconductor layer and extending in a second direction orthogonal to the first direction in a plan view.

Abstract: A dynamic flash memory is formed by stacking, on a first impurity layer on a P-layer substrate, a first insulating layer, a first material layer, a second insulating layer, a second material layer, a third insulating layer, a third material layer, and a fourth material layer, forming a first hole penetrating these layers on the P-layer substrate, forming a semiconductor pillar by embedding the first hole with a semiconductor, removing the first, second, and third material layers to form second, third, and fourth holes, by oxidizing an outermost surface of the semiconductor pillar exposing in the second, third, and fourth holes to form first, second, and third gate insulating layers, and forming first, second, and third gate conductor layers embedded in the second, third, and fourth holes.

Abstract: A memory apparatus includes pages each including a plurality of memory cells arranged in a column on a substrate. A voltage applied to each of a first gate conductor layer, a second gate conductor layer, a first impurity layer, and a second impurity layer in each memory cell included in each page is controlled to perform a page write operation for retaining holes, which have been formed through an impact ionization phenomenon or using a gate induced drain leakage current, in a channel semiconductor layer, or a voltage applied to each of the first gate conductor layer, the second gate conductor layer, a third gate conductor layer, a fourth gate conductor layer, the first impurity layer, and the second impurity layer is controlled to perform a page erase operation for removing the holes from the channel semiconductor layer. The first impurity layer in the memory cell connects to a source line. The second impurity layer connects to a bit line.

Abstract: A memory device includes pages arranged in columns and each constituted by a plurality of memory cells on a substrate, voltages applied to a first gate conductor layer, a second gate conductor layer, a first impurity layer, and a second impurity layer in each memory cell included in each of the pages are controlled to perform a page write operation of retaining, inside a channel semiconductor layer, a group of positive holes generated by an impact ionization phenomenon or by a gate-induced drain leakage current, and the voltages applied to the first gate conductor layer, the second gate conductor layer, the first impurity layer, and the second impurity layer are controlled to perform a page erase operation of discharging the group of positive holes from inside the channel semiconductor layer.

Abstract: In a semiconductor memory device, an n-type semiconductor layer is formed on a p-type semiconductor region on a substrate, a p-type first semiconductor layer having a columnar shape and concave top surface extends vertically from part of the n-type semiconductor layer, the p-type first semiconductor layer and n-type semiconductor layer are partially covered with an insulating layer, a first gate insulating layer is placed in contact with the p-type first semiconductor layer, a first gate conductor layer is placed in contact with the first gate insulating layer, and a second gate insulating layer, a second gate conductor layer, and an access transistor with an n+ layer provided on both sides are installed along a surface of the p-type first semiconductor layer.

Abstract: Provided on a substrate 1 are an N+ layer connecting to a source line SL, a first Si pillar as a P+ layer standing in an upright position along the vertical direction, and a second Si pillar as a P layer. An N+ layer connecting to a bit line BL is provided on the second Si pillar. A first gate insulating layer is provided so as to surround the first Si pillar, and a second gate insulating layer is provided so as to surround the second Si pillar. A first gate conductor layer connecting to a plate line PL is provided so as to surround the first insulating layer, and a second gate conductor layer connecting to a word line WL is provided so as to surround the second insulating layer.

Abstract: A semiconductor device includes a substrate, and an N-type MOS transistor and a P-type MOS transistor on the substrate. In the semiconductor device, during an erase operation, the hole group in a P-type semiconductor layer, which is the body of the N-type MOS transistor, and the electron group in an N-type semiconductor layer, which is the body of the P-type MOS transistor, are decreased; and during a write operation, the hole group in the P-type semiconductor layer of the N-type MOS transistor and the electron group in the N-type semiconductor layer of the P-type MOS transistor are increased. The N-type MOS transistor and the P-type MOS transistor forms a logic circuit configured to provide an output in a high impedance state (Hi-Z state) during the erase operation and to provide an output of a logic “1” or a logic “0” in a low impedance state during the write operation.