Patents by Inventor Nozomu Harada

Nozomu Harada has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10877345
    Abstract: A light control film to be bonded to a panel member for a vehicle includes film substrates, conductive layers, and a liquid crystal layer. The conductive layers are on surfaces of the film substrates opposed to each other, respectively. The liquid crystal layer is sandwiched between conductive layers. The light control film is switchable between a first state with a first haze percentage and a second state with a second haze percentage that is lower than the first haze percentage. Each film substrate includes at least an acrylic imide layer made of acrylic imide. Each conductive layer includes a thin silver film or a copper wire mesh.
    Type: Grant
    Filed: October 29, 2019
    Date of Patent: December 29, 2020
    Assignees: TOYOTA BOSHOKU KABUSHIKI KAISHA, RIKEN TECHNOS CORPORATION, TDK CORPORATION
    Inventors: Masahiro Irie, Kanji Kobayashi, Kenji Okamoto, Nozomu Washio, Koji Mishima, Shouhei Harada, Kazushi Yamada
  • Publication number: 20200373415
    Abstract: A SiO2 layer 5 is formed in the bottom portion of a Si pillar 3 and on an i-layer substrate 2. Subsequently, a gate HfO2 layer 11b is formed so as to surround the side surface of the Si pillar 3, and a gate TiN layer 12b is formed so as to surround the HfO2 layer 11b. Subsequently, P+ layers 18 and 32 containing an acceptor impurity at a high concentration and serving as a source and a drain are simultaneously or separately formed by a selective epitaxial crystal growth method on the exposed side surface of the bottom portion of and on the top portion of the Si pillar 3. Thus, an SGT is formed on the i-layer substrate 2.
    Type: Application
    Filed: August 13, 2020
    Publication date: November 26, 2020
    Inventors: Fujio MASUOKA, Nozomu HARADA, Yoshiaki KIKUCHI
  • Patent number: 10840155
    Abstract: Regions including SiO2 layers, Si3N4 layers, and SiO2 layers, and C layers and SiO2 layers, whose two ends in Y-Y? direction are located on the SiO2 layers and two ends in X-X? direction are coincident with the rectangular SiO2 layers, are formed on an i-layer. The i-layer is etched using the SiO2 layers as masks to form Si pillar bases, and the C layers and the SiO2 layers are removed. Thereafter, the SiO2 layers are formed into a circular shape by isotropic etching using the Si3N4 layers as masks, and Si pillars are formed on the Si pillar bases using the circular SiO2 layers as masks.
    Type: Grant
    Filed: April 10, 2019
    Date of Patent: November 17, 2020
    Assignee: UNISANTIS ELECTRONICS SINGAPORE PTE. LTD.
    Inventors: Fujio Masuoka, Nozomu Harada
  • Patent number: 10825822
    Abstract: In an SRAM cell circuit, an N+ layer 12a and a P+ layer 13a, which are present between first gate connection W layers 22a and 22b connecting to gate TiN layers 23a and 23b in plan view, which connect to the bottom portions of Si pillars 11a and 11b, and which extend in the horizontal direction, connect through a second gate connection W layer 29a to a first gate connection W layer 22c, which connects to the gate TiN layers 23a and 23b and extend in the horizontal direction. The second gate connection W layer 29a has a bottom portion within the first gate connection W layer 22c, and has an upper surface positioned lower than the upper surfaces of the gate TiN layers 23a to 23f and the first gate connection W layers 22a to 22d.
    Type: Grant
    Filed: December 19, 2018
    Date of Patent: November 3, 2020
    Assignee: UNISANTIS ELECTRONICS SINGAPORE PTE. LTD.
    Inventors: Fujio Masuoka, Nozomu Harada, Hiroki Nakamura, Min Soo Kim, Zheng Tao
  • Publication number: 20200321903
    Abstract: Provided is a control device for an AC rotating electric machine, which includes: a temperature detection unit configured to detect a temperature of a protection unit provided in an object to be protected when a current is supplied from a power conversion circuit including a switching element to the AC rotating electric machine and output, as a detected temperature, one of the temperature and a temperature of the object to be protected that is estimated from the temperature; a temperature compensation unit configured to calculate, through use of the detected temperature output from the temperature detection unit, a compensated temperature equal to or higher than the detected temperature; and a torque limiting unit configured to limit, through use of the compensated temperature calculated by the temperature compensation unit, a torque command value input thereto.
    Type: Application
    Filed: February 19, 2020
    Publication date: October 8, 2020
    Applicant: Mitsubishi Electric Corporation
    Inventors: Shingo HARADA, Keiichi ENOKI, Tomohisa SHODA, Nozomu KAMIOKA, Ryosuke SHIGEMATSU, Kazuhiko OTSUKA
  • Patent number: 10734391
    Abstract: A first contact hole is formed so as to extend to a NiSi layer as a lower wiring conductor layer connecting to an N+ layer of an SGT formed within a Si pillar, and so as to extend through a NiSi layer as an upper wiring conductor layer connecting to a gate TiN layer, and a NiSi layer as an intermediate wiring conductor layer connecting to an N+ layer. A second contact hole is formed so as to extend to the NiSi layer, and surround, in plan view, the first contact hole. An insulating SiO2 layer is formed on a side surface of the NiSi layer. A wiring metal layer in the contact holes connects the NiSi layer and the NiSi layer to each other.
    Type: Grant
    Filed: January 3, 2019
    Date of Patent: August 4, 2020
    Assignee: Unisantis Electronics Singapore Pte. Ltd.
    Inventors: Fujio Masuoka, Nozomu Harada
  • Publication number: 20200227553
    Abstract: An SGT is formed that includes Si pillars. The SGT includes WSi2 layers serving as wiring alloy layers and constituted by first alloy regions that are connected to the entire peripheries of impurity regions serving as sources or drains located in lower portions of the Si pillars, are formed in a self-aligned manner with the impurity regions in a tubular shape, and contain the same impurity atom as the impurity regions and a second alloy region that is partly connected to the peripheries of the first alloy regions and contains the same impurity atom as the impurity regions.
    Type: Application
    Filed: March 27, 2020
    Publication date: July 16, 2020
    Inventors: Fujio MASUOKA, Nozomu HARADA
  • Patent number: 10658371
    Abstract: A method for producing a pillar-shaped semiconductor device includes, forming a first semiconductor pillar, a second semiconductor pillar, and a third semiconductor pillar on a substrate. A gate insulating layer and gate conductor layer are formed surrounding each of the pillars and impurity regions are formed in each pillar. The gate conductor layer is selectively processed to form gate conductors around the pillars and to interconnect the gate conductors.
    Type: Grant
    Filed: December 19, 2018
    Date of Patent: May 19, 2020
    Assignee: UNISANTIS ELECTRONICS SINGAPORE PTE. LTD.
    Inventors: Fujio Masuoka, Nozomu Harada
  • Patent number: 10651180
    Abstract: A method for producing a pillar-shaped semiconductor device includes steps of forming, on the side surface of an N+ layer (38b) of the top portion of a Si pillar (6b) and the side surface of the top portion of a W layer (43a), ring-shaped SiO2 layers and an AlO layer (51) in outer peripheral portions surrounding the ring-shaped SiO2 layers; etching the ring-shaped SiO2 layers through the AlO layer serving as a mask, to form ring-shaped contact holes; and filling the contact holes with W layers (52a, 52b), to form ring-shaped W layers (52a, 52d) being in contact with the side surface of the N+ layer (38b) and the side surface of the top portion of the W layer (43a), and having constant widths in plan view.
    Type: Grant
    Filed: November 29, 2018
    Date of Patent: May 12, 2020
    Assignee: UNISANTIS ELECTRONICS SINGAPORE PTE. LTD.
    Inventors: Fujio Masuoka, Nozomu Harada
  • Patent number: 10651181
    Abstract: The method for producing a pillar-shaped semiconductor device includes a step of forming a tubular SiO2 layer that surrounds side surfaces of a P+ layer 38a and N+ layers 38b and 8c formed on a Si pillar 6b by epitaxial crystal growth, forming an AlO layer 51 on a periphery of the SiO2 layer, forming a tubular contact hole by etching the tubular SiO2 layer using the AlO layer 51 as a mask, and filling the contact hole with W layers 52c, 52d, and 52e to form tubular W layers 52c, 52d, and 52e (including a buffer conductor layer) that have an equal width when viewed in plan and are in contact with side surfaces of the tops of the P+ layer 38a and the N+ layers 38b and 8c.
    Type: Grant
    Filed: April 2, 2019
    Date of Patent: May 12, 2020
    Assignee: UNISANTIS ELECTRONICS SINGAPORE PTE. LTD.
    Inventors: Fujio Masuoka, Nozomu Harada, Hiroki Nakamura, Phillipe Matagne, Yoshiaki Kikuchi
  • Patent number: 10651189
    Abstract: A method for producing a pillar-shaped semiconductor memory device includes forming a mask on a semiconductor substrate and etching to form a semiconductor pillar on the semiconductor substrate. A tunnel insulating layer is formed and a data charge storage insulating layer is formed so as to surround the tunnel insulating layer, and a first conductor layer and a second interlayer insulating layer are formed on the semiconductor pillar. A stacked material layer is formed in a direction perpendicular to an upper surface of the semiconductor substrate, the stacked material layer including the first conductor layer and the second interlayer insulating layer. Data writing and erasing due to charge transfer between the semiconductor pillar and the data charge storage insulating layer through the tunnel insulating layer is performed by application of a voltage to the first conductor layer.
    Type: Grant
    Filed: October 1, 2018
    Date of Patent: May 12, 2020
    Assignee: UNISANTIS ELECTRONICS SINGAPORE PTE. LTD.
    Inventors: Fujio Masuoka, Nozomu Harada
  • Publication number: 20200142226
    Abstract: A light control film to be bonded to a panel member for a vehicle includes film substrates, conductive layers, and a liquid crystal layer. The conductive layers are on surfaces of the film substrates opposed to each other, respectively. The liquid crystal layer is sandwiched between conductive layers. The light control film is switchable between a first state with a first haze percentage and a second state with a second haze percentage that is lower than the first haze percentage. Each film substrate includes at least an acrylic imide layer made of acrylic imide. Each conductive layer includes a thin silver film or a copper wire mesh.
    Type: Application
    Filed: October 29, 2019
    Publication date: May 7, 2020
    Applicants: TOYOTA BOSHOKU KABUSHIKI KAISHA, RIKEN TECHNOS CORPORATION, TDK CORPORATION
    Inventors: Masahiro IRIE, Kanji KOBAYASHI, Kenji OKAMOTO, Nozomu WASHIO, Koji MISHIMA, Shouhei HARADA, Kazushi YAMADA
  • Patent number: 10644151
    Abstract: A surround gate MOS transistor (SGT) includes a silicon pillar and tungsten silicide or cobalt silicide wiring alloy layers constituted by first alloy regions connected to the entire peripheries of impurity regions serving as sources or drains in lower portions of the silicon pillar. The first alloy regions are formed in a self-aligned manner with the impurity regions in a tubular shape, and contain the same impurity atoms as the impurity regions. A second alloy region is partly connected to the peripheries of the first alloy regions and contains the same impurity atoms as the impurity regions.
    Type: Grant
    Filed: April 30, 2019
    Date of Patent: May 5, 2020
    Assignee: Unisantis Electronics Singapore Pte. Ltd.
    Inventors: Fujio Masuoka, Nozomu Harada
  • Publication number: 20200119166
    Abstract: The method for producing a pillar-shaped semiconductor device includes a step of providing a structure that includes, on an i layer substrate, a Si pillar and an impurity region located in a lower portion of the Si pillar and serving as a source or a drain, a step of forming a SiO2 layer that extends in a horizontal direction and is connected to an entire periphery of the impurity region in plan view, a step of forming a SiO2 layer on the SiO2 layer such that the SiO2 layer surrounds the Si pillar in plan view, a step of forming a resist layer that is partly connected to the SiO2 layer in plan view, and a step of forming a SiO2 layer by etching the SiO2 layer below the SiO2 layer and the resist layer using the SiO2 layer and the resist layer as masks.
    Type: Application
    Filed: December 6, 2019
    Publication date: April 16, 2020
    Inventors: Fujio MASUOKA, Nozomu HARADA
  • Publication number: 20200119193
    Abstract: An SGT is formed that includes Si pillars. The SGT includes WSi2 layers serving as wiring alloy layers and constituted by first alloy regions that are connected to the entire peripheries of impurity regions serving as sources or drains located in lower portions of the Si pillars, are formed in a self-aligned manner with the impurity regions in a tubular shape, and contain the same impurity atom as the impurity regions and a second alloy region that is partly connected to the peripheries of the first alloy regions and contains the same impurity atom as the impurity regions.
    Type: Application
    Filed: December 16, 2019
    Publication date: April 16, 2020
    Inventors: Fujio MASUOKA, Nozomu HARADA
  • Patent number: 10593682
    Abstract: A method for producing a semiconductor memory device includes forming two Si pillars on a substrate. In the Si pillars, inverter circuits are formed. The inverter circuits include drive N-channel SGTs each including first and second N+ layers functioning as a source and a drain, and load SGTs each including first and second P+ layers functioning as a source and drain. Selection SGTs each including third and fourth N+ layers functioning as a source and a drain are formed above SiO2 layers disposed above the inverter circuits. The first N+ layer is connected to a ground wiring metal layer. The first P+ layers are connected to a power supply wiring metal layer through a NiSi layer. Gate TiN layers are connected to a word-line wiring metal layer through a NiSi layer. The third N+ layers are connected to an inverted bit-line wiring metal layer and a bit-line wiring metal layer.
    Type: Grant
    Filed: March 8, 2019
    Date of Patent: March 17, 2020
    Assignee: UNISANTIS ELECTRONICS SINGAPORE PTE. LTD.
    Inventors: Fujio Masuoka, Nozomu Harada
  • Patent number: 10553715
    Abstract: An SGT is formed that includes Si pillars. The SGT includes WSi2 layers serving as wiring alloy layers and constituted by first alloy regions that are connected to the entire peripheries of impurity regions serving as sources or drains located in lower portions of the Si pillars, are formed in a self-aligned manner with the impurity regions in a tubular shape, and contain the same impurity atom as the impurity regions and a second alloy region that is partly connected to the peripheries of the first alloy regions and contains the same impurity atom as the impurity regions.
    Type: Grant
    Filed: March 9, 2018
    Date of Patent: February 4, 2020
    Assignee: UNISANTIS ELECTRONICS SINGAPORE PTE. LTD.
    Inventors: Fujio Masuoka, Nozomu Harada
  • Publication number: 20200020812
    Abstract: An SGT circuit includes a first conductor layer which contains a semiconductor atom, which is in contact with an N+ region and a P+ region of a Si pillar, or a TiN layer, and whose outer circumference is located outside an outer circumference of a SiO2 layer in plan view, and a second conductor layer which contains a metal atom, which is connected to an outer periphery of the first conductor layer, and which extends in a horizontal direction.
    Type: Application
    Filed: September 24, 2019
    Publication date: January 16, 2020
    Inventors: Fujio MASUOKA, Nozomu HARADA
  • Patent number: 10535756
    Abstract: The method for producing a pillar-shaped semiconductor device includes a step of providing a structure that includes, on an i layer substrate, a Si pillar and an impurity region located in a lower portion of the Si pillar and serving as a source or a drain, a step of forming a SiO2 layer that extends in a horizontal direction and is connected to an entire periphery of the impurity region in plan view, a step of forming a SiO2 layer on the SiO2 layer such that the SiO2 layer surrounds the Si pillar in plan view, a step of forming a resist layer that is partly connected to the SiO2 layer in plan view, and a step of forming a SiO2 layer by etching the SiO2 layer below the SiO2 layer and the resist layer using the SiO2 layer and the resist layer as masks.
    Type: Grant
    Filed: January 7, 2019
    Date of Patent: January 14, 2020
    Assignee: UNISANTIS ELECTRONICS SINGAPORE PTE. LTD.
    Inventors: Fujio Masuoka, Nozomu Harada
  • Patent number: 10483376
    Abstract: A method for producing a semiconductor device includes depositing a first insulating film and a second insulating film on a planar semiconductor layer formed on a substrate; forming a first hole for forming a gate electrode in the second insulating film; filling the first hole with a first metal to form the gate electrode; forming a side wall formed of a third insulating film on an upper surface of the gate electrode and a side surface of the first hole; performing etching through, as a mask, the side wall formed of the third insulating film, to form a second hole in the gate electrode and the first insulating film; forming a gate insulating film on a side surface of the second hole; and epitaxially growing a semiconductor layer, within the second hole, on the planar semiconductor layer to form a first pillar-shaped semiconductor layer.
    Type: Grant
    Filed: July 24, 2019
    Date of Patent: November 19, 2019
    Assignee: UNISANTIS ELECTRONICS SINGAPORE PTE. LTD.
    Inventors: Fujio Masuoka, Hiroki Nakamura, Nozomu Harada