Abstract: An N+ layer 21 connected to a source line SL at both ends of Si pillars 23a to 23d standing in a vertical direction; N+ layers 30a and 30b connected to a bit line BL1; N+ layers 30c and 30d connected to a bit line BL2; the Si pillars 23a to 23d connected to the N+ layer 21; gate insulating layers 27a to 27d surrounding the Si pillars 23a to 23d; first gate conductor layers 28a and 28b surrounding the gate insulating layers 27a t 27d and connected to plate lines PL1 and PL2; and second gate conductor layers 29a and 29b connected to word lines WL1 and WL2 are disposed on a substrate 1. The Si pillars 23a and 23c have sections partially overlap each other in perspective view of the sections along line X1-X1? and line X2-X2?, and the same applies to the Si pillars 23b and 23d.

Abstract: A memory device includes a page made of a plurality of memory cells arranged in rows on a substrate. A page write operation is performed, during which, in each of the memory cells included in the page, a first voltage V1 is applied to a first drive control line PL, a second voltage V2 is applied to a word line WL, a third voltage V3 is applied to a source line SL, a fourth voltage V4 is applied to a bit line BL, a group of holes generated by an impact ionization phenomenon is retained in an inside of the channel semiconductor layer. A page erase operation is performed, during which the voltages to be applied to the first drive control line PL, the word line WL, the source line SL, and the bit line BL are controlled to discharge the group of holes from the inside of the channel semiconductor layer, and the voltage of the channel semiconductor layer is decreased.

Abstract: A SiO2 layer is disposed in the bottom portion of a Si pillar and on an i-layer substrate. A gate HfO2 layer 11b is disposed so as to surround the side surface of the Si pillar, and a gate TiN layer is disposed so as to surround the HfO2 layer. P+ layers are disposed that contain an acceptor impurity at a high concentration, serve as a source and a drain, and are simultaneously or separately formed by a selective epitaxial crystal growth method on the exposed side surface of the bottom portion of and on the top portion of the Si pillar. Thus, an SGT is formed on the i-layer substrate.

Abstract: A memory device includes pages each composed of memory cells arrayed in columns on a substrate. A page write operation of retaining a hole group formed by impact ionization inside a channel semiconductor layer, and a page erase operation of discharging the hole group from the channel semiconductor layer are performed. A first impurity layer is connected to a source line, a second impurity layer to a bit line, a first gate conductor layer to a first selection gate line, a second gate conductor layer to a drive control line, a third gate conductor layer to a second selection gate line, and a bit line to a sense amplifier circuit. Page data of a memory cell group selected in at least one page is read to the bit line. Zero volts or less is applied to the drive control line of the memory cell connected to an unselected page.

Abstract: A memory device includes pages each constituted by memory cells, and a page write operation and a page erase operation are performed. First and second impurity layers and first and second gate conductor layers in each memory cell is connected to a source line, a bit line, a word line, and a driving control line. In a page read operation, page data is read. In the page write and read operations, a selected driving control line is lowered to zero volt at a first reset time, the driving control line is isolated from a driving circuit at a second reset time, thereby putting the driving control line in a zero-volt floating state, and a selected word line is set at zero volt at a third reset time, thereby putting the driving control line in a negative-voltage floating state by capacitive coupling between the word line and the driving control line.

Abstract: A memory device includes pages each constituted by memory cells, and a page write operation of retaining a group of positive holes, inside a channel semiconductor layer, generated by an impact ionization phenomenon by controlling voltages applied to first and second gate conductor layers and first and second impurity layers in each memory cell and a page erase operation of discharging the group of positive holes by controlling the voltages are performed. The first and second impurity layers and the first and second gate conductor layers of each memory cell is connected to a source line, a bit line connected to a sense amplifier circuit, a word line, and a driving control line respectively. In a page read operation, page data in a selected page is read to the bit lines. To the driving control line connected to a non-selected page, a voltage of zero volt or lower is applied.

Abstract: A Si pillar is formed in a memory region. A TiN layer to be connected to a plate line and a TiN layer to be connected to a word line are formed to extend in a horizontal direction, bend upward from the horizontal direction to a vertical direction in a memory region peripheral portion, and have upper surfaces on a same plane. The TiN layers are connected to metal wiring layers via contact holes formed on the upper surfaces thereof. A memory operation is performed by storing or not storing a group of holes generated by an impact ionization phenomenon in the Si pillar by controlling voltages to be applied to a source line, the plate line, the word line, and a bit line.

Abstract: A dynamic flash memory is formed by stacking, on a first impurity layer on a P-layer substrate, a first insulating layer, a first material layer, a second insulating layer, a second material layer, a third insulating layer, a third material layer, and a fourth material layer, forming a first hole penetrating these layers on the P-layer substrate, forming a semiconductor pillar by embedding the first hole with a semiconductor, removing the first, second, and third material layers to form second, third, and fourth holes, by oxidizing an outermost surface of the semiconductor pillar exposing in the second, third, and fourth holes to form first, second, and third gate insulating layers, and forming first, second, and third gate conductor layers embedded in the second, third, and fourth holes.

Abstract: A dynamic flash memory cell is formed by: stacking a first insulating layer, a first material layer, a second insulating layer, a second material layer, a third insulating layer, and a third material layer on a first impurity layer on a P-layer substrate; making a first hole that extends through the insulating layers and the material layers formed on the P-layer substrate; forming a semiconductor pillar by filling the first hole; making a second hole and a third hole by removing the first material layer and the second material layer; forming a first gate insulating layer and a second gate insulating layer by oxidizing a surface layer of the semiconductor pillar exposed inside the second hole and inside the third hole; and forming a first gate conductor layer and a second gate conductor layer by filling the second hole and the third hole.

Abstract: A memory device includes pages each constituted by memory cells on a substrate. Voltages applied to first and second gate conductor layers and impurity layers in each memory cell are controlled to retain positive holes inside a channel semiconductor layer. In a page write operation, the voltage of the channel semiconductor layer is set to a first data retention voltage. In a page erase operation, the applied voltages are controlled to discharge the positive holes, and the voltage of the channel semiconductor layer is set to a second data retention voltage. At a second time after a first time, a memory re-erase operation is performed for the channel semiconductor layers at the second data retention voltage at the first time. At a third time after the second time, a memory re-write operation is performed for the channel semiconductor layers at the first data retention voltage at the first time.

Abstract: A groove is formed in a first semiconductor layer 1, a sidewall of the groove is coated with a first insulating film 2, a first impurity layer 3 and a second impurity layer 4 thereon are disposed in the groove, a second semiconductor layer 7 is disposed on the second impurity layer, a first semiconductor is disposed at the other part, an n+ layer 6a and an n+ layer 6c are positioned at respective ends of the second semiconductor layer 7 and connected to a source line SL and a bit line BL, respectively, a first gate insulating layer 8 is formed on the second semiconductor layer 7, and a first gate conductor layer 9 is connected to a word line WL.

Abstract: A memory device includes a page constituted by multiple memory cells arranged in a row form on a substrate, and performs a page write operation of controlling voltages to be applied to first and second gate conductor layers and first and second impurity layers of each memory cell included in the page to hold a positive hole group formed by an impact ionization phenomenon inside a channel semiconductor layer; During a page read operation, page data of a memory cell group selected with the word line is read to the sense amplifier circuit, and a refresh operation is performed at least once before the page read operation to hold a positive hole group formed by an impact ionization phenomenon inside a channel semiconductor layer.

Abstract: First and second impurity layers are formed on a first semiconductor layer on a substrate. A third gate insulating layer covers side walls of the impurity layers and the first semiconductor layer. First and second gate conductor layers and a second insulating layer are formed in a groove, and n+-layers connected to source and bit lines are formed at ends of a second semiconductor layer formed on the second impurity layer and covered with a second gate insulating layer, on which a third gate conductor layer connected to a word line is formed. An operation of maintaining holes generated in a channel region of the second semiconductor layer by impact ionization or a GIDL current near the gate insulating layer and an operation of discharging the holes from the channel region are performed by controlling voltages applied to the source, bit, and word lines and first and second plate lines.

Abstract: An N+ layer 11a and N+ layers 13a to 13d that are disposed on both ends of Si pillars 12a to 12d standing on a substrate 10 in a vertical direction, a TiN layer 18a that surrounds a gate HfO2 layer 17a surrounding the Si pillars 12a to 12d and that extends between the Si pillars 12a and 12b, a TiN layer 18b that surrounds the gate HfO2 layer 17a and that extends between the Si pillars 12c and 12d, a TiN layer 26a that surrounds a gate HfO2 layer 17b surrounding the Si pillars 12a to 12d and that extends between the Si pillars 12a and 12b, and a TiN layer 26b that surrounds the gate HfO2 layer 17b and that extends between the Si pillars 12c and 12d are formed.

Abstract: A first semiconductor layer 1 is formed on a substrate, a first impurity layer 3 and a second impurity layer 4 extending in a vertical direction are sequentially disposed on part of the first semiconductor layer 1, their sidewalls and the semiconductor layer 1 are covered by a second gate insulating layer 2, a gate conductor layer 22 and a second insulating layer are disposed in a groove formed there, and a second semiconductor layer 7, n+ layers 6a and 6c positioned at respective ends of the layer 7 and connected to a source line SL and a bit line BL, respectively, a second gate insulating layer 8 formed to cover the second semiconductor layer 7, and a second gate conductor layer 9 connected to a word line WL are disposed on the second impurity layer.

Abstract: A method for forming a first impurity region 3 connected to lower portions of first semiconductor pillars and second impurity regions 4a and 4b connected to lower portions of second semiconductor pillars includes forming a semiconductor layer 100 having an impurity concentration lower than an impurity concentration of each of the first impurity region 3 and the second impurity regions 4a and 4b in impurity boundary regions of the first impurity region 3 and the second impurity regions 4a and 4b in a vertical direction and a horizontal direction.

Abstract: Material layers including first and second poly-Si layer are formed on a P-layer substrate. Holes which are parallel to each other and each of which is continuous in a first direction are formed in the material layers. The first and second poly-Si layers are each divided by the holes in a second direction orthogonal to the first direction in plan view. Gate insulating layers and P-layer Si pillars are formed in the holes. The P-layer Si pillars are isolated from one another by the gate insulating layers. A dynamic flash memory is formed in which a first gate conductor layer is connected to a plate line, a second gate conductor layer is connected to a word line, the P-layer Si pillars serve as channels, and one of the N+ layers below and above the P-layer Si pillars is connected to a source line.

Abstract: A memory device includes a page made up of plural memory cells arranged in a column on a substrate, and a page write operation is performed to hold positive hole groups generated by an impact ionization phenomenon, in a channel semiconductor layer by controlling voltages applied to a first gate conductor layer, a second gate conductor layer, a first impurity region, and a second impurity region of each memory cell contained in the page and a page erase operation is performed to remove the positive hole groups out of the channel semiconductor layer by controlling voltages applied to the first gate conductor layer, the second gate conductor layer, the first impurity region, and the second impurity region.

Abstract: An n+ layer 3a connected to a source line SL at both ends, an n+ layer 3b connected to a bit line BL, a first gate insulating layer 4a formed on a semiconductor substrate 1 existing on an insulating film 2, a gate conductor layer 16a connected to a plate line PL, a gate insulating layer 4b formed on the semiconductor substrate, and a second gate conductor layer 5b connected to a word line WL and having a work function different from a work function of the gate conductor layer 16a are disposed on the semiconductor substrate, and data hold operation of holding, near a gate insulating film, holes generated by an impact ionization phenomenon or gate-induced drain leakage current inside a channel region 12 of the semiconductor substrate 1 and data erase operation of removing the holes from inside the substrate 1 and the channel region 12 are performed by controlling voltage applied to the source line SL, the plate line PL, the word line WL, and the bit line BL.

Abstract: A memory device includes pages containing memory cells arranged in an array on a substrate. In each memory cell, a voltage applied to a first gate conductor layer, second gate conductor layer, third gate conductor layer, first impurity layer, and second impurity layer is controlled to form a hole group by impact ionization inside a channel semiconductor layer, and a page write operation of holding the hole group and a page erase operation of removing the hole group are performed. The first impurity layer is connected to a source line, the second impurity layer to a bit line, the first gate conductor layer to a first plate line, the second gate conductor layer to a second plate line, and the third gate conductor layer to a word line. A page erase operation is performed without inputting a positive or negative bias pulse to the bit line and the source line.