Abstract: Provided is a display device including a display panel, an optical sensor, a timing controller, a scan driver, a data driver, and an image controller. The timing controller controls an image refresh rate of the display panel based on a refresh rate control signal. Thus, the display device provides improved visibility.

Abstract: A nonvolatile memory device, including a first latch unit and a nonvolatile memory cell, and a method of writing data in a nonvolatile memory device are provided. The method includes receiving a first writing command or a second writing command from outside of the nonvolatile memory device, and writing first data stored in the first latch unit in the nonvolatile memory cell in response to the first or second writing command. The first data is retained in the first latch unit until the writing of the first data stored in the first latch unit in the nonvolatile memory cell is completed.

Abstract: A leakage current detection device includes a drive voltage generation circuit, a reference voltage generation circuit, a first capacitor, a second capacitor, a comparator, and a latch circuit. The drive voltage generation circuit provides a drive voltage to a test line in response to a charge control signal to charge the test line. The reference voltage generation circuit generates a first reference voltage and a second reference voltage, and provides the first reference voltage to a detection node in response to a switch control signal. The first capacitor is coupled between the test line and the detection node. The second capacitor is coupled between the detection node and a ground voltage. The comparator outputs a comparison signal by comparing a voltage of the detection node with the second reference voltage. The latch circuit latches the comparison signal, and outputs the latched comparison signal as a test result signal.

Abstract: A nonvolatile memory device, including a first latch unit and a nonvolatile memory cell, and a method of writing data in a nonvolatile memory device are provided. The method includes receiving a first writing command or a second writing command from outside of the nonvolatile memory device, and writing first data stored in the first latch unit in the nonvolatile memory cell in response to the first or second writing command. The first data is retained in the first latch unit until the writing of the first data stored in the first latch unit in the nonvolatile memory cell is completed.

Abstract: The present invention relates to a system for dynamically converting a webpage, which can construct a web application and a site for supporting a cross browser and a cross platform and, particularly, the system for dynamically converting a webpage comprises: a library storage unit for storing at least one constituent element which constitutes a webpage or a web application; a layout editing unit for arranging the constituent element selected from the library storage unit on a layout for configuring the webpage; an attribute editing unit for setting an attribute for each constituent element arranged by the layout editing unit; a contents editing unit for providing a function of editing contents arranged by the layout editing unit; a parameter converting unit for converting each constituent element arranged by the layout editing unit into a standard parameter value; a standard parameter information database for storing the standard parameter value converted by the parameter converting unit; a browser determinat

Abstract: A program verification circuit comprises a failed state counting unit and a failed bit counting unit. The failed state counting unit counts failed program states among a plurality of program states, and generates a first program mode signal indicating whether counting of failed bits is required. The failed bit counting unit selectively counts failed bits in response to the first program mode signal, and generates a second program mode signal indicating whether a program operation is completed.

Abstract: Provided is a programming method in a flash memory device. The programming method applies a first pass voltage to a selection word line and a non-selection word line, applies a local voltage to the non-selection word line, applies a second pass voltage to the selection word line, and applies a programming voltage to the selection word line.

Abstract: A page buffer includes a sense latch, a data latch and a page buffer controller. The sense latch is connected to a bit line, and is configured to set stored data in response to a sense latch control signal, and to change the stored data in response to a signal applied to the bit line in a data verification operation. The data latch is configured to store multi-bit data to be programmed in a program operation, and to set stored data in response to a data latch control signal in the data verification operation. The page buffer controller is configured to control the bit line in accordance with the multi-bit data stored in the data latch in the program operation, and to output the sense latch control signal and the data latch control signal in accordance with the multi-bit data stored in the data latch in response to a control signal in the data verification operation.

Abstract: A program verification circuit comprises a failed state counting unit and a failed bit counting unit. The failed state counting unit counts failed program states among a plurality of program states, and generates a first program mode signal indicating whether counting of failed bits is required. The failed bit counting unit selectively counts failed bits in response to the first program mode signal, and generates a second program mode signal indicating whether a program operation is completed.

Abstract: A page buffer includes a sense latch, a data latch and a page buffer controller. The sense latch is connected to a bit line, and is configured to set stored data in response to a sense latch control signal, and to change the stored data in response to a signal applied to the bit line in a data verification operation. The data latch is configured to store multi-bit data to be programmed in a program operation, and to set stored data in response to a data latch control signal in the data verification operation. The page buffer controller is configured to control the bit line in accordance with the multi-bit data stored in the data latch in the program operation, and to output the sense latch control signal and the data latch control signal in accordance with the multi-bit data stored in the data latch in response to a control signal in the data verification operation.

Abstract: Provided is a programming method in a flash memory device. The programming method applies a first pass voltage to a selection word line and a non-selection word line, applies a local voltage to the non-selection word line, applies a second pass voltage to the selection word line, and applies a programming voltage to the selection word line.

Abstract: A method of programming a memory device includes comparing a first verify voltage and a distribution voltage of at least one memory cell, and if a result of the comparison is a pass, adjusting the distribution voltage until the distribution voltage is higher than a second verify voltage while comparing the distribution voltage and the second verify voltage.

Abstract: A nonvolatile memory device and programming method and apparatus therefore are described that include operatively coupled first and second sense amplifiers having first and second data registers or latches, a storage circuit for storing a data of the second amplifier, a pass/fail check circuit for checking the content of the second data register whether a cell of the memory device has been sufficiently programmed and a restore circuit for resetting the second data register for reprogramming the device until sufficiently programmed.

Abstract: A method and apparatus for controlling two or more non-volatile memory devices includes activating a read enable signal or a write enable signal, which is input to the first and second non-volatile memory devices, using a controller. A first chip enable signal is alternately activated for selecting the first non-volatile memory device and a second chip enable signal is activated for selecting the second non-volatile memory device using the controller. This is done while the read enable signal or the write enable signal is input to the first and second non-volatile memory devices being activated. Accordingly, even when the minimum cycle of the controller is longer than that of a memory device read/write time is reduced, thereby improving read/write performance.

Abstract: Integrated circuit devices include operational circuits that are configured to operate from power supply voltages and from high voltages that are generated in the integrated circuit device from the power supply voltages. A circuit for measuring the high voltages is also provided in the integrated circuit. The circuit includes a common high voltage measurement pad and high voltage switch units connected to the common high voltage measurement pad. A respective high voltage switch unit is configured to transmit a corresponding one of the high voltages to the common high voltage measurement pad in response to a corresponding enable signal. The operational circuits may be non-volatile memory cells, such as flash memory cells. Related methods of measuring high voltages in an integrated circuit device are also described.

Abstract: An apparatus and method for generating pulsating noise in an audio device are provided. The apparatus and method mix audio signals processed by an audio play operation with pulsating noise generated by a pulsating noise generator if a brain wave induction mode is set in an audio device and output a result of the mixing operation through wired or wireless speaker. Therefore, a user can efficiently experience brain wave induction action based on the pulsating noise while he/she hears audio from the speaker.

Abstract: A nonvolatile memory device and programming method and apparatus therefore are described that include operatively coupled first and second sense amplifiers having first and second data registers or latches, a storage circuit for storing a data of the second amplifier, a pass/fail check circuit for checking the content of the second data register whether a cell of the memory device has been sufficiently programmed and a restore circuit for resetting the second data register for reprogramming the device until sufficiently programmed.

Abstract: A program method of a non-volatile memory device comprises setting a string select line to a predetermined voltage, setting a selected word line to a program voltage and unselected word lines to a pass voltage respectively. The program voltage is varied according to an arrangement of the selected word line. Problems arising from capacitive coupling between adjacent signal lines are alleviated.

Abstract: Disclosed are multi-channel PWM (Pulse Width Modulation) apparatuses and methods for modulating PCM-based multi-channel audio signals read from an optical medium into PWM-based multi-channel audio signals. A multi-channel PWM apparatus and method can reduce noise from amplifying PCM-based audio signals having adjacent signal processing paths. The multi-channel PWM apparatus and method selectively vary only gains of some channels in a plurality of channels in order to allow an audio signal applied to a pulse width modulator to have a different level in individual channels in a prescribed system condition (e.g., overload). The multi-channel PWM apparatus can selectively enable a subset among a plurality of pulse width modulators to reduce unnecessary driving and noise. Thus, preferred embodiments can reduce or prevent deterioration of output audio signals.

Abstract: A multi-chip semiconductor memory device includes of a plurality of memory chips sharing a predetermined chip enable signal. Each of the plurality of memory chips includes an active internal power supply generation circuit configured to convert an external power supply voltage into an internal power supply voltage and to be disabled in response to deactivation of a predetermined drive control signal. Each of the plurality of memory chips also includes a conversion control circuit for generating the drive control signal, wherein the drive control signal is deactivated in an interval in which any of the plurality of memory chips is in an active interval.