Abstract: A flash memory device may include: a plurality of main bit lines; a plurality of redundant bit lines; a plurality of first page buffers respectively organized as a plurality of first page buffer groups which are connected to main bit lines; a plurality of second page buffers respectively organized as a plurality of second page buffer groups which are connected to the redundant bit lines; each of the first and second page buffers including an output P/F terminal to provide pass/fail data; a plurality of fuses corresponding to the pluralities of the first and second page buffer groups, respectively, each of the fuses having one end commonly connected to the P/F terminals in a corresponding page buffer group and the other end connected to a signal line; and a pass/fail check circuit to determine an overall pass/fail signal based upon a signal on the signal line.

Abstract: A program method of a non-volatile memory device comprises setting a string select line to a predetermined voltage, setting a selected word line to a program voltage and unselected word lines to a pass voltage respectively. The program voltage is varied according to an arrangement of the selected word line. Problems arising from capacitive coupling between adjacent signal lines are alleviated.

Abstract: The present invention relates to a nonvolatile semiconductor memory, that is, a flash memory and especially to a NAND type flash memory device capable of selectively controlling data input/output units by an address control. In the NAND type flash memory device, a memory cell array is divided into a plurality of blocks, and a data input/output path is selectively controlled by a predetermined data rate option and introduced addresses to perform data input/output operations at a ×8 or ×16 speed in one chip.

Abstract: A nonvolatile memory device and programming method and apparatus therefore are described that include operatively coupled first and second sense amplifiers having first and second data registers or latches, a storage circuit for storing a data of the second amplifier, a pass/fail check circuit for checking the content of the second data register whether a cell of the memory device has been sufficiently programmed and a restore circuit for resetting the second data register for reprogramming the device until sufficiently programmed.

Abstract: A flash memory device having a memory cell string is programmed. The flash memory device includes a plurality of memory cells. During a programming cycle, application of a program voltage to a channel region of the plurality of memory cells is delaying until after a gate of each of the memory cells of the plurality of memory cells that is to be programmed has reached a programming voltage Vpgm.

Abstract: The present invention relates to a nonvolatile semiconductor memory, that is, a flash memory and especially to a NAND type flash memory device capable of selectively controlling data input/output units by an address control. In the NAND type flash memory device, a memory cell array is divided into a plurality of blocks, and a data input/output path is selectively controlled by a predetermined data rate option and introduced addresses to perform data input/output operations at a ×8 or ×16 speed in one chip.

Abstract: A flash memory device may include: a plurality of main bit lines; a plurality of redundant bit lines; a plurality of first page buffers respectively organized as a plurality of first page buffer groups which are connected to main bit lines; a plurality of second page buffers respectively organized as a plurality of second page buffer groups which are connected to the redundant bit lines; each of the first and second page buffers including an output P/F terminal to provide pass/fail data; a plurality of fuses corresponding to the pluralities of the first and second page buffer groups, respectively, each of the fuses having one end commonly connected to the P/F terminals in a corresponding page buffer group and the other end connected to a signal line; and a pass/fail check circuit to determine an overall pass/fail signal based upon a signal on the signal line.

Abstract: A flash memory device includes a plurality of data pads to receive data from an adjacent plurality of data pins. A signal generation circuit generates a plurality of selection signals responsive to bit organization and package signals. A buffer circuit buffers the data from the plurality of data pads. An input switch receives the data from the buffer circuit and transmits the data to the data lines responsive to the selection signals. And an output switch provides data to the buffer circuit responsive to the selection signals.

Abstract: Disclosed are multi-channel PWM (Pulse Width Modulation) apparatuses and methods for modulating PCM-based multi-channel audio signals read from an optical medium into PWM-based multi-channel audio signals. A multi-channel PWM apparatus and method can reduce noise from amplifying PCM-based audio signals having adjacent signal processing paths. The multi-channel PWM apparatus and method selectively vary only gains of some channels in a plurality of channels in order to allow an audio signal applied to a pulse width modulator to have a different level in individual channels in a prescribed system condition (e.g., overload). The multi-channel PWM apparatus can selectively enable a subset among a plurality of pulse width modulators to reduce unnecessary driving and noise. Thus, preferred embodiments can reduce or prevent deterioration of output audio signals.

Abstract: An apparatus for improving reception sensitivity of a public wave receiver includes power devices formed in a power supply of the public wave receiver, and a shielding plate for shielding noise generated by the power devices. A signal line for connecting an antenna used for the public wave receiver to a public wave receiver main body and a ground line are formed coaxially to each other by a shield layer.

Abstract: A nonvolatile memory device and programming method and apparatus therefore are described that include operatively coupled first and second sense amplifiers having first and second data registers or latches, a storage circuit for storing a data of the second amplifier, a pass/fail check circuit for checking the content of the second data register whether a cell of the memory device has been sufficiently programmed and a restore circuit for resetting the second data register for reprogramming the device until sufficiently programmed.