Abstract: A method of manufacturing a power device includes: etching a trench in a semiconductor body; forming at least a first layer of dielectric material in the trench; forming a first field electrode structure on the at least one first layer of dielectric material and in the trench; forming at least one second layer of dielectric material on the first electrode structure and in the trench; and forming a second field electrode structure on the at least one second layer of dielectric material and in the trench.

Abstract: A semiconductor chip is provided. The semiconductor chip may include a front side including a control chip contact and a first controlled chip contact, a back side including a second controlled chip contact, a backside metallization formed over the back side in contact with the second controlled chip contact, and a stop region extending at least partially along an outer edge of the back side between a contact portion of the backside metallization and the outer edge of the back side. The contact portion is configured to be attached to an electrically conductive structure by a die attach material, a surface of the stop region is recessed with respect to a surface of the contact portion, and/or the surface of the stop region has a lower wettability with respect to the die attach material than the contact portion.

Abstract: The disclosure relates to a power device, having a channel region, a gate region formed aside the channel region, for controlling a channel formation, a drift region formed vertically below the channel region, a field electrode formed in a field electrode trench extending vertically into the drift region, wherein the field electrode comprises a first and a second field electrode structure, the first field electrode structure capacitively coupling to a first section of the drift region and the second field electrode structure capacitively coupling to a second section of the drift region, arranged vertically above the first section, the first and the second field electrode structure formed with a vertical overlap and adapted to balance a capacitive coupling between the first and the second field electrode structure and between the field electrode and the drift region.

Abstract: An electronic circuit and a method are disclosed. The electronic circuit includes: a first transistor device having a load path between a first load path node and a second load path node; and a clamping circuit connected to the load path of the first transistor device. The clamping circuit includes: a second transistor device having a load path connected in parallel with the load path of the first transistor device, and a control node; and a drive circuit configured to drive the second transistor device. The drive circuit includes a clamping element and a resistor connected in series between the first and second load path nodes of the first transistor device. The drive circuit is configured to drive the second transistor device dependent on a voltage across the resistor. The first transistor device and the clamping circuit are integrated in a same semiconductor die.

Abstract: A semiconductor device is described. The semiconductor device includes: a trench formed in a first main surface of a semiconductor substrate; a field plate electrode disposed in a lower part of the trench; an insulating material separating the field plate electrode from the semiconductor substrate; and a strain-inducing material embedded in the field plate electrode. The field plate electrode comprises a different material than the strain-inducing material. The trench adjoins a region of the semiconductor substrate through which current flows in a first direction during operation of the semiconductor device. The strain-inducing material reaches an upper surface of the field plate electrode and terminates before reaching a lower surface of the field plate electrode, such that part of the field plate electrode is interposed between a lower surface of the strain-inducing material and a bottom of the trench. Additional device embodiments and methods of producing the device are also described.

Abstract: A semiconductor device is described. The semiconductor device includes: a semiconductor substrate; a trench formed in a first main surface of the semiconductor substrate; a field plate electrode in the trench and reaching a same level as the first main surface of the semiconductor substrate; an insulating material that separates the field plate electrode from the semiconductor substrate; and a material embedded in the field plate electrode. The field plate electrode is made of a different material than the material embedded in the field plate electrode. The trench adjoins a region of the semiconductor substrate through which current flows in a first direction during operation of the semiconductor device. Additional device embodiments and methods of producing the semiconductor device are also described.

Abstract: An electronic circuit and a method are disclosed. The electronic circuit includes: a first transistor device having a load path between a first load path node and a second load path node; and a clamping circuit connected to the load path of the first transistor device. The clamping circuit includes: a second transistor device having a load path connected in parallel with the load path of the first transistor device, and a control node; and a drive circuit configured to drive the second transistor device. The drive circuit includes a clamping element and a resistor connected in series between the first and second load path nodes of the first transistor device. The drive circuit is configured to drive the second transistor device dependent on a voltage across the resistor. The first transistor device and the clamping circuit are integrated in a same semiconductor die.

Abstract: The application relates to a semiconductor die including a device in an active area of the die. The device includes a field electrode region formed in a field electrode trench extending vertically into a semiconductor body. The field electrode region includes a first and a second field electrode stacked vertically above each other in the field electrode trench. An edge termination structure laterally between the active area and a lateral edge region of the die includes a first and a second shield electrode arranged laterally consecutive between the active area and the lateral edge region to stepwise decrease an electrical potential between the edge region and the active area.

Abstract: A semiconductor device includes transistor cells formed in a semiconductor substrate and electrically coupled in parallel to form a power transistor. The transistor cells include trenches extending in a vertical direction from a first main surface of the semiconductor substrate into the semiconductor substrate. The trenches include: a gate electrode; a field electrode below the gate electrode; and at least one dielectric material separating the gate electrode and the field electrode from one another and from the semiconductor substrate. The at least one dielectric material is thicker between the field electrode and a bottom of the trenches than between the field electrode and each sidewall of the trenches. Each trench has a tapered width that decreases over a depth of the trench in the vertical direction. A method of producing the semiconductor device is also described.

Abstract: The present application relates to a semiconductor circuit, including a semiconductor device and a delay element. The semiconductor device includes a gate electrode and a field electrode in a field electrode trench. The delay element is electrically connected between the gate electrode and the field electrode. The delay element is configured to delay a charging of the field electrode compared to a charging of the gate electrode. A semiconductor die that includes the semiconductor circuit and a method of manufacturing the semiconductor die are also described.

Abstract: A semiconductor device is described. The semiconductor device includes: a semiconductor substrate having an edge, an active area spaced inward from the edge, and an edge termination area laterally surrounding the active area; and a plurality of transistor cells formed in the active area, each transistor cell including a source region of a first conductivity type and a body region of a second conductivity type opposite the first conductivity type. The edge termination area includes a plurality of needle-shaped compensation trenches and is devoid of complete transistor cells. A body doping region of the second conductivity type and that includes the body regions of the transistor cells extends from the active area into the edge termination area. The body doping region in the edge termination area is physically and electrically isolated from the body doping region in the active area.

Abstract: The application relates to a semiconductor die having a semiconductor body including an active region, an insulation layer on the semiconductor body, and a sodium stopper formed in the insulation layer. The sodium stopper is arranged in an insulation layer groove which intersects the insulation layer vertically and extends around the active region. The sodium stopper is formed of a tungsten material that at least partly fills the insulation layer groove. Both the insulation layer groove and the tungsten material extend into the semiconductor body.

Abstract: In an embodiment, a semiconductor die includes a base substrate having a first major surface, a second major surface opposing the first major surface, and a material other than a Group III nitride. A Group III nitride layer arranged on the first major surface of the base substrate includes a Group III nitride device. A first metallization structure is arranged on the Group III nitride layer and a second metallization structure is arranged on the second major surface of the base layer. The second metallization structure includes an electrically insulating inorganic layer arranged directly on the second major surface.

Abstract: The application relates to a semiconductor transistor device, having a source region, a body region including a channel region extending in a vertical direction, a drain region, a gate region arranged aside the channel region in a lateral direction, and a body contact region made of an electrically conductive material, wherein the body contact region forms a body contact area, the body contact region being in an electrical contact with the body region via the body contact area, and wherein the body contact area is tilted with respect to the vertical direction and the lateral direction.

Abstract: A semiconductor device includes: a plurality of transistor cells formed in a semiconductor body. The plurality of transistor cells includes: a plurality of stripe-shape gate trenches formed in a first main surface of the semiconductor body; and a plurality of field plate trenches separate from the stripe-shape gate trenches. At least one field plate trench is laterally interposed between each pair of neighboring stripe-shape gate trenches. Each stripe-shape gate trench includes a gate electrode, a gate dielectric between the gate electrode and a sidewall of the stripe-shape gate trench, and an oxide between the gate electrode and a bottom of the stripe-shape gate trench, the oxide having a vertical thickness that is greater than eight times a lateral thickness of the gate dielectric and/or greater than a vertical thickness of the gate electrode. A method of producing the semiconductor device is also described.

Abstract: A semiconductor die is described. The semiconductor die includes a semiconductor body having an active region, a metallization formed on the semiconductor body, and a passivation formed on the metallization. The metallization includes at least one of a titanium layer, a titanium nitride layer, and a tungsten layer. The passivation includes a silicon oxide layer. Corresponding methods of manufacturing and using the semiconductor die are also described.

Abstract: In an exemplary embodiment, a semiconductor device includes: a semiconductor substrate having a first major surface; a trench positioned in the semiconductor substrate and having a width, a base, and a side wall extending from the base to the first major surface; a first electrically insulating layer that lines the base and the side wall of the trench; and an electrically insulating plug that is positioned in the trench and that extends across the entire width of the trench. The plug has a lower surface that forms an interface with the first electrically insulating layer and an upper surface. The upper surface of the plug is coplanar with the first major surface of the semiconductor substrate or positioned within the trench.

Abstract: In an embodiment, a semiconductor wafer is provided that includes a plurality of component positions with scribe line regions located at least one of adjacent to and between the component positions. The component positions include an active device structure. An auxiliary structure is positioned in one or more of the scribe line regions. The auxiliary structure is electrically coupled to an auxiliary contact pad which includes tungsten. The auxiliary structure does not interact with or affect the active device structure in the component positions.

Abstract: A power semiconductor device includes a semiconductor substrate. A signal routing structure is disposed above the semiconductor substrate. The signal routing structure comprises a specific metal. A solderable power pad forms a power terminal of the power semiconductor device. The solderable power pad comprises the specific metal. An electrically insulating dielectric passivation layer is disposed between the solderable power pad and the signal routing structure.

Abstract: A semiconductor device includes a semiconductor die having a vertical transistor device with a source electrode, a drain electrode and a gate electrode, the semiconductor die having a first surface and a second surface opposing the first surface. A first metallization structure is located on the first surface and includes at least one source pad coupled to the source electrode, at least one drain pad coupled to the drain electrode and at least one gate pad coupled to the gate electrode, A second metallization structure is electrically insulated from the semiconductor die by the electrically insulating layer.