Patents by Inventor Oliver Blank

Oliver Blank has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200239812
    Abstract: A detergent or cleaning agent, in particular a cleaning agent for hard surfaces, having at least two phases which are different from each other. The detergent or cleaning agent includes at least one first phase and at least one second phase that is different, with the at least one first phase being solid and the at least one second phase having at least one polymer and at least one polyvalent alcohol.
    Type: Application
    Filed: April 2, 2020
    Publication date: July 30, 2020
    Applicant: Henkel AG & Co. KGaA
    Inventors: Oliver Kurth, Inga Kerstin Vockenroth, David Matulla, Volker Blank
  • Patent number: 10727331
    Abstract: A semiconductor device includes a semiconductor substrate having drift and body regions. The drift region includes upper and lower drift regions. An active area includes a plurality of spicular trenches extending through the body region and into the drift region. Each spicular trench in the active area has a lower end which together define a lower end of the upper drift region extending towards a first side and a lower drift region extending from the lower end of the upper drift region towards a second side. The edge termination area includes spicular termination trenches extending at least into the upper drift region. A surface doping region arranged in the upper drift region in the edge termination area extends to the first side, is spaced apart from the lower end of the upper drift region, and has a net doping concentration lower than that of the upper drift region.
    Type: Grant
    Filed: June 29, 2018
    Date of Patent: July 28, 2020
    Assignee: Infineon Technologies Austria AG
    Inventors: Cedric Ouvrard, Adam Amali, Oliver Blank, Michael Hutzler, David Laforet, Harsh Naik, Ralf Siemieniec, Li Juin Yip
  • Patent number: 10636883
    Abstract: A method of forming a semiconductor device includes forming a source trench extending into a semiconductor body from a first surface of the semiconductor body, forming a source trench dielectric and a source trench electrode in the source trench, forming a gate trench dielectric and a gate trench electrode in a gate trench extending into the semiconductor body from the first surface, forming a body region of a first conductivity type between the gate and source trenches, forming a source region of a second conductivity type different from the first conductivity type between the gate and source trenches, forming an interconnection electrically coupling the body region and the source trench electrode, wherein the interconnection adjoins a lateral face of the source trench electrode of the body region, and forming a source contact on the source trench electrode at the first surface.
    Type: Grant
    Filed: February 20, 2019
    Date of Patent: April 28, 2020
    Assignee: Infineon Technologies Austria AG
    Inventor: Oliver Blank
  • Publication number: 20200127102
    Abstract: A semiconductor device includes a semiconductor substrate, a transistor cell region formed in the semiconductor substrate and an inner termination region formed in the semiconductor substrate and devoid of transistor cells. The transistor cell region includes a plurality of transistor cells and a gate structure that forms a grid separating transistor sections of the transistor cells from each other, each of the transistor sections including a needle-shaped first field plate structure extending from a first surface into the semiconductor substrate. The inner termination region surrounds the transistor cell region and includes needle-shaped second field plate structures extending from the first surface into the semiconductor substrate. The first field plate structures form a first portion of a regular pattern and the second field plate structures form a second portion of the same regular pattern.
    Type: Application
    Filed: November 22, 2019
    Publication date: April 23, 2020
    Inventors: Ralf Siemieniec, Oliver Blank, Franz Hirler, Michael Hutzler, David Laforet, Cedric Ouvrard, Li Juin Yip
  • Publication number: 20200127134
    Abstract: A semiconductor device includes: a gate trench extending into a Si substrate; a body region in the Si substrate, the body region including a vertical channel region adjacent a sidewall of the gate trench; a source region in the Si substrate above the body region; a contact trench extending into the Si substrate and separated from the gate trench by a portion of the source region and by a portion of the body region; an electrically conductive material in the contact trench; and a diffusion barrier structure interposed between a sidewall of the contact trench and the vertical channel region, the diffusion barrier structure including alternating layers of Si and oxygen-doped Si and configured to increase carrier mobility within the vertical channel region. Corresponding methods of manufacture are also described.
    Type: Application
    Filed: December 18, 2019
    Publication date: April 23, 2020
    Inventors: Oliver Blank, Thomas Feil, Maximilian Roesch, Martin Poelzl, Robert Haase, Sylvain Leomant, Bernhard Goller, Andreas Meiser
  • Patent number: 10626352
    Abstract: A detergent or cleaning agent, in particular a cleaning agent for hard surfaces, having at least two phases which are different from each other. The detergent or cleaning agent includes at least one first phase and at least one second phase that is different, with the at least one first phase being solid and the at least one second phase having at least one polymer and at least one polyvalent alcohol.
    Type: Grant
    Filed: January 22, 2018
    Date of Patent: April 21, 2020
    Assignee: Henkel AG & Co. KGaA
    Inventors: Oliver Kurth, Inga Kerstin Vockenroth, David Matulla, Volker Blank
  • Patent number: 10580888
    Abstract: A semiconductor device includes a gate trench extending into a Si substrate, a body region in the Si substrate, the body region including a channel region which extends along a sidewall of the gate trench, a source region in the Si substrate above the body region, a contact trench extending into the Si substrate and separated from the gate trench by a portion of the source region and a portion of the body region, the contact trench being filled with an electrically conductive material which contacts the source region at a sidewall of the contact trench and a highly doped body contact region at a bottom of the contact trench, and a diffusion barrier structure formed along the sidewall of the contact trench and disposed between the highly doped body contact region and the channel region, the diffusion barrier structure including alternating layers of Si and oxygen-doped Si.
    Type: Grant
    Filed: August 8, 2018
    Date of Patent: March 3, 2020
    Assignee: Infineon Technologies Austria AG
    Inventors: Oliver Blank, Thomas Feil, Maximilian Roesch, Martin Poelzl, Robert Haase, Sylvain Leomant, Bernhard Goller, Andreas Meiser
  • Publication number: 20200052077
    Abstract: A power semiconductor die has a semiconductor body coupled to first and second load terminals, and at least one power cell. In a horizontal cross-section of the at least one power cell, a contact has a contact region which horizontally overlaps with a field plate electrode and horizontally protrudes from the field plate trench, and a recess region does not horizontally overlap with the contact region and extends into a horizontal circumference of the field plate trench.
    Type: Application
    Filed: August 9, 2019
    Publication date: February 13, 2020
    Inventors: Christof Altstaetter, Marcel Rene Mueller, Oliver Blank, David Laforet
  • Publication number: 20200052109
    Abstract: A semiconductor device includes a gate trench extending into a Si substrate, a body region in the Si substrate, the body region including a channel region which extends along a sidewall of the gate trench, a source region in the Si substrate above the body region, a contact trench extending into the Si substrate and separated from the gate trench by a portion of the source region and a portion of the body region, the contact trench being filled with an electrically conductive material which contacts the source region at a sidewall of the contact trench and a highly doped body contact region at a bottom of the contact trench, and a diffusion barrier structure formed along the sidewall of the contact trench and disposed between the highly doped body contact region and the channel region, the diffusion barrier structure including alternating layers of Si and oxygen-doped Si.
    Type: Application
    Filed: August 8, 2018
    Publication date: February 13, 2020
    Inventors: Oliver Blank, Thomas Feil, Maximilian Roesch, Martin Poelzl, Robert Haase, Sylvain Leomant, Bernhard Goller, Andreas Meiser
  • Patent number: 10510846
    Abstract: A semiconductor device includes a semiconductor substrate, a transistor cell region formed in the semiconductor substrate and an inner termination region formed in the semiconductor substrate and devoid of transistor cells. The transistor cell region includes a plurality of transistor cells and a gate structure that forms a grid separating transistor sections of the transistor cells from each other, each of the transistor sections including a needle-shaped first field plate structure extending from a first surface into the semiconductor substrate. The inner termination region surrounds the transistor cell region and includes needle-shaped second field plate structures extending from the first surface into the semiconductor substrate. The first field plate structures form a first portion of a regular pattern and the second field plate structures form a second portion of the same regular pattern.
    Type: Grant
    Filed: February 20, 2017
    Date of Patent: December 17, 2019
    Assignee: Infineon Technologies Austria AG
    Inventors: Ralf Siemieniec, Oliver Blank, Franz Hirler, Michael Hutzler, David Laforet, Cedric Ouvrard, Li Juin Yip
  • Patent number: 10453931
    Abstract: A semiconductor device comprises a semiconductor substrate structure comprising a cell region and an edge termination region surrounding the cell region. Further it comprises a plurality of needle-shaped cell trenches within the cell region reaching from a surface of the semiconductor substrate structure into the substrate structure and an edge termination trench within the edge termination region surrounding the cell region at the surface of the semiconductor substrate structure.
    Type: Grant
    Filed: November 9, 2018
    Date of Patent: October 22, 2019
    Assignee: Infineon Technologies Austria AG
    Inventors: Oliver Blank, Franz Hirler, Ralf Siemieniec, Li Juin Yip
  • Patent number: 10453929
    Abstract: A method of manufacturing a power metal oxide semiconductor field effect transistor includes: forming a field electrode in a field plate trench in a main surface of a semiconductor substrate; forming a gate trench in the main surface, the gate trench extending in a first direction parallel to the main surface; and for a gate electrode in the gate trench, the gate electrode being made of a gate electrode material that comprises a metal. The field plate trench is formed to have an extension length in the first direction which is less than double of an extension length of the field plate trench in a second direction, the second direction being perpendicular to the first direction.
    Type: Grant
    Filed: May 2, 2017
    Date of Patent: October 22, 2019
    Assignee: Infineon Technologies Austria AG
    Inventors: David Laforet, Oliver Blank, Michael Hutzler, Cedric Ouvrard, Ralf Siemieniec, Li Juin Yip
  • Publication number: 20190318995
    Abstract: In an embodiment, a semiconductor wafer is provided that includes a plurality of component positions with scribe line regions located at least one of adjacent to and between the component positions. The component positions include an active device structure. An auxiliary structure is positioned in one or more of the scribe line regions. The auxiliary structure is electrically coupled to an auxiliary contact pad which includes tungsten.
    Type: Application
    Filed: April 16, 2019
    Publication date: October 17, 2019
    Inventor: Oliver Blank
  • Publication number: 20190305092
    Abstract: A power semiconductor die has a semiconductor body coupled to a first load terminal and a second load terminal of the power semiconductor die and configured to conduct a load current between the load terminals. The die further comprises: a control trench structure for controlling the load current, the control trench structure extending into the semiconductor body along a vertical direction and arranged in accordance with a horizontal grid pattern having a plurality of grid openings; a plurality of power cells, each power cell being, in a horizontal cross-section, at least partially arranged in a respective one of the plurality of grid openings.
    Type: Application
    Filed: March 27, 2019
    Publication date: October 3, 2019
    Inventors: Oliver Blank, Marcel Rene Mueller, Cedric Ouvrard
  • Publication number: 20190277687
    Abstract: Dynamic change information is detected on a vehicle, that is transporting a load receiving structure. The dynamic operational information is monitored to identify a period of dynamic change in the operation of the vehicle. The period of dynamic change is used to define a sampling window. The dynamic operational information, during the sampling window, is provided to fill level classifier logic that identifies a fill level corresponding to the dynamic operational information. A fill level metric, indicative of the identified fill level, is generated, and an action signal is generated based upon the fill level metric.
    Type: Application
    Filed: March 6, 2018
    Publication date: September 12, 2019
    Inventors: SEBASTIAN BLANK, Oliver Grüenewald
  • Publication number: 20190267487
    Abstract: Disclosed is a transistor device with at least one gate electrode, a gate runner connected to the at least one gate electrode and arranged on top of a semiconductor body, and a gate pad arranged on top of the semiconductor body and electrically connected to the gate runner. The gate runner includes a first metal line, a second metal line on top of the first metal line, a first gate runner section, and at least one second gate runner section. The at least one second gate runner section is arranged between the first gate runner section and the gate pad. A cross sectional area of the second metal line in the at least one second gate runner section is less than 50% of the cross sectional area of the second metal line in the first gate runner section.
    Type: Application
    Filed: February 25, 2019
    Publication date: August 29, 2019
    Inventors: David Laforet, Oliver Blank, Cesar Augusto Braz, Gerhard Noebauer, Cedric Ouvrard
  • Publication number: 20190259709
    Abstract: A semiconductor wafer has a semiconductor body, an insulation layer on the semiconductor body, an active region with a power semiconductor die, the active region forming a part of the semiconductor body, a scribeline region arranged adjacent to the active region, and a passivation structure arranged above the insulation layer and exposing a section of the insulation layer. The exposed section of the insulation layer is terminated by a termination edge of the passivation structure. The semiconductor wafer also has an optically detectable reference feature configured to serve as a reference position during a wafer separation processing stage. The optically detectable reference feature is included in the active region, spatially displaced from the termination edge, and exposed by the passivation structure.
    Type: Application
    Filed: February 19, 2019
    Publication date: August 22, 2019
    Inventor: Oliver Blank
  • Patent number: 10388782
    Abstract: A semiconductor device includes a main transistor and a sense transistor. The main transistor is disposed in a semiconductor body and includes a plurality of sections which are individually controllable via separate gate electrodes disposed above the semiconductor body. The sense transistor is disposed in the same semiconductor body as the main transistor and has the same number of individually controllable sections as the main transistor. Each individually controllable section of the sense transistor is configured to mirror current flowing through one of the individually controllable sections of the main transistor and is connected to the same gate electrode as that individually controllable section of the main transistor. An electronic circuit that includes the semiconductor device and a current sense circuit that outputs a current sense signal representing the current mirrored by the sense transistor is also provided.
    Type: Grant
    Filed: December 17, 2014
    Date of Patent: August 20, 2019
    Assignee: Infineon Technologies Austria AG
    Inventors: Giuseppe Bernacchia, Riccardo Pittassi, Oliver Blank
  • Patent number: 10374078
    Abstract: A semiconductor device includes a plurality of striped-shaped trenches extending into a semiconductor substrate. At least one trench of a first group of trenches of the plurality of striped-shaped trenches is located between two trenches of a second group of trenches of the plurality of striped-shaped trenches. A gate of a transistor structure is located in each trench of the second group of trenches and a gate insulation layer is located between the gate and the semiconductor substrate in each trench of the second group of trenches. Trench insulation material is located in each trench of the first group of trenches. A thickness of the trench insulation material throughout each trench of the first group of trenches is at least two times larger than a thickness of the gate insulation layer in each trench of the second group of trenches.
    Type: Grant
    Filed: March 10, 2017
    Date of Patent: August 6, 2019
    Assignee: Infineon Technologies Austria AG
    Inventors: Oliver Blank, Britta Wutte
  • Patent number: 10355126
    Abstract: A method for manufacturing a semiconductor device includes: forming a recess in a semiconductor substrate, the recess having a bottom and a sidewall extending from the bottom to a first side of the semiconductor substrate; forming an auxiliary structure on the sidewall and the bottom of the recess and forming a hollow space within the recess; filling the hollow space with a filling material; forming a plug on the first side of the semiconductor substrate to cover the auxiliary structure at least on the sidewall of the recess; forming an opening in the plug to partially expose the auxiliary structure in the recess; removing the auxiliary structure at least partially from the sidewall of the recess to form cavities between the auxiliary structure and the sidewall; and sealing the opening in the plug.
    Type: Grant
    Filed: May 12, 2017
    Date of Patent: July 16, 2019
    Assignee: Infineon Technologies Austria AG
    Inventor: Oliver Blank