Patents by Inventor Oliver Blank

Oliver Blank has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20180166543
    Abstract: A semiconductor device comprises a semiconductor substrate structure comprising a cell region and an edge termination region surrounding the cell region. Further it comprises a plurality of needle-shaped cell trenches within the cell region reaching from a surface of the semiconductor substrate structure into the substrate structure and an edge termination trench within the edge termination region surrounding the cell region at the surface of the semiconductor substrate structure.
    Type: Application
    Filed: January 11, 2018
    Publication date: June 14, 2018
    Inventors: Oliver Blank, Franz Hirler, Ralf Siemieniec, Li Juin Yip
  • Patent number: 9960270
    Abstract: A method for manufacturing a semiconductor device includes: forming a recess in a semiconductor substrate, the recess having a bottom and a sidewall extending from the bottom to a first side of the semiconductor substrate; forming an auxiliary structure on the sidewall and the bottom of the recess and forming a hollow space within the recess; filling the hollow space with a filling material; forming a plug on the first side of the semiconductor substrate to cover the auxiliary structure at least on the sidewall of the recess; forming an opening in the plug to partially expose the auxiliary structure in the recess; removing the auxiliary structure at least partially from the sidewall of the recess to form cavities between the auxiliary structure and the sidewall; and sealing the opening in the plug.
    Type: Grant
    Filed: May 12, 2017
    Date of Patent: May 1, 2018
    Assignee: Infineon Technologies Austria AG
    Inventor: Oliver Blank
  • Patent number: 9941365
    Abstract: A method for producing a field-effect semiconductor device includes providing a semiconductor body with a first surface defining a vertical direction, defining an active area, forming a vertical trench from the first surface into the semiconductor body, forming a field dielectric layer at least on a side wall and a bottom wall of the vertical trench, depositing a conductive layer on the field dielectric layer, forming a closed cavity on the conductive layer in the vertical trench, and forming an insulated gate electrode on the closed cavity in the vertical trench.
    Type: Grant
    Filed: June 22, 2016
    Date of Patent: April 10, 2018
    Assignee: Infineon Technologies Austria AG
    Inventors: Stefan Sedlmaier, Markus Zundel, Franz Hirler, Johannes Baumgartl, Anton Mauder, Ralf Siemieniec, Oliver Blank, Michael Hutzler
  • Patent number: 9917160
    Abstract: A semiconductor device includes a semiconductor body, having a first surface, a gate electrode structure, which includes polycrystalline silicon, of an IGFET in a first trench extending from the first surface into the semiconductor body. The device also includes a semiconductor element, which is different from the gate electrode structure of the IGFET and includes polycrystalline silicon, in a second trench extending from the first surface into the semiconductor body, wherein the polycrystalline silicon of the IGFET and of the semiconductor element different therefrom ends below a top side of an insulation layer adjoining the first surface of the semiconductor body.
    Type: Grant
    Filed: April 14, 2016
    Date of Patent: March 13, 2018
    Assignee: Infineon Technologies AG
    Inventors: Andrew Christopher Graeme Wood, Oliver Blank, Martin Poelzl, Martin Vielemeyer
  • Patent number: 9905685
    Abstract: A semiconductor device includes compensation structures that extend from a first surface into a semiconductor portion. Sections of the semiconductor portion between neighboring ones of the compensation structures form semiconductor mesas. A field dielectric separating a field electrode in the compensation structures from the semiconductor portion includes a thermally grown portion, which directly adjoins the semiconductor portion. A not fully densified deposited portion of the field dielectric has a lower density than the thermally grown portion.
    Type: Grant
    Filed: April 27, 2016
    Date of Patent: February 27, 2018
    Assignee: Infineon Technologies Austria AG
    Inventors: Ralf Siemieniec, Oliver Blank, Mario Kleindienst, Stefan Kramp
  • Publication number: 20180026130
    Abstract: A method of manufacturing a semiconductor device includes: forming a trench extending into a semiconductor substrate and a polysilicon gate electrode in the trench; forming a body region of a first conductivity type in the substrate adjacent the trench and a source region of a second conductivity type adjacent the body region and the trench; forming a dielectric layer on the substrate; forming a gate metallization on the dielectric layer which covers part of the substrate and a source metallization on the dielectric layer which is electrically connected to the source region, spaced apart from the gate metallization and covering a different part of the substrate than the gate metallization; and forming a metal-filled groove in the polysilicon gate electrode which is electrically connected to the gate metallization. The metal-filled groove extends along a length of the trench underneath at least part of the source metallization.
    Type: Application
    Filed: August 17, 2017
    Publication date: January 25, 2018
    Inventors: Ralf Siemieniec, Oliver Blank, Li Juin Yip
  • Publication number: 20170338338
    Abstract: A method for manufacturing a semiconductor device includes: forming a recess in a semiconductor substrate, the recess having a bottom and a sidewall extending from the bottom to a first side of the semiconductor substrate; forming an auxiliary structure on the sidewall and the bottom of the recess and forming a hollow space within the recess; filling the hollow space with a filling material; forming a plug on the first side of the semiconductor substrate to cover the auxiliary structure at least on the sidewall of the recess; forming an opening in the plug to partially expose the auxiliary structure in the recess; removing the auxiliary structure at least partially from the sidewall of the recess to form cavities between the auxiliary structure and the sidewall; and sealing the opening in the plug.
    Type: Application
    Filed: May 12, 2017
    Publication date: November 23, 2017
    Inventor: Oliver Blank
  • Publication number: 20170309713
    Abstract: A semiconductor device includes a pair of stripe-shaped gate structures formed lengthwise in parallel in a first surface of a semiconductor body and extending into the semiconductor body, each stripe-shaped gate structure including a gate electrode and a gate dielectric separating the gate electrode from the semiconductor body. The semiconductor device further includes a plurality of field electrode structures formed in the semiconductor body between the pair of stripe-shaped gate structures, a body zone of a second conductivity type formed in the semiconductor body and extending between the pair of stripe-shaped gate structures, and a source zone of a first conductivity type opposite the second conductivity type formed in the body zone. Each field electrode structure includes a spicular or needle-shaped field electrode and a field dielectric adjacent the field electrode. Each spicular or needle-shaped field electrode has a diameter of at most 500 nm.
    Type: Application
    Filed: July 10, 2017
    Publication date: October 26, 2017
    Inventors: Franz Hirler, Oliver Blank, Ralf Siemieniec
  • Patent number: 9799729
    Abstract: A method of manufacturing a semiconductor device includes: forming field electrode structures extending in a direction vertical to a first surface in a semiconductor body; forming cell mesas from portions of the semiconductor body between the field electrode structures, including body zones forming first pn junctions with a drift zone; forming gate structures between the field electrode structures and configured to control a current flow through the body zones; and forming auxiliary diode structures with a forward voltage lower than the first pn junctions and electrically connected in parallel with the first pn junctions, wherein semiconducting portions of the auxiliary diode structures are formed in the cell mesas.
    Type: Grant
    Filed: January 6, 2017
    Date of Patent: October 24, 2017
    Assignee: Infineon Technologies Austria AG
    Inventors: Ralf Siemieniec, Oliver Blank, Franz Hirler, Martin Henning Vielemeyer
  • Patent number: 9799738
    Abstract: A semiconductor device includes a field electrode structure with a field electrode and a field dielectric surrounding the field electrode. A semiconductor body includes a transistor section surrounding the field electrode structure and including a source zone, a first drift zone section and a body zone separating the source zone and the first drift zone section. The body zone forms a first pn junction with the source zone and a second pn junction with the first drift zone section. A gate structure surrounds the field electrode structure and includes a gate electrode and a gate dielectric separating the gate electrode and the body zone. A contact structure directly adjoins the source and body zones and surrounds the field electrode structure equably with respect to the field electrode structure.
    Type: Grant
    Filed: August 7, 2015
    Date of Patent: October 24, 2017
    Assignee: Infineon Technologies Austria AG
    Inventors: Ralf Siemieniec, Oliver Blank, Michael Hutzler, David Laforet, Cedric Ouvrard, Li Juin Yip
  • Publication number: 20170271446
    Abstract: First reinforcement stripes are formed on a process surface of a base substrate. A first epitaxial layer covering the first reinforcement stripes is formed on the first process surface. Second reinforcement stripes are formed on the first epitaxial layer. A second epitaxial layer covering the second reinforcement stripes is formed on exposed portions of the first epitaxial layer. Semiconducting portions of transistor cells are formed in or portions of micro electromechanical structures are formed from the second epitaxial layer.
    Type: Application
    Filed: March 13, 2017
    Publication date: September 21, 2017
    Inventors: Ravi Keshav Joshi, Johannes Baumgartl, Oliver Blank, Oliver Hellmund, Martin Poelzl
  • Patent number: 9768290
    Abstract: A semiconductor device includes a semiconductor substrate, a body region of a first conductivity type in the substrate, a source region of a second conductivity type adjacent the body region, and a trench extending into the substrate. The trench contains a polysilicon gate electrode insulated from the substrate. The device further includes a dielectric layer on the substrate, a gate metallization on the dielectric layer and covering part of the substrate and a source metallization on the dielectric layer and electrically connected to the source region. The gate metallization includes two spaced apart fingers. The source metallization is spaced apart from the gate metallization and covers a different part of the substrate than the gate metallization. A metal-filled groove in the polysilicon gate electrode is electrically connected to the two spaced apart fingers, and extends along a length of the trench directly underneath at least part of the source metallization.
    Type: Grant
    Filed: June 23, 2015
    Date of Patent: September 19, 2017
    Assignee: Infineon Technologies Austria AG
    Inventors: Ralf Siemieniec, Oliver Blank, Li Juin Yip
  • Publication number: 20170263756
    Abstract: A semiconductor device includes a plurality of striped-shaped trenches extending into a semiconductor substrate. At least one trench of a first group of trenches of the plurality of striped-shaped trenches is located between two trenches of a second group of trenches of the plurality of striped-shaped trenches. A gate of a transistor structure is located in each trench of the second group of trenches and a gate insulation layer is located between the gate and the semiconductor substrate in each trench of the second group of trenches. Trench insulation material is located in each trench of the first group of trenches. A thickness of the trench insulation material throughout each trench of the first group of trenches is at least two times larger than a thickness of the gate insulation layer in each trench of the second group of trenches.
    Type: Application
    Filed: March 10, 2017
    Publication date: September 14, 2017
    Inventors: Oliver Blank, Britta Wutte
  • Publication number: 20170250256
    Abstract: A semiconductor device includes needle-shaped field plate structures extending from a first surface into transistor sections of a semiconductor portion in a transistor cell area. A grid structure separates the transistor sections from each other. The grid structure includes: stripe-shaped gate edge portions extending along one edge of the transistor sections, respectively; gate node portions wider than the gate edge portions and connecting two or more of the gate edge portions, respectively; and one or more connection sections of the semiconductor portion, wherein the one or more connection sections extend between neighboring transistor sections.
    Type: Application
    Filed: February 23, 2017
    Publication date: August 31, 2017
    Inventors: Ralf Siemieniec, Oliver Blank, David Laforet, Cedric Ouvrard, Li Juin Yip
  • Publication number: 20170250255
    Abstract: A semiconductor device includes a semiconductor substrate, a transistor cell region formed in the semiconductor substrate and an inner termination region formed in the semiconductor substrate and devoid of transistor cells. The transistor cell region includes a plurality of transistor cells and a gate structure that forms a grid separating transistor sections of the transistor cells from each other, each of the transistor sections including a needle-shaped first field plate structure extending from a first surface into the semiconductor substrate. The inner termination region surrounds the transistor cell region and includes needle-shaped second field plate structures extending from the first surface into the semiconductor substrate. The first field plate structures form a first portion of a regular pattern and the second field plate structures form a second portion of the same regular pattern.
    Type: Application
    Filed: February 20, 2017
    Publication date: August 31, 2017
    Inventors: Ralf Siemieniec, Oliver Blank, Franz Hirler, Michael Hutzler, David Laforet, Cedric Ouvrard, Li Juin Yip
  • Publication number: 20170236910
    Abstract: A method of manufacturing a power metal oxide semiconductor field effect transistor includes: forming a field electrode in a field plate trench in a main surface of a semiconductor substrate; forming a gate trench in the main surface, the gate trench extending in a first direction parallel to the main surface; and for a gate electrode in the gate trench, the gate electrode being made of a gate electrode material that comprises a metal. The field plate trench is formed to have an extension length in the first direction which is less than double of an extension length of the field plate trench in a second direction, the second direction being perpendicular to the first direction.
    Type: Application
    Filed: May 2, 2017
    Publication date: August 17, 2017
    Inventors: David Laforet, Oliver Blank, Michael Hutzler, Cedric Ouvrard, Ralf Siemieniec, Li Juin Yip
  • Patent number: 9728614
    Abstract: A semiconductor device is manufactured by forming a gate electrode adjacent to a body region in a semiconductor substrate, forming a field plate trench in a main surface of the substrate, the field plate trench having an extension length in a first direction parallel to the main surface, and forming a field electrode and a field dielectric layer in the field plate trench so that the field electrode is insulated from an adjacent drift zone by the field dielectric layer. The extension length of the field plate trench in the first direction is less than double an extension length of the field electrode in a second direction that is perpendicular to the first direction and is parallel to the main surface. The extension length in the first direction is more than half the extension length in the second direction.
    Type: Grant
    Filed: December 22, 2016
    Date of Patent: August 8, 2017
    Assignee: Infineon Technologies Austria AG
    Inventors: David Laforet, Oliver Blank, Franz Hirler, Ralf Siemieniec
  • Patent number: 9722036
    Abstract: According to an embodiment a semiconductor device includes a semiconductor body with a mesa section that may include a rectifying structure and a first drift zone section. The mesa section surrounds a field electrode structure that includes a field electrode and a field dielectric sandwiched between the field electrode and the semiconductor body. A maximum horizontal extension of the field electrode in a measure plane parallel to a first surface of the semiconductor body is at most 500 nm.
    Type: Grant
    Filed: August 28, 2015
    Date of Patent: August 1, 2017
    Assignee: Infineon Technologies Austria AG
    Inventors: Franz Hirler, Oliver Blank, Ralf Siemieniec
  • Patent number: 9680004
    Abstract: A power MOSFET includes a gate electrode in a gate trench in a main surface of a semiconductor substrate, the gate trench extending parallel to the main surface. The power MOSFET further includes a field electrode in a field plate trench in the main surface. The field plate trench has an extension length in a first direction which is less than double and more than half of an extension length of the field plate trench in a second direction perpendicular to the first direction, the first and the second directions being parallel to the main surface. The gate electrode includes a gate electrode material which comprises a metal.
    Type: Grant
    Filed: July 8, 2015
    Date of Patent: June 13, 2017
    Assignee: Infineon Technologies Austria AG
    Inventors: David Laforet, Oliver Blank, Michael Hutzler, Cedric Ouvrard, Ralf Siemieniec, Li Juin Yip
  • Publication number: 20170154965
    Abstract: A semiconductor device includes a semiconductor substrate including, between a bottom side and a top side, a first trench and a second trench extending in a vertical direction, and a contact groove arranged between the first trench and the second trench. The contact groove has a longitudinal extension in a plane perpendicular to the vertical direction. The longitudinal extension of the contact groove at least partially has a wave-shape.
    Type: Application
    Filed: November 25, 2016
    Publication date: June 1, 2017
    Inventors: Ralf Siemieniec, Oliver Blank, Marion Hoja, Christoph Kadow, Sabine Konrad, Cedric Ouvrard